1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "rk3588-vehicle-s66-v10.dtsi" 10*4882a593Smuzhiyun#include "rk3588-vehicle-adsp-audio-s66.dtsi" 11*4882a593Smuzhiyun#include "rk3588-vehicle-maxim-serdes-display-s66.dtsi" 12*4882a593Smuzhiyun#include "rk3588-vehicle-maxim-cameras-s66.dtsi" 13*4882a593Smuzhiyun#include "rk3588-android.dtsi" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "Rockchip RK3588 VEHICLE S66 Board V10"; 17*4882a593Smuzhiyun compatible = "rockchip,rk3588-vehicle-s66-v10", "rockchip,rk3588"; 18*4882a593Smuzhiyun}; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun&rockchip_suspend { 21*4882a593Smuzhiyun rockchip,sleep-mode-config = < 22*4882a593Smuzhiyun (0 23*4882a593Smuzhiyun | RKPM_SLP_ARMOFF_DDRPD 24*4882a593Smuzhiyun | RKPM_SLP_PMU_PMUALIVE_32K 25*4882a593Smuzhiyun | RKPM_SLP_PMU_DIS_OSC 26*4882a593Smuzhiyun | RKPM_SLP_32K_EXT 27*4882a593Smuzhiyun ) 28*4882a593Smuzhiyun >; 29*4882a593Smuzhiyun rockchip,wakeup-config = < 30*4882a593Smuzhiyun (0 31*4882a593Smuzhiyun | RKPM_GPIO_WKUP_EN 32*4882a593Smuzhiyun ) 33*4882a593Smuzhiyun >; 34*4882a593Smuzhiyun status = "okay"; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&vdd_log_s0 { 38*4882a593Smuzhiyun regulator-state-mem { 39*4882a593Smuzhiyun regulator-on-in-suspend; 40*4882a593Smuzhiyun regulator-suspend-microvolt = <800000>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&vcc_3v3_s0 { 45*4882a593Smuzhiyun regulator-state-mem { 46*4882a593Smuzhiyun regulator-on-in-suspend; 47*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&vcc_1v8_s0 { 52*4882a593Smuzhiyun regulator-state-mem { 53*4882a593Smuzhiyun regulator-on-in-suspend; 54*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun}; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun&vccio_sd_s0 { 59*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 60*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun&vdd_0v75_hdmi_edp_s0 { 64*4882a593Smuzhiyun regulator-min-microvolt = <837500>; 65*4882a593Smuzhiyun regulator-max-microvolt = <837500>; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun&vdd_cpu_big1_mem_s0 { 69*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 70*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun&vdd_cpu_big0_mem_s0 { 74*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 75*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun&vdd_cpu_lit_mem_s0 { 79*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 80*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 81*4882a593Smuzhiyun}; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun&vdd_gpu_mem_s0 { 84*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 85*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 86*4882a593Smuzhiyun regulator-state-mem { 87*4882a593Smuzhiyun regulator-on-in-suspend; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun}; 90