1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h" 8*4882a593Smuzhiyun#include "rk3588m.dtsi" 9*4882a593Smuzhiyun#include "rk3588-vehicle.dtsi" 10*4882a593Smuzhiyun#include "rk3588-rk806-single.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun es8388_sound: es8388-sound { 14*4882a593Smuzhiyun status = "disabled"; 15*4882a593Smuzhiyun compatible = "rockchip,multicodecs-card"; 16*4882a593Smuzhiyun rockchip,card-name = "rockchip-es8388"; 17*4882a593Smuzhiyun hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; 18*4882a593Smuzhiyun io-channels = <&saradc 3>; 19*4882a593Smuzhiyun io-channel-names = "adc-detect"; 20*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 21*4882a593Smuzhiyun poll-interval = <100>; 22*4882a593Smuzhiyun spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 23*4882a593Smuzhiyun hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 24*4882a593Smuzhiyun rockchip,format = "i2s"; 25*4882a593Smuzhiyun rockchip,mclk-fs = <256>; 26*4882a593Smuzhiyun rockchip,cpu = <&i2s0_8ch>; 27*4882a593Smuzhiyun rockchip,codec = <&es8388>; 28*4882a593Smuzhiyun rockchip,audio-routing = 29*4882a593Smuzhiyun "Headphone", "LOUT1", 30*4882a593Smuzhiyun "Headphone", "ROUT1", 31*4882a593Smuzhiyun "Speaker", "LOUT2", 32*4882a593Smuzhiyun "Speaker", "ROUT2", 33*4882a593Smuzhiyun "Headphone", "Headphone Power", 34*4882a593Smuzhiyun "Headphone", "Headphone Power", 35*4882a593Smuzhiyun "Speaker", "Speaker Power", 36*4882a593Smuzhiyun "Speaker", "Speaker Power", 37*4882a593Smuzhiyun "LINPUT1", "Main Mic", 38*4882a593Smuzhiyun "LINPUT2", "Main Mic", 39*4882a593Smuzhiyun "RINPUT1", "Headset Mic", 40*4882a593Smuzhiyun "RINPUT2", "Headset Mic"; 41*4882a593Smuzhiyun pinctrl-names = "default"; 42*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 43*4882a593Smuzhiyun play-pause-key { 44*4882a593Smuzhiyun label = "playpause"; 45*4882a593Smuzhiyun linux,code = <KEY_PLAYPAUSE>; 46*4882a593Smuzhiyun press-threshold-microvolt = <2000>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun fan: pwm-fan { 51*4882a593Smuzhiyun compatible = "pwm-fan"; 52*4882a593Smuzhiyun #cooling-cells = <2>; 53*4882a593Smuzhiyun pwms = <&pwm3 0 50000 0>; 54*4882a593Smuzhiyun cooling-levels = <0 50 100 150 200 255>; 55*4882a593Smuzhiyun rockchip,temp-trips = < 56*4882a593Smuzhiyun 50000 1 57*4882a593Smuzhiyun 55000 2 58*4882a593Smuzhiyun 60000 3 59*4882a593Smuzhiyun 65000 4 60*4882a593Smuzhiyun 70000 5 61*4882a593Smuzhiyun >; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun pcie20_avdd0v85: pcie20-avdd0v85 { 66*4882a593Smuzhiyun compatible = "regulator-fixed"; 67*4882a593Smuzhiyun regulator-name = "pcie20_avdd0v85"; 68*4882a593Smuzhiyun regulator-boot-on; 69*4882a593Smuzhiyun regulator-always-on; 70*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 71*4882a593Smuzhiyun regulator-max-microvolt = <850000>; 72*4882a593Smuzhiyun vin-supply = <&vdd_0v85_s0>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun pcie20_avdd1v8: pcie20-avdd1v8 { 76*4882a593Smuzhiyun compatible = "regulator-fixed"; 77*4882a593Smuzhiyun regulator-name = "pcie20_avdd1v8"; 78*4882a593Smuzhiyun regulator-boot-on; 79*4882a593Smuzhiyun regulator-always-on; 80*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 81*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 82*4882a593Smuzhiyun vin-supply = <&avcc_1v8_s0>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun pcie30_avdd0v75: pcie30-avdd0v75 { 86*4882a593Smuzhiyun compatible = "regulator-fixed"; 87*4882a593Smuzhiyun regulator-name = "pcie30_avdd0v75"; 88*4882a593Smuzhiyun regulator-boot-on; 89*4882a593Smuzhiyun regulator-always-on; 90*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 91*4882a593Smuzhiyun regulator-max-microvolt = <750000>; 92*4882a593Smuzhiyun vin-supply = <&avdd_0v75_s0>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun pcie30_avdd1v8: pcie30-avdd1v8 { 96*4882a593Smuzhiyun compatible = "regulator-fixed"; 97*4882a593Smuzhiyun regulator-name = "pcie30_avdd1v8"; 98*4882a593Smuzhiyun regulator-boot-on; 99*4882a593Smuzhiyun regulator-always-on; 100*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 101*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 102*4882a593Smuzhiyun vin-supply = <&avcc_1v8_s0>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 106*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 107*4882a593Smuzhiyun clocks = <&hym8563>; 108*4882a593Smuzhiyun clock-names = "ext_clock"; 109*4882a593Smuzhiyun pinctrl-names = "default"; 110*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 111*4882a593Smuzhiyun /* 112*4882a593Smuzhiyun * On the module itself this is one of these (depending 113*4882a593Smuzhiyun * on the actual card populated): 114*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 115*4882a593Smuzhiyun * - PDN (power down when low) 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun post-power-on-delay-ms = <200>; 118*4882a593Smuzhiyun reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; 119*4882a593Smuzhiyun status = "disabled"; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun rk_headset: rk-headset { 123*4882a593Smuzhiyun status = "disabled"; 124*4882a593Smuzhiyun compatible = "rockchip_headset"; 125*4882a593Smuzhiyun headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 126*4882a593Smuzhiyun pinctrl-names = "default"; 127*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 128*4882a593Smuzhiyun io-channels = <&saradc 3>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { 133*4882a593Smuzhiyun compatible = "regulator-fixed"; 134*4882a593Smuzhiyun regulator-name = "vcc_1v1_nldo_s3"; 135*4882a593Smuzhiyun regulator-always-on; 136*4882a593Smuzhiyun regulator-boot-on; 137*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 138*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 139*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun vcc3v3_lcd_n: vcc3v3-lcd0-n { 143*4882a593Smuzhiyun compatible = "regulator-fixed"; 144*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd0_n"; 145*4882a593Smuzhiyun regulator-boot-on; 146*4882a593Smuzhiyun enable-active-high; 147*4882a593Smuzhiyun gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; 148*4882a593Smuzhiyun vin-supply = <&vcc_1v8_s0>; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun vcc5v0_otg: vcc5v0-otg { 152*4882a593Smuzhiyun compatible = "regulator-fixed"; 153*4882a593Smuzhiyun regulator-name = "vcc5v0_otg"; 154*4882a593Smuzhiyun regulator-boot-on; 155*4882a593Smuzhiyun regulator-always-on; 156*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 157*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 158*4882a593Smuzhiyun enable-active-high; 159*4882a593Smuzhiyun gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; 160*4882a593Smuzhiyun vin-supply = <&vcc5v0_usb>; 161*4882a593Smuzhiyun pinctrl-names = "default"; 162*4882a593Smuzhiyun pinctrl-0 = <&vcc5v0_otg_en>; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun vcc5v0_host: vcc5v0-host { 166*4882a593Smuzhiyun compatible = "regulator-fixed"; 167*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 168*4882a593Smuzhiyun regulator-boot-on; 169*4882a593Smuzhiyun regulator-always-on; 170*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 171*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 172*4882a593Smuzhiyun enable-active-high; 173*4882a593Smuzhiyun gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; 174*4882a593Smuzhiyun vin-supply = <&vcc5v0_usb>; 175*4882a593Smuzhiyun pinctrl-names = "default"; 176*4882a593Smuzhiyun pinctrl-0 = <&vcc5v0_host_en>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun wireless_bluetooth: wireless-bluetooth { 180*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 181*4882a593Smuzhiyun clocks = <&hym8563>; 182*4882a593Smuzhiyun clock-names = "ext_clock"; 183*4882a593Smuzhiyun uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; 184*4882a593Smuzhiyun pinctrl-names = "default", "rts_gpio"; 185*4882a593Smuzhiyun pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; 186*4882a593Smuzhiyun pinctrl-1 = <&uart9_gpios>; 187*4882a593Smuzhiyun BT,reset_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; 188*4882a593Smuzhiyun BT,wake_gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; 189*4882a593Smuzhiyun BT,wake_host_irq = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; 190*4882a593Smuzhiyun status = "okay"; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun wireless_wlan: wireless-wlan { 194*4882a593Smuzhiyun compatible = "wlan-platdata"; 195*4882a593Smuzhiyun wifi_chip_type = "ap6398s"; 196*4882a593Smuzhiyun pinctrl-names = "default"; 197*4882a593Smuzhiyun pinctrl-0 = <&wifi_host_wake_irq>; 198*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; 199*4882a593Smuzhiyun WIFI,poweren_gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; 200*4882a593Smuzhiyun status = "okay"; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun dummy_codec: dummy-codec { 204*4882a593Smuzhiyun status = "okay"; 205*4882a593Smuzhiyun compatible = "rockchip,dummy-codec"; 206*4882a593Smuzhiyun #sound-dai-cells = <0>; 207*4882a593Smuzhiyun pinctrl-names = "default"; 208*4882a593Smuzhiyun pinctrl-0 = <&rk3308_reset>; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun car_rk3308_sound: car-rk3308-sound { 212*4882a593Smuzhiyun status = "okay"; 213*4882a593Smuzhiyun compatible = "simple-audio-card"; 214*4882a593Smuzhiyun simple-audio-card,name = "rockchip,car-rk3308-sound"; 215*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 216*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 217*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&codec_master>; 218*4882a593Smuzhiyun simple-audio-card,frame-master = <&codec_master>; 219*4882a593Smuzhiyun simple-audio-card,cpu { 220*4882a593Smuzhiyun sound-dai = <&i2s0_8ch>; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun codec_master: simple-audio-card,codec { 223*4882a593Smuzhiyun sound-dai = <&dummy_codec>; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&backlight { 229*4882a593Smuzhiyun pwms = <&pwm1 0 25000 0>; 230*4882a593Smuzhiyun status = "okay"; 231*4882a593Smuzhiyun}; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun&combphy0_ps { 234*4882a593Smuzhiyun status = "okay"; 235*4882a593Smuzhiyun}; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun&combphy1_ps { 238*4882a593Smuzhiyun status = "okay"; 239*4882a593Smuzhiyun}; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun&combphy2_psu { 242*4882a593Smuzhiyun status = "okay"; 243*4882a593Smuzhiyun}; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun&gmac1 { 246*4882a593Smuzhiyun /* Use rgmii-rxid mode to disable rx delay inside Soc */ 247*4882a593Smuzhiyun phy-mode = "rgmii-rxid"; 248*4882a593Smuzhiyun clock_in_out = "output"; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 251*4882a593Smuzhiyun snps,reset-active-low; 252*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 253*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun pinctrl-names = "default"; 256*4882a593Smuzhiyun pinctrl-0 = <&gmac1_miim 257*4882a593Smuzhiyun &gmac1_tx_bus2 258*4882a593Smuzhiyun &gmac1_rx_bus2 259*4882a593Smuzhiyun &gmac1_rgmii_clk 260*4882a593Smuzhiyun &gmac1_rgmii_bus>; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun tx_delay = <0x43>; 263*4882a593Smuzhiyun /* rx_delay = <0x3f>; */ 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun phy-handle = <&rgmii_phy>; 266*4882a593Smuzhiyun status = "disabled"; 267*4882a593Smuzhiyun}; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun&hdmi0 { 270*4882a593Smuzhiyun enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 271*4882a593Smuzhiyun status = "okay"; 272*4882a593Smuzhiyun}; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun&hdmi0_in_vp0 { 275*4882a593Smuzhiyun status = "okay"; 276*4882a593Smuzhiyun}; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun&hdmi0_sound { 279*4882a593Smuzhiyun status = "okay"; 280*4882a593Smuzhiyun}; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun&hdmi1 { 283*4882a593Smuzhiyun enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 284*4882a593Smuzhiyun status = "okay"; 285*4882a593Smuzhiyun}; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun&hdmi1_in_vp0 { 288*4882a593Smuzhiyun status = "okay"; 289*4882a593Smuzhiyun}; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun&hdmi1_sound { 292*4882a593Smuzhiyun status = "okay"; 293*4882a593Smuzhiyun}; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun&hdptxphy_hdmi0 { 297*4882a593Smuzhiyun status = "okay"; 298*4882a593Smuzhiyun}; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun&hdptxphy_hdmi1 { 301*4882a593Smuzhiyun status = "okay"; 302*4882a593Smuzhiyun}; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun&i2c0 { 305*4882a593Smuzhiyun status = "okay"; 306*4882a593Smuzhiyun pinctrl-names = "default"; 307*4882a593Smuzhiyun pinctrl-0 = <&i2c0m2_xfer>; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { 310*4882a593Smuzhiyun compatible = "rockchip,rk8602"; 311*4882a593Smuzhiyun reg = <0x42>; 312*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 313*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 314*4882a593Smuzhiyun regulator-name = "vdd_cpu_big0_s0"; 315*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 316*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 317*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 318*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 319*4882a593Smuzhiyun regulator-boot-on; 320*4882a593Smuzhiyun regulator-always-on; 321*4882a593Smuzhiyun regulator-state-mem { 322*4882a593Smuzhiyun regulator-off-in-suspend; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { 327*4882a593Smuzhiyun compatible = "rockchip,rk8603"; 328*4882a593Smuzhiyun reg = <0x43>; 329*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 330*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 331*4882a593Smuzhiyun regulator-name = "vdd_cpu_big1_s0"; 332*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 333*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 334*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 335*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 336*4882a593Smuzhiyun regulator-boot-on; 337*4882a593Smuzhiyun regulator-always-on; 338*4882a593Smuzhiyun regulator-state-mem { 339*4882a593Smuzhiyun regulator-off-in-suspend; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun}; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun&i2c1 { 345*4882a593Smuzhiyun status = "okay"; 346*4882a593Smuzhiyun pinctrl-names = "default"; 347*4882a593Smuzhiyun pinctrl-0 = <&i2c1m2_xfer>; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { 350*4882a593Smuzhiyun compatible = "rockchip,rk8602"; 351*4882a593Smuzhiyun reg = <0x42>; 352*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 353*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 354*4882a593Smuzhiyun regulator-name = "vdd_npu_s0"; 355*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 356*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 357*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 358*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 359*4882a593Smuzhiyun regulator-boot-on; 360*4882a593Smuzhiyun regulator-always-on; 361*4882a593Smuzhiyun regulator-state-mem { 362*4882a593Smuzhiyun regulator-off-in-suspend; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun}; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun&i2c4 { 368*4882a593Smuzhiyun status = "okay"; 369*4882a593Smuzhiyun pinctrl-0 = <&i2c4m2_xfer>; 370*4882a593Smuzhiyun hym8563: hym8563@51 { 371*4882a593Smuzhiyun compatible = "haoyu,hym8563"; 372*4882a593Smuzhiyun reg = <0x51>; 373*4882a593Smuzhiyun #clock-cells = <0>; 374*4882a593Smuzhiyun clock-frequency = <32768>; 375*4882a593Smuzhiyun clock-output-names = "hym8563"; 376*4882a593Smuzhiyun pinctrl-names = "default"; 377*4882a593Smuzhiyun pinctrl-0 = <&hym8563_int>; 378*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 379*4882a593Smuzhiyun interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 380*4882a593Smuzhiyun wakeup-source; 381*4882a593Smuzhiyun }; 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun}; 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun&i2c5 { 386*4882a593Smuzhiyun status = "okay"; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun}; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun&i2c6 { 391*4882a593Smuzhiyun status = "okay"; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun}; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun&i2c7 { 396*4882a593Smuzhiyun status = "okay"; 397*4882a593Smuzhiyun es8388: es8388@11 { 398*4882a593Smuzhiyun status = "okay"; 399*4882a593Smuzhiyun #sound-dai-cells = <0>; 400*4882a593Smuzhiyun compatible = "everest,es8388", "everest,es8323"; 401*4882a593Smuzhiyun reg = <0x11>; 402*4882a593Smuzhiyun clocks = <&mclkout_i2s0>; 403*4882a593Smuzhiyun clock-names = "mclk"; 404*4882a593Smuzhiyun assigned-clocks = <&mclkout_i2s0>; 405*4882a593Smuzhiyun assigned-clock-rates = <12288000>; 406*4882a593Smuzhiyun pinctrl-names = "default"; 407*4882a593Smuzhiyun pinctrl-0 = <&i2s0_mclk>; 408*4882a593Smuzhiyun }; 409*4882a593Smuzhiyun}; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun&i2s0_8ch { 412*4882a593Smuzhiyun status = "okay"; 413*4882a593Smuzhiyun pinctrl-names = "default"; 414*4882a593Smuzhiyun pinctrl-0 = <&i2s0_lrck 415*4882a593Smuzhiyun &i2s0_sclk 416*4882a593Smuzhiyun &i2s0_sdi0 417*4882a593Smuzhiyun &i2s0_sdi1 418*4882a593Smuzhiyun &i2s0_sdo0 419*4882a593Smuzhiyun &i2s0_sdo1 420*4882a593Smuzhiyun &i2s0_sdo2 421*4882a593Smuzhiyun &i2s0_sdo3>; 422*4882a593Smuzhiyun}; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun&i2s5_8ch { 425*4882a593Smuzhiyun status = "okay"; 426*4882a593Smuzhiyun}; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun&i2s6_8ch { 429*4882a593Smuzhiyun status = "okay"; 430*4882a593Smuzhiyun}; 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun&i2s7_8ch { 433*4882a593Smuzhiyun status = "okay"; 434*4882a593Smuzhiyun}; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun&mdio1 { 437*4882a593Smuzhiyun rgmii_phy: phy@1 { 438*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 439*4882a593Smuzhiyun reg = <0x1>; 440*4882a593Smuzhiyun }; 441*4882a593Smuzhiyun}; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun&pcie2x1l0 { 444*4882a593Smuzhiyun reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; 445*4882a593Smuzhiyun status = "disabled"; 446*4882a593Smuzhiyun}; 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun&pcie2x1l2 { 449*4882a593Smuzhiyun reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; 450*4882a593Smuzhiyun rockchip,skip-scan-in-resume; 451*4882a593Smuzhiyun pinctrl-names = "default"; 452*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 453*4882a593Smuzhiyun status = "okay"; 454*4882a593Smuzhiyun}; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun&pcie30phy { 457*4882a593Smuzhiyun rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>; 458*4882a593Smuzhiyun status = "disabled"; 459*4882a593Smuzhiyun}; 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun&pcie3x4 { 462*4882a593Smuzhiyun reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; 463*4882a593Smuzhiyun status = "disabled"; 464*4882a593Smuzhiyun}; 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun&pinctrl { 467*4882a593Smuzhiyun cam { 468*4882a593Smuzhiyun mipicsi0_pwr: mipicsi0-pwr { 469*4882a593Smuzhiyun rockchip,pins = 470*4882a593Smuzhiyun /* camera power en */ 471*4882a593Smuzhiyun <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 472*4882a593Smuzhiyun }; 473*4882a593Smuzhiyun mipicsi1_pwr: mipicsi1-pwr { 474*4882a593Smuzhiyun rockchip,pins = 475*4882a593Smuzhiyun /* camera power en */ 476*4882a593Smuzhiyun <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 477*4882a593Smuzhiyun }; 478*4882a593Smuzhiyun mipidcphy0_pwr: mipidcphy0-pwr { 479*4882a593Smuzhiyun rockchip,pins = 480*4882a593Smuzhiyun /* camera power en */ 481*4882a593Smuzhiyun <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 482*4882a593Smuzhiyun }; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun 485*4882a593Smuzhiyun headphone { 486*4882a593Smuzhiyun hp_det: hp-det { 487*4882a593Smuzhiyun rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 488*4882a593Smuzhiyun }; 489*4882a593Smuzhiyun }; 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun hym8563 { 492*4882a593Smuzhiyun hym8563_int: hym8563-int { 493*4882a593Smuzhiyun rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun lcd { 498*4882a593Smuzhiyun lcd_rst_gpio: lcd-rst-gpio { 499*4882a593Smuzhiyun rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 500*4882a593Smuzhiyun }; 501*4882a593Smuzhiyun }; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun sdio-pwrseq { 504*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 505*4882a593Smuzhiyun rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 506*4882a593Smuzhiyun }; 507*4882a593Smuzhiyun }; 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun touch { 510*4882a593Smuzhiyun touch_gpio: touch-gpio { 511*4882a593Smuzhiyun rockchip,pins = 512*4882a593Smuzhiyun <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, 513*4882a593Smuzhiyun <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun }; 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun usb { 518*4882a593Smuzhiyun vcc5v0_otg_en: vcc5v0-otg-en { 519*4882a593Smuzhiyun rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun vcc5v0_host_en: vcc5v0-host-en { 523*4882a593Smuzhiyun rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 524*4882a593Smuzhiyun }; 525*4882a593Smuzhiyun }; 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun wireless-bluetooth { 529*4882a593Smuzhiyun uart9_gpios: uart9-gpios { 530*4882a593Smuzhiyun rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 531*4882a593Smuzhiyun }; 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun bt_reset_gpio: bt-reset-gpio { 534*4882a593Smuzhiyun rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; 535*4882a593Smuzhiyun }; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun bt_wake_gpio: bt-wake-gpio { 538*4882a593Smuzhiyun rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 539*4882a593Smuzhiyun }; 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun bt_irq_gpio: bt-irq-gpio { 542*4882a593Smuzhiyun rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 543*4882a593Smuzhiyun }; 544*4882a593Smuzhiyun }; 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun wireless-wlan { 547*4882a593Smuzhiyun wifi_host_wake_irq: wifi-host-wake-irq { 548*4882a593Smuzhiyun rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; 549*4882a593Smuzhiyun }; 550*4882a593Smuzhiyun }; 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun rk3308 { 553*4882a593Smuzhiyun rk3308_reset: rk3308-reset { 554*4882a593Smuzhiyun rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; 555*4882a593Smuzhiyun }; 556*4882a593Smuzhiyun }; 557*4882a593Smuzhiyun}; 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun&pwm1 { 560*4882a593Smuzhiyun status = "okay"; 561*4882a593Smuzhiyun}; 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun&pwm3 { 564*4882a593Smuzhiyun pinctrl-0 = <&pwm3m1_pins>; 565*4882a593Smuzhiyun status = "okay"; 566*4882a593Smuzhiyun}; 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun&route_dsi0 { 569*4882a593Smuzhiyun status = "okay"; 570*4882a593Smuzhiyun connect = <&vp3_out_dsi0>; 571*4882a593Smuzhiyun}; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun&route_dsi1 { 574*4882a593Smuzhiyun status = "disabled"; 575*4882a593Smuzhiyun connect = <&vp3_out_dsi1>; 576*4882a593Smuzhiyun}; 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun&route_hdmi0 { 579*4882a593Smuzhiyun status = "okay"; 580*4882a593Smuzhiyun}; 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun&route_hdmi1 { 583*4882a593Smuzhiyun status = "okay"; 584*4882a593Smuzhiyun}; 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun&sata0 { 587*4882a593Smuzhiyun status = "okay"; 588*4882a593Smuzhiyun}; 589*4882a593Smuzhiyun 590*4882a593Smuzhiyun&sdio { 591*4882a593Smuzhiyun max-frequency = <150000000>; 592*4882a593Smuzhiyun no-sd; 593*4882a593Smuzhiyun no-mmc; 594*4882a593Smuzhiyun bus-width = <4>; 595*4882a593Smuzhiyun disable-wp; 596*4882a593Smuzhiyun cap-sd-highspeed; 597*4882a593Smuzhiyun cap-sdio-irq; 598*4882a593Smuzhiyun keep-power-in-suspend; 599*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 600*4882a593Smuzhiyun non-removable; 601*4882a593Smuzhiyun pinctrl-names = "default"; 602*4882a593Smuzhiyun pinctrl-0 = <&sdiom0_pins>; 603*4882a593Smuzhiyun sd-uhs-sdr104; 604*4882a593Smuzhiyun status = "disabled"; 605*4882a593Smuzhiyun}; 606*4882a593Smuzhiyun 607*4882a593Smuzhiyun&sdmmc { 608*4882a593Smuzhiyun status = "disabled"; 609*4882a593Smuzhiyun}; 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun&uart9 { 612*4882a593Smuzhiyun status = "okay"; 613*4882a593Smuzhiyun pinctrl-names = "default"; 614*4882a593Smuzhiyun pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; 615*4882a593Smuzhiyun}; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun&u2phy0_otg { 618*4882a593Smuzhiyun status = "okay"; 619*4882a593Smuzhiyun}; 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun&u2phy1_otg { 622*4882a593Smuzhiyun phy-supply = <&vcc5v0_otg>; 623*4882a593Smuzhiyun}; 624*4882a593Smuzhiyun 625*4882a593Smuzhiyun&u2phy2_host { 626*4882a593Smuzhiyun phy-supply = <&vcc5v0_otg>; 627*4882a593Smuzhiyun}; 628*4882a593Smuzhiyun 629*4882a593Smuzhiyun&u2phy3_host { 630*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 631*4882a593Smuzhiyun}; 632*4882a593Smuzhiyun 633*4882a593Smuzhiyun&usbdp_phy0 { 634*4882a593Smuzhiyun rockchip,dp-lane-mux = <2 3>; 635*4882a593Smuzhiyun status = "okay"; 636*4882a593Smuzhiyun}; 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun&usbdp_phy0_dp { 639*4882a593Smuzhiyun status = "okay"; 640*4882a593Smuzhiyun}; 641*4882a593Smuzhiyun 642*4882a593Smuzhiyun&usbdp_phy0_u3 { 643*4882a593Smuzhiyun status = "okay"; 644*4882a593Smuzhiyun}; 645*4882a593Smuzhiyun 646*4882a593Smuzhiyun&usbdp_phy1 { 647*4882a593Smuzhiyun rockchip,dp-lane-mux = <3 2 1 0>; 648*4882a593Smuzhiyun status = "okay"; 649*4882a593Smuzhiyun}; 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun&usbdp_phy1_dp { 652*4882a593Smuzhiyun status = "okay"; 653*4882a593Smuzhiyun}; 654*4882a593Smuzhiyun 655*4882a593Smuzhiyun&usbdp_phy1_u3 { 656*4882a593Smuzhiyun maximum-speed = "high-speed"; 657*4882a593Smuzhiyun status = "okay"; 658*4882a593Smuzhiyun}; 659*4882a593Smuzhiyun 660*4882a593Smuzhiyun&usbdrd_dwc3_0 { 661*4882a593Smuzhiyun dr_mode = "peripheral"; 662*4882a593Smuzhiyun maximum-speed = "high-speed"; 663*4882a593Smuzhiyun extcon = <&u2phy0>; 664*4882a593Smuzhiyun status = "okay"; 665*4882a593Smuzhiyun}; 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun&usbdrd_dwc3_1 { 668*4882a593Smuzhiyun dr_mode = "host"; 669*4882a593Smuzhiyun maximum-speed = "high-speed"; 670*4882a593Smuzhiyun snps,dis_u2_susphy_quirk; 671*4882a593Smuzhiyun status = "okay"; 672*4882a593Smuzhiyun}; 673