xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h"
8*4882a593Smuzhiyun#include "rk3588m.dtsi"
9*4882a593Smuzhiyun#include "rk3588-vehicle-v20.dtsi"
10*4882a593Smuzhiyun#include "rk3588-rk806-dual.dtsi"
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	pcie20_avdd0v85: pcie20-avdd0v85 {
13*4882a593Smuzhiyun		compatible = "regulator-fixed";
14*4882a593Smuzhiyun		regulator-name = "pcie20_avdd0v85";
15*4882a593Smuzhiyun		regulator-boot-on;
16*4882a593Smuzhiyun		regulator-always-on;
17*4882a593Smuzhiyun		regulator-min-microvolt = <850000>;
18*4882a593Smuzhiyun		regulator-max-microvolt = <850000>;
19*4882a593Smuzhiyun		vin-supply = <&vdd_0v85_s0>;
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	pcie20_avdd1v8: pcie20-avdd1v8 {
23*4882a593Smuzhiyun		compatible = "regulator-fixed";
24*4882a593Smuzhiyun		regulator-name = "pcie20_avdd1v8";
25*4882a593Smuzhiyun		regulator-boot-on;
26*4882a593Smuzhiyun		regulator-always-on;
27*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
28*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
29*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	pcie30_avdd0v75: pcie30-avdd0v75 {
33*4882a593Smuzhiyun		compatible = "regulator-fixed";
34*4882a593Smuzhiyun		regulator-name = "pcie30_avdd0v75";
35*4882a593Smuzhiyun		regulator-boot-on;
36*4882a593Smuzhiyun		regulator-always-on;
37*4882a593Smuzhiyun		regulator-min-microvolt = <750000>;
38*4882a593Smuzhiyun		regulator-max-microvolt = <750000>;
39*4882a593Smuzhiyun		vin-supply = <&avdd_0v75_s0>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	pcie30_avdd1v8: pcie30-avdd1v8 {
43*4882a593Smuzhiyun		compatible = "regulator-fixed";
44*4882a593Smuzhiyun		regulator-name = "pcie30_avdd1v8";
45*4882a593Smuzhiyun		regulator-boot-on;
46*4882a593Smuzhiyun		regulator-always-on;
47*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
48*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
49*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
50*4882a593Smuzhiyun	};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
53*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
54*4882a593Smuzhiyun		clocks = <&hym8563>;
55*4882a593Smuzhiyun		clock-names = "ext_clock";
56*4882a593Smuzhiyun		pinctrl-names = "default";
57*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
58*4882a593Smuzhiyun		/*
59*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
60*4882a593Smuzhiyun		 * on the actual card populated):
61*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
62*4882a593Smuzhiyun		 * - PDN (power down when low)
63*4882a593Smuzhiyun		 */
64*4882a593Smuzhiyun		post-power-on-delay-ms = <10>;
65*4882a593Smuzhiyun		reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;
66*4882a593Smuzhiyun		status = "okay";
67*4882a593Smuzhiyun	};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	fan: pwm-fan {
70*4882a593Smuzhiyun		compatible = "pwm-fan";
71*4882a593Smuzhiyun		#cooling-cells = <2>;
72*4882a593Smuzhiyun		pwms = <&pwm8 0 50000 0>;
73*4882a593Smuzhiyun		cooling-levels = <0 50 100 150 200 255>;
74*4882a593Smuzhiyun		rockchip,temp-trips = <
75*4882a593Smuzhiyun			50000	1
76*4882a593Smuzhiyun			55000	2
77*4882a593Smuzhiyun			60000	3
78*4882a593Smuzhiyun			65000	4
79*4882a593Smuzhiyun			70000	5
80*4882a593Smuzhiyun		>;
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host {
84*4882a593Smuzhiyun		compatible = "regulator-fixed";
85*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
86*4882a593Smuzhiyun		regulator-boot-on;
87*4882a593Smuzhiyun		regulator-always-on;
88*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
89*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
90*4882a593Smuzhiyun		enable-active-high;
91*4882a593Smuzhiyun		gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
92*4882a593Smuzhiyun		vin-supply = <&vcc5v0_usb>;
93*4882a593Smuzhiyun		pinctrl-names = "default";
94*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en>;
95*4882a593Smuzhiyun	};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun	wireless_bluetooth: wireless-bluetooth {
98*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
99*4882a593Smuzhiyun		clocks = <&hym8563>;
100*4882a593Smuzhiyun		clock-names = "ext_clock";
101*4882a593Smuzhiyun		uart_rts_gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
102*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
103*4882a593Smuzhiyun		pinctrl-0 = <&uart9m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>;
104*4882a593Smuzhiyun		pinctrl-1 = <&uart9_gpios>;
105*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
106*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
107*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
108*4882a593Smuzhiyun		status = "okay";
109*4882a593Smuzhiyun	};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun	wireless_wlan: wireless-wlan {
112*4882a593Smuzhiyun		compatible = "wlan-platdata";
113*4882a593Smuzhiyun		wifi_chip_type = "ap6398s";
114*4882a593Smuzhiyun		pinctrl-names = "default";
115*4882a593Smuzhiyun		pinctrl-0 = <&wifi_host_wake_irq>;
116*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
117*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
118*4882a593Smuzhiyun		status = "okay";
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	dummy_codec: dummy-codec {
122*4882a593Smuzhiyun		status = "okay";
123*4882a593Smuzhiyun		compatible = "rockchip,dummy-codec";
124*4882a593Smuzhiyun		#sound-dai-cells = <0>;
125*4882a593Smuzhiyun		pinctrl-names = "default";
126*4882a593Smuzhiyun		pinctrl-0 = <&rk3308_reset>;
127*4882a593Smuzhiyun	};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun	car_rk3308_sound: car-rk3308-sound {
130*4882a593Smuzhiyun		status = "okay";
131*4882a593Smuzhiyun		compatible = "simple-audio-card";
132*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,car-rk3308-sound";
133*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
134*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
135*4882a593Smuzhiyun		simple-audio-card,bitclock-master = <&codec_master>;
136*4882a593Smuzhiyun		simple-audio-card,frame-master = <&codec_master>;
137*4882a593Smuzhiyun		simple-audio-card,cpu {
138*4882a593Smuzhiyun			sound-dai = <&i2s0_8ch>;
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun		codec_master: simple-audio-card,codec {
141*4882a593Smuzhiyun			sound-dai = <&dummy_codec>;
142*4882a593Smuzhiyun		};
143*4882a593Smuzhiyun	};
144*4882a593Smuzhiyun};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun&combphy0_ps {
147*4882a593Smuzhiyun	status = "okay";
148*4882a593Smuzhiyun};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&combphy1_ps {
151*4882a593Smuzhiyun	status = "okay";
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&combphy2_psu {
155*4882a593Smuzhiyun	status = "okay";
156*4882a593Smuzhiyun};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun&gmac0 {
159*4882a593Smuzhiyun	/* Use rgmii-rxid mode to disable rx delay inside Soc */
160*4882a593Smuzhiyun	phy-mode = "rgmii-rxid";
161*4882a593Smuzhiyun	clock_in_out = "output";
162*4882a593Smuzhiyun	snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
163*4882a593Smuzhiyun	snps,reset-active-low;
164*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
165*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
166*4882a593Smuzhiyun	pinctrl-names = "default";
167*4882a593Smuzhiyun	pinctrl-0 = <&gmac0_miim
168*4882a593Smuzhiyun		     &gmac0_tx_bus2
169*4882a593Smuzhiyun		     &gmac0_rx_bus2
170*4882a593Smuzhiyun		     &gmac0_rgmii_clk
171*4882a593Smuzhiyun		     &gmac0_rgmii_bus
172*4882a593Smuzhiyun		     &phydisb>;
173*4882a593Smuzhiyun	tx_delay = <0x43>;
174*4882a593Smuzhiyun	//rx_delay = <0x3f>;
175*4882a593Smuzhiyun	phy-handle = <&rgmii_phy>;
176*4882a593Smuzhiyun	status = "okay";
177*4882a593Smuzhiyun};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun&i2c4 {
180*4882a593Smuzhiyun	status = "okay";
181*4882a593Smuzhiyun	pinctrl-0 = <&i2c4m2_xfer>;
182*4882a593Smuzhiyun	hym8563: hym8563@51 {
183*4882a593Smuzhiyun		compatible = "haoyu,hym8563";
184*4882a593Smuzhiyun		reg = <0x51>;
185*4882a593Smuzhiyun		#clock-cells = <0>;
186*4882a593Smuzhiyun		clock-frequency = <32768>;
187*4882a593Smuzhiyun		clock-output-names = "hym8563";
188*4882a593Smuzhiyun		pinctrl-names = "default";
189*4882a593Smuzhiyun		pinctrl-0 = <&hym8563_int>;
190*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
191*4882a593Smuzhiyun		interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
192*4882a593Smuzhiyun		wakeup-source;
193*4882a593Smuzhiyun	};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun};
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun&i2s0_8ch {
198*4882a593Smuzhiyun	status = "okay";
199*4882a593Smuzhiyun	pinctrl-names = "default";
200*4882a593Smuzhiyun	pinctrl-0 = <&i2s0_lrck
201*4882a593Smuzhiyun		     &i2s0_sclk
202*4882a593Smuzhiyun		     &i2s0_sdi0
203*4882a593Smuzhiyun		     &i2s0_sdi1
204*4882a593Smuzhiyun		     &i2s0_sdo0
205*4882a593Smuzhiyun		     &i2s0_sdo1
206*4882a593Smuzhiyun		     &i2s0_sdo2
207*4882a593Smuzhiyun		     &i2s0_sdo3>;
208*4882a593Smuzhiyun};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun&mdio0 {
211*4882a593Smuzhiyun	rgmii_phy: phy@1 {
212*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
213*4882a593Smuzhiyun		reg = <0x1>;
214*4882a593Smuzhiyun	};
215*4882a593Smuzhiyun};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&pcie2x1l0 {
218*4882a593Smuzhiyun	reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
219*4882a593Smuzhiyun	rockchip,skip-scan-in-resume;
220*4882a593Smuzhiyun	pinctrl-names = "default";
221*4882a593Smuzhiyun	pinctrl-0 = <&wifi_enable_h>;
222*4882a593Smuzhiyun	status = "disabled";
223*4882a593Smuzhiyun};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun&pcie2x1l2 {
226*4882a593Smuzhiyun	reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
227*4882a593Smuzhiyun	status = "disabled";
228*4882a593Smuzhiyun};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun&pinctrl {
231*4882a593Smuzhiyun	gmac0 {
232*4882a593Smuzhiyun		phydisb: phydisb {
233*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_high>;
234*4882a593Smuzhiyun		};
235*4882a593Smuzhiyun	};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun	hym8563 {
238*4882a593Smuzhiyun		hym8563_int: hym8563-int {
239*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
240*4882a593Smuzhiyun		};
241*4882a593Smuzhiyun	};
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun	sdio-pwrseq {
244*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
245*4882a593Smuzhiyun			rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
246*4882a593Smuzhiyun		};
247*4882a593Smuzhiyun	};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun	usb {
250*4882a593Smuzhiyun		vcc5v0_host_en: vcc5v0-host-en {
251*4882a593Smuzhiyun			rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
252*4882a593Smuzhiyun		};
253*4882a593Smuzhiyun	};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun	wireless-bluetooth {
257*4882a593Smuzhiyun		uart9_gpios: uart9-gpios {
258*4882a593Smuzhiyun			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
259*4882a593Smuzhiyun		};
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun		bt_reset_gpio: bt-reset-gpio {
262*4882a593Smuzhiyun			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
263*4882a593Smuzhiyun		};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun		bt_wake_gpio: bt-wake-gpio {
266*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
267*4882a593Smuzhiyun		};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun		bt_irq_gpio: bt-irq-gpio {
270*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
271*4882a593Smuzhiyun		};
272*4882a593Smuzhiyun	};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun	wireless-wlan {
275*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
276*4882a593Smuzhiyun			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
277*4882a593Smuzhiyun		};
278*4882a593Smuzhiyun	};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun	rk3308 {
281*4882a593Smuzhiyun		rk3308_reset: rk3308-reset {
282*4882a593Smuzhiyun			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
283*4882a593Smuzhiyun		};
284*4882a593Smuzhiyun	};
285*4882a593Smuzhiyun};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun&pwm0 {
288*4882a593Smuzhiyun	pinctrl-0 = <&pwm0m2_pins>;
289*4882a593Smuzhiyun	status = "okay";
290*4882a593Smuzhiyun};
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun&pwm1 {
293*4882a593Smuzhiyun	pinctrl-0 = <&pwm1m2_pins>;
294*4882a593Smuzhiyun	status = "okay";
295*4882a593Smuzhiyun};
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun&pwm8 {
298*4882a593Smuzhiyun	pinctrl-0 = <&pwm8m1_pins>;
299*4882a593Smuzhiyun	status = "okay";
300*4882a593Smuzhiyun};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun&sata0 {
303*4882a593Smuzhiyun	status = "okay";
304*4882a593Smuzhiyun};
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun&sdio {
307*4882a593Smuzhiyun	max-frequency = <150000000>;
308*4882a593Smuzhiyun	no-sd;
309*4882a593Smuzhiyun	no-mmc;
310*4882a593Smuzhiyun	bus-width = <4>;
311*4882a593Smuzhiyun	disable-wp;
312*4882a593Smuzhiyun	cap-sd-highspeed;
313*4882a593Smuzhiyun	cap-sdio-irq;
314*4882a593Smuzhiyun	keep-power-in-suspend;
315*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
316*4882a593Smuzhiyun	non-removable;
317*4882a593Smuzhiyun	pinctrl-names = "default";
318*4882a593Smuzhiyun	pinctrl-0 = <&sdiom1_pins>;
319*4882a593Smuzhiyun	status = "okay";
320*4882a593Smuzhiyun};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun&sdmmc {
323*4882a593Smuzhiyun	status = "disabled";
324*4882a593Smuzhiyun};
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun&uart9 {
327*4882a593Smuzhiyun	status = "okay";
328*4882a593Smuzhiyun	pinctrl-names = "default";
329*4882a593Smuzhiyun	pinctrl-0 = <&uart9m1_xfer &uart9m1_ctsn>;
330*4882a593Smuzhiyun};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun&u2phy1_otg {
333*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
334*4882a593Smuzhiyun};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun&u2phy2_host {
337*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
338*4882a593Smuzhiyun};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun&u2phy3_host {
341*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
342*4882a593Smuzhiyun};
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun&usbdp_phy0 {
345*4882a593Smuzhiyun	rockchip,dp-lane-mux = <2 3>;
346*4882a593Smuzhiyun	status = "okay";
347*4882a593Smuzhiyun};
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun&usbdp_phy0_dp {
350*4882a593Smuzhiyun	status = "okay";
351*4882a593Smuzhiyun};
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun&usbdp_phy0_u3 {
354*4882a593Smuzhiyun	status = "okay";
355*4882a593Smuzhiyun};
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun&usbdp_phy1 {
358*4882a593Smuzhiyun	rockchip,dp-lane-mux = <3 2 1 0>;
359*4882a593Smuzhiyun	status = "okay";
360*4882a593Smuzhiyun};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun&usbdp_phy1_dp {
363*4882a593Smuzhiyun	status = "okay";
364*4882a593Smuzhiyun};
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun&usbdp_phy1_u3 {
367*4882a593Smuzhiyun	maximum-speed = "high-speed";
368*4882a593Smuzhiyun	status = "okay";
369*4882a593Smuzhiyun};
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun&usbdrd_dwc3_0 {
372*4882a593Smuzhiyun	dr_mode = "peripheral";
373*4882a593Smuzhiyun	maximum-speed = "high-speed";
374*4882a593Smuzhiyun	extcon = <&u2phy0>;
375*4882a593Smuzhiyun	status = "okay";
376*4882a593Smuzhiyun};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun&usbdrd_dwc3_1 {
379*4882a593Smuzhiyun	dr_mode = "host";
380*4882a593Smuzhiyun	maximum-speed = "high-speed";
381*4882a593Smuzhiyun	snps,dis_u2_susphy_quirk;
382*4882a593Smuzhiyun	status = "okay";
383*4882a593Smuzhiyun};
384