1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/ { 8 max96712_osc: oscillator { 9 compatible = "fixed-clock"; 10 #clock-cells = <1>; 11 clock-frequency = <25000000>; 12 clock-output-names = "max96712-osc"; 13 }; 14}; 15 16&csi2_dphy1_hw { 17 status = "okay"; 18}; 19 20&csi2_dphy3 { 21 status = "okay"; 22 23 ports { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 port@0 { 27 reg = <0>; 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 mipi_dphy1_in_max96712: endpoint@1 { 32 reg = <1>; 33 remote-endpoint = <&max96712_out>; 34 data-lanes = <1 2 3 4>; 35 }; 36 }; 37 port@1 { 38 reg = <1>; 39 #address-cells = <1>; 40 #size-cells = <0>; 41 42 csidphy1_out: endpoint@0 { 43 reg = <0>; 44 remote-endpoint = <&mipi4_csi2_input>; 45 }; 46 }; 47 }; 48}; 49 50&i2c6 { 51 status = "okay"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&i2c6m3_xfer>, <&max96712_errb>, <&max96712_int>; 54 55 max96712: max96712@29 { 56 compatible = "max96712"; 57 status = "okay"; 58 reg = <0x29>; 59 clock-names = "xvclk"; 60 clocks = <&max96712_osc 0>; 61 power-domains = <&power RK3588_PD_VI>; 62 rockchip,grf = <&sys_grf>; 63 power-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 64 pocen-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; 65 //reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 66 lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; 67 auto-init-deskew-mask = <0x03>; 68 frame-sync-period = <0>; 69 rockchip,camera-module-index = <0>; 70 rockchip,camera-module-facing = "back"; 71 rockchip,camera-module-name = "max96712"; 72 rockchip,camera-module-lens-name = "max96712"; 73 74 port { 75 max96712_out: endpoint { 76 remote-endpoint = <&mipi_dphy1_in_max96712>; 77 data-lanes = <1 2 3 4>; 78 }; 79 }; 80 }; 81}; 82 83&mipi4_csi2 { 84 status = "okay"; 85 86 ports { 87 #address-cells = <1>; 88 #size-cells = <0>; 89 90 port@0 { 91 reg = <0>; 92 #address-cells = <1>; 93 #size-cells = <0>; 94 95 mipi4_csi2_input: endpoint@1 { 96 reg = <1>; 97 remote-endpoint = <&csidphy1_out>; 98 }; 99 }; 100 101 port@1 { 102 reg = <1>; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 106 mipi4_csi2_output: endpoint@0 { 107 reg = <0>; 108 remote-endpoint = <&cif_mipi2_in>; 109 }; 110 }; 111 }; 112}; 113 114&rkcif_mipi_lvds4 { 115 status = "okay"; 116 /* parameters for do cif reset detecting: 117 * index0: monitor mode, 118 0 for idle, 119 1 for continue, 120 2 for trigger, 121 3 for hotplug (for nextchip) 122 * index1: the frame id to start timer, 123 min is 2 124 * index2: frame num of monitoring cycle 125 * index3: err time for keep monitoring 126 after finding out err (ms) 127 * index4: csi2 err reference val for resetting 128 */ 129 rockchip,cif-monitor = <3 2 1 1000 5>; 130 131 port { 132 cif_mipi2_in: endpoint { 133 remote-endpoint = <&mipi4_csi2_output>; 134 }; 135 }; 136}; 137 138&rkcif { 139 status = "okay"; 140 rockchip,android-usb-camerahal-enable; 141}; 142 143&rkcif_mmu { 144 status = "okay"; 145}; 146 147&pinctrl { 148 max96712 { 149 max96712_errb: max96712-errb { 150 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; 151 }; 152 153 max96712_int: max96712-int { 154 rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; 155 }; 156 }; 157}; 158