1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h" 8*4882a593Smuzhiyun#include "rk3588.dtsi" 9*4882a593Smuzhiyun#include "rk3588-toybrick.dtsi" 10*4882a593Smuzhiyun#include "rk3588-rk806-single.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun es8388_sound: es8388-sound { 14*4882a593Smuzhiyun status = "okay"; 15*4882a593Smuzhiyun compatible = "simple-audio-card"; 16*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 17*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 18*4882a593Smuzhiyun simple-audio-card,name = "rockchip,es8388-codec"; 19*4882a593Smuzhiyun simple-audio-card,dai-link@0 { 20*4882a593Smuzhiyun format = "i2s"; 21*4882a593Smuzhiyun cpu { 22*4882a593Smuzhiyun sound-dai = <&i2s0_8ch>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun codec { 25*4882a593Smuzhiyun sound-dai = <&es8388>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun pcie20_avdd0v85: pcie20-avdd0v85 { 31*4882a593Smuzhiyun compatible = "regulator-fixed"; 32*4882a593Smuzhiyun regulator-name = "pcie20_avdd0v85"; 33*4882a593Smuzhiyun regulator-boot-on; 34*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 35*4882a593Smuzhiyun regulator-max-microvolt = <850000>; 36*4882a593Smuzhiyun vin-supply = <&vdd_0v85_s0>;//csq 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun pcie20_avdd1v8: pcie20-avdd1v8 { 40*4882a593Smuzhiyun compatible = "regulator-fixed"; 41*4882a593Smuzhiyun regulator-name = "pcie20_avdd1v8"; 42*4882a593Smuzhiyun regulator-boot-on; 43*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 44*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 45*4882a593Smuzhiyun vin-supply = <&avcc_1v8_s0>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun pcie30_avdd0v75: pcie30-avdd0v75 { 49*4882a593Smuzhiyun compatible = "regulator-fixed"; 50*4882a593Smuzhiyun regulator-name = "pcie30_avdd0v75"; 51*4882a593Smuzhiyun regulator-boot-on; 52*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 53*4882a593Smuzhiyun regulator-max-microvolt = <750000>; 54*4882a593Smuzhiyun vin-supply = <&avdd_0v75_s0>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun pcie30_avdd1v8: pcie30-avdd1v8 { 58*4882a593Smuzhiyun compatible = "regulator-fixed"; 59*4882a593Smuzhiyun regulator-name = "pcie30_avdd1v8"; 60*4882a593Smuzhiyun regulator-boot-on; 61*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 62*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 63*4882a593Smuzhiyun vin-supply = <&avcc_1v8_s0>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun rk_headset: rk-headset { 67*4882a593Smuzhiyun status = "okay"; 68*4882a593Smuzhiyun compatible = "rockchip_headset"; 69*4882a593Smuzhiyun headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 70*4882a593Smuzhiyun pinctrl-names = "default"; 71*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 72*4882a593Smuzhiyun io-channels = <&saradc 3>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun vbus5v0_typec: vbus5v0-typec { 76*4882a593Smuzhiyun compatible = "regulator-fixed"; 77*4882a593Smuzhiyun regulator-name = "vbus5v0_typec"; 78*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 79*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 80*4882a593Smuzhiyun enable-active-high; 81*4882a593Smuzhiyun gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; 82*4882a593Smuzhiyun vin-supply = <&vcc5v0_usb>; 83*4882a593Smuzhiyun pinctrl-names = "default"; 84*4882a593Smuzhiyun pinctrl-0 = <&typec5v_pwren>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun vcc3v3_lcd_n: vcc3v3-lcd0-n { 88*4882a593Smuzhiyun compatible = "regulator-fixed"; 89*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd0_n"; 90*4882a593Smuzhiyun regulator-boot-on; 91*4882a593Smuzhiyun enable-active-high; 92*4882a593Smuzhiyun gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; 93*4882a593Smuzhiyun vin-supply = <&vcc_1v8_s0>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun vcc3v3_pcie30: vcc3v3-pcie30 { 97*4882a593Smuzhiyun compatible = "regulator-fixed"; 98*4882a593Smuzhiyun regulator-name = "vcc3v3_pcie30"; 99*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 100*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 101*4882a593Smuzhiyun enable-active-high; 102*4882a593Smuzhiyun gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; 103*4882a593Smuzhiyun startup-delay-us = <5000>; 104*4882a593Smuzhiyun vin-supply = <&vcc12v_dcin>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun vcc5v0_host: vcc5v0-host { 108*4882a593Smuzhiyun compatible = "regulator-fixed"; 109*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 110*4882a593Smuzhiyun regulator-boot-on; 111*4882a593Smuzhiyun regulator-always-on; 112*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 113*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 114*4882a593Smuzhiyun enable-active-high; 115*4882a593Smuzhiyun gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 116*4882a593Smuzhiyun vin-supply = <&vcc5v0_usb>; 117*4882a593Smuzhiyun pinctrl-names = "default"; 118*4882a593Smuzhiyun pinctrl-0 = <&vcc5v0_host_en>; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun vcc_mipicsi0: vcc-mipicsi0-regulator { 122*4882a593Smuzhiyun compatible = "regulator-fixed"; 123*4882a593Smuzhiyun gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; 124*4882a593Smuzhiyun pinctrl-names = "default"; 125*4882a593Smuzhiyun pinctrl-0 = <&mipicsi0_pwr>; 126*4882a593Smuzhiyun regulator-name = "vcc_mipicsi0"; 127*4882a593Smuzhiyun enable-active-high; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun vcc_mipicsi1: vcc-mipicsi1-regulator { 131*4882a593Smuzhiyun compatible = "regulator-fixed"; 132*4882a593Smuzhiyun gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 133*4882a593Smuzhiyun pinctrl-names = "default"; 134*4882a593Smuzhiyun pinctrl-0 = <&mipicsi1_pwr>; 135*4882a593Smuzhiyun regulator-name = "vcc_mipicsi1"; 136*4882a593Smuzhiyun enable-active-high; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun vcc_mipidcphy0: vcc-mipidcphy0-regulator { 140*4882a593Smuzhiyun compatible = "regulator-fixed"; 141*4882a593Smuzhiyun gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; 142*4882a593Smuzhiyun pinctrl-names = "default"; 143*4882a593Smuzhiyun pinctrl-0 = <&mipidcphy0_pwr>; 144*4882a593Smuzhiyun regulator-name = "vcc_mipicsi1"; 145*4882a593Smuzhiyun enable-active-high; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun wireless_bluetooth: wireless-bluetooth { 149*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 150*4882a593Smuzhiyun clocks = <&hym8563>; 151*4882a593Smuzhiyun clock-names = "ext_clock"; 152*4882a593Smuzhiyun uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; 153*4882a593Smuzhiyun pinctrl-names = "default", "rts_gpio"; 154*4882a593Smuzhiyun pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; 155*4882a593Smuzhiyun pinctrl-1 = <&uart8_gpios>; 156*4882a593Smuzhiyun BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; 157*4882a593Smuzhiyun BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 158*4882a593Smuzhiyun BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; 159*4882a593Smuzhiyun status = "okay"; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun wireless_wlan: wireless-wlan { 163*4882a593Smuzhiyun compatible = "wlan-platdata"; 164*4882a593Smuzhiyun wifi_chip_type = "ap6255"; 165*4882a593Smuzhiyun pinctrl-names = "default"; 166*4882a593Smuzhiyun pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; 167*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; 168*4882a593Smuzhiyun WIFI,poweren_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; 169*4882a593Smuzhiyun status = "okay"; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun panel-edp { 173*4882a593Smuzhiyun compatible = "innolux,p120zdg-bf4", "simple-panel"; 174*4882a593Smuzhiyun backlight = <&backlight>; 175*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd_edp>; 176*4882a593Smuzhiyun prepare-delay-ms = <120>; 177*4882a593Smuzhiyun enable-delay-ms = <120>; 178*4882a593Smuzhiyun unprepare-delay-ms = <500>; 179*4882a593Smuzhiyun disable-delay-ms = <120>; 180*4882a593Smuzhiyun width-mm = <254>; 181*4882a593Smuzhiyun height-mm = <169>; 182*4882a593Smuzhiyun panel-timing { 183*4882a593Smuzhiyun clock-frequency = <200000000>; 184*4882a593Smuzhiyun hactive = <1536>; 185*4882a593Smuzhiyun vactive = <2048>; 186*4882a593Smuzhiyun hfront-porch = <12>; 187*4882a593Smuzhiyun hsync-len = <16>; 188*4882a593Smuzhiyun hback-porch = <48>; 189*4882a593Smuzhiyun vfront-porch = <8>; 190*4882a593Smuzhiyun vsync-len = <4>; 191*4882a593Smuzhiyun vback-porch = <8>; 192*4882a593Smuzhiyun hsync-active = <0>; 193*4882a593Smuzhiyun vsync-active = <0>; 194*4882a593Smuzhiyun de-active = <0>; 195*4882a593Smuzhiyun pixelclk-active = <0>; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun port { 199*4882a593Smuzhiyun panel_in_edp: endpoint { 200*4882a593Smuzhiyun remote-endpoint = <&edp_out_panel>; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun vcc3v3_lcd_edp: vcc3v3-lcd-edp { 206*4882a593Smuzhiyun compatible = "regulator-fixed"; 207*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd_edp"; 208*4882a593Smuzhiyun gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; 209*4882a593Smuzhiyun enable-active-high; 210*4882a593Smuzhiyun vin-supply = <&vcc_3v3_s3>; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun}; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun&backlight { 215*4882a593Smuzhiyun pwms = <&pwm2 0 25000 0>; 216*4882a593Smuzhiyun status = "okay"; 217*4882a593Smuzhiyun}; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun&combphy0_ps { 220*4882a593Smuzhiyun status = "okay"; 221*4882a593Smuzhiyun}; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun&combphy1_ps { 224*4882a593Smuzhiyun status = "okay"; 225*4882a593Smuzhiyun}; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun&combphy2_psu { 228*4882a593Smuzhiyun status = "okay"; 229*4882a593Smuzhiyun}; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun&dp0 { 232*4882a593Smuzhiyun status = "disabled"; 233*4882a593Smuzhiyun}; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun&dp0_in_vp2 { 236*4882a593Smuzhiyun status = "disabled"; 237*4882a593Smuzhiyun}; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun&dp1 { 240*4882a593Smuzhiyun pinctrl-names = "default"; 241*4882a593Smuzhiyun pinctrl-0 = <&dp1_hpd>; 242*4882a593Smuzhiyun hpd-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; 243*4882a593Smuzhiyun status = "disabled"; 244*4882a593Smuzhiyun}; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun&dp1_in_vp2 { 247*4882a593Smuzhiyun status = "disabled"; 248*4882a593Smuzhiyun}; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun/* 251*4882a593Smuzhiyun * mipi_dcphy0 needs to be enabled 252*4882a593Smuzhiyun * when dsi0 is enabled 253*4882a593Smuzhiyun */ 254*4882a593Smuzhiyun&dsi0 { 255*4882a593Smuzhiyun status = "disabled"; 256*4882a593Smuzhiyun}; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun&dsi0_in_vp2 { 259*4882a593Smuzhiyun status = "disabled"; 260*4882a593Smuzhiyun}; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun&dsi0_in_vp3 { 263*4882a593Smuzhiyun status = "disabled"; 264*4882a593Smuzhiyun}; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun&edp1 { 267*4882a593Smuzhiyun force-hpd; 268*4882a593Smuzhiyun status = "okay"; 269*4882a593Smuzhiyun ports { 270*4882a593Smuzhiyun port@1 { 271*4882a593Smuzhiyun reg = <1>; 272*4882a593Smuzhiyun edp_out_panel: endpoint { 273*4882a593Smuzhiyun remote-endpoint = <&panel_in_edp>; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun}; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun&edp1_in_vp2 { 280*4882a593Smuzhiyun status = "okay"; 281*4882a593Smuzhiyun}; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun&hdptxphy1 { 284*4882a593Smuzhiyun status = "okay"; 285*4882a593Smuzhiyun}; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun&dsi0_panel { 288*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd_n>; 289*4882a593Smuzhiyun reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; 290*4882a593Smuzhiyun pinctrl-names = "default"; 291*4882a593Smuzhiyun pinctrl-0 = <&lcd_rst_gpio>; 292*4882a593Smuzhiyun}; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun/* 295*4882a593Smuzhiyun * mipi_dcphy1 needs to be enabled 296*4882a593Smuzhiyun * when dsi1 is enabled 297*4882a593Smuzhiyun */ 298*4882a593Smuzhiyun&dsi1 { 299*4882a593Smuzhiyun status = "disabled"; 300*4882a593Smuzhiyun}; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun&dsi1_in_vp2 { 303*4882a593Smuzhiyun status = "disabled"; 304*4882a593Smuzhiyun}; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun&dsi1_in_vp3 { 307*4882a593Smuzhiyun status = "disabled"; 308*4882a593Smuzhiyun}; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun&dsi1_panel { 311*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd_n>; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun /* 314*4882a593Smuzhiyun * because in hardware, the two screens share the reset pin, 315*4882a593Smuzhiyun * so reset-gpios need only in dsi1 enable and dsi0 disabled 316*4882a593Smuzhiyun * case. 317*4882a593Smuzhiyun */ 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; 320*4882a593Smuzhiyun //pinctrl-names = "default"; 321*4882a593Smuzhiyun //pinctrl-0 = <&lcd_rst_gpio>; 322*4882a593Smuzhiyun}; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun&gmac0 { 325*4882a593Smuzhiyun /* Use rgmii-rxid mode to disable rx delay inside Soc */ 326*4882a593Smuzhiyun phy-mode = "rgmii-rxid"; 327*4882a593Smuzhiyun clock_in_out = "output"; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; 330*4882a593Smuzhiyun snps,reset-active-low; 331*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 332*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun pinctrl-names = "default"; 335*4882a593Smuzhiyun pinctrl-0 = <&gmac0_miim 336*4882a593Smuzhiyun &gmac0_tx_bus2 337*4882a593Smuzhiyun &gmac0_rx_bus2 338*4882a593Smuzhiyun &gmac0_rgmii_clk 339*4882a593Smuzhiyun &gmac0_rgmii_bus>; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun tx_delay = <0x43>; 342*4882a593Smuzhiyun /* rx_delay = <0x3f>; */ 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun phy-handle = <&rgmii_phy>; 345*4882a593Smuzhiyun status = "okay"; 346*4882a593Smuzhiyun}; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun&hdmi0 { 349*4882a593Smuzhiyun enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 350*4882a593Smuzhiyun status = "okay"; 351*4882a593Smuzhiyun}; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun&hdmi0_in_vp0 { 354*4882a593Smuzhiyun status = "okay"; 355*4882a593Smuzhiyun}; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun&hdmi0_sound { 358*4882a593Smuzhiyun status = "okay"; 359*4882a593Smuzhiyun}; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun&hdptxphy_hdmi0 { 362*4882a593Smuzhiyun status = "okay"; 363*4882a593Smuzhiyun}; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun&i2c0 { 366*4882a593Smuzhiyun status = "okay"; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { 369*4882a593Smuzhiyun compatible = "rockchip,rk8602"; 370*4882a593Smuzhiyun reg = <0x42>; 371*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 372*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 373*4882a593Smuzhiyun regulator-name = "vdd_cpu_big0_s0"; 374*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 375*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 376*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 377*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 378*4882a593Smuzhiyun regulator-boot-on; 379*4882a593Smuzhiyun regulator-always-on; 380*4882a593Smuzhiyun regulator-state-mem { 381*4882a593Smuzhiyun regulator-off-in-suspend; 382*4882a593Smuzhiyun }; 383*4882a593Smuzhiyun }; 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { 386*4882a593Smuzhiyun compatible = "rockchip,rk8603"; 387*4882a593Smuzhiyun reg = <0x43>; 388*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 389*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 390*4882a593Smuzhiyun regulator-name = "vdd_cpu_big1_s0"; 391*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 392*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 393*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 394*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 395*4882a593Smuzhiyun regulator-boot-on; 396*4882a593Smuzhiyun regulator-always-on; 397*4882a593Smuzhiyun regulator-state-mem { 398*4882a593Smuzhiyun regulator-off-in-suspend; 399*4882a593Smuzhiyun }; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun}; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun&i2c2 { 404*4882a593Smuzhiyun status = "okay"; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun usbc0: fusb302@22 { 407*4882a593Smuzhiyun compatible = "fcs,fusb302"; 408*4882a593Smuzhiyun reg = <0x22>; 409*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 410*4882a593Smuzhiyun interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; 411*4882a593Smuzhiyun pinctrl-names = "default"; 412*4882a593Smuzhiyun pinctrl-0 = <&usbc0_int>; 413*4882a593Smuzhiyun vbus-supply = <&vbus5v0_typec>; 414*4882a593Smuzhiyun status = "okay"; 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun ports { 417*4882a593Smuzhiyun #address-cells = <1>; 418*4882a593Smuzhiyun #size-cells = <0>; 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun port@0 { 421*4882a593Smuzhiyun reg = <0>; 422*4882a593Smuzhiyun usbc0_role_sw: endpoint@0 { 423*4882a593Smuzhiyun remote-endpoint = <&dwc3_0_role_switch>; 424*4882a593Smuzhiyun }; 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun usb_con: connector { 429*4882a593Smuzhiyun compatible = "usb-c-connector"; 430*4882a593Smuzhiyun label = "USB-C"; 431*4882a593Smuzhiyun data-role = "dual"; 432*4882a593Smuzhiyun power-role = "dual"; 433*4882a593Smuzhiyun try-power-role = "sink"; 434*4882a593Smuzhiyun op-sink-microwatt = <1000000>; 435*4882a593Smuzhiyun sink-pdos = 436*4882a593Smuzhiyun <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; 437*4882a593Smuzhiyun source-pdos = 438*4882a593Smuzhiyun <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun altmodes { 441*4882a593Smuzhiyun #address-cells = <1>; 442*4882a593Smuzhiyun #size-cells = <0>; 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun altmode@0 { 445*4882a593Smuzhiyun reg = <0>; 446*4882a593Smuzhiyun svid = <0xff01>; 447*4882a593Smuzhiyun vdo = <0xffffffff>; 448*4882a593Smuzhiyun }; 449*4882a593Smuzhiyun }; 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun ports { 452*4882a593Smuzhiyun #address-cells = <1>; 453*4882a593Smuzhiyun #size-cells = <0>; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun port@0 { 456*4882a593Smuzhiyun reg = <0>; 457*4882a593Smuzhiyun usbc0_orien_sw: endpoint { 458*4882a593Smuzhiyun remote-endpoint = <&usbdp_phy0_orientation_switch>; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun port@1 { 463*4882a593Smuzhiyun reg = <1>; 464*4882a593Smuzhiyun dp_altmode_mux: endpoint { 465*4882a593Smuzhiyun remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun }; 468*4882a593Smuzhiyun }; 469*4882a593Smuzhiyun }; 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun hym8563: hym8563@51 { 473*4882a593Smuzhiyun compatible = "haoyu,hym8563"; 474*4882a593Smuzhiyun reg = <0x51>; 475*4882a593Smuzhiyun #clock-cells = <0>; 476*4882a593Smuzhiyun clock-frequency = <32768>; 477*4882a593Smuzhiyun clock-output-names = "hym8563"; 478*4882a593Smuzhiyun pinctrl-names = "default"; 479*4882a593Smuzhiyun pinctrl-0 = <&hym8563_int>; 480*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 481*4882a593Smuzhiyun interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; 482*4882a593Smuzhiyun }; 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { 485*4882a593Smuzhiyun compatible = "rockchip,rk8602"; 486*4882a593Smuzhiyun reg = <0x42>; 487*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 488*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 489*4882a593Smuzhiyun regulator-name = "vdd_npu_s0"; 490*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 491*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 492*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 493*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 494*4882a593Smuzhiyun regulator-boot-on; 495*4882a593Smuzhiyun regulator-always-on; 496*4882a593Smuzhiyun regulator-state-mem { 497*4882a593Smuzhiyun regulator-off-in-suspend; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun }; 500*4882a593Smuzhiyun}; 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun&i2c6 { 503*4882a593Smuzhiyun status = "okay"; 504*4882a593Smuzhiyun gt1x: gt1x@14 { 505*4882a593Smuzhiyun compatible = "goodix,gt1x"; 506*4882a593Smuzhiyun reg = <0x14>; 507*4882a593Smuzhiyun pinctrl-names = "default"; 508*4882a593Smuzhiyun pinctrl-0 = <&touch_gpio>; 509*4882a593Smuzhiyun goodix,rst-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; 510*4882a593Smuzhiyun goodix,irq-gpio = <&gpio0 RK_PB0 IRQ_TYPE_LEVEL_LOW>; 511*4882a593Smuzhiyun }; 512*4882a593Smuzhiyun 513*4882a593Smuzhiyun gsl3673: gsl3673@40 { 514*4882a593Smuzhiyun compatible = "GSL,GSL3673"; 515*4882a593Smuzhiyun reg = <0x40>; 516*4882a593Smuzhiyun screen_max_x = <1536>; 517*4882a593Smuzhiyun screen_max_y = <2048>; 518*4882a593Smuzhiyun irq_gpio_number = <&gpio1 RK_PA6 IRQ_TYPE_LEVEL_LOW>; 519*4882a593Smuzhiyun rst_gpio_number = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun}; 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun&i2c7 { 524*4882a593Smuzhiyun status = "okay"; 525*4882a593Smuzhiyun es8388: es8388@11 { 526*4882a593Smuzhiyun status = "okay"; 527*4882a593Smuzhiyun #sound-dai-cells = <0>; 528*4882a593Smuzhiyun compatible = "everest,es8388", "everest,es8323"; 529*4882a593Smuzhiyun reg = <0x11>; 530*4882a593Smuzhiyun clocks = <&mclkout_i2s0>; 531*4882a593Smuzhiyun clock-names = "mclk"; 532*4882a593Smuzhiyun assigned-clocks = <&mclkout_i2s0>; 533*4882a593Smuzhiyun assigned-clock-rates = <12288000>; 534*4882a593Smuzhiyun pinctrl-names = "default"; 535*4882a593Smuzhiyun pinctrl-0 = <&i2s0_mclk>; 536*4882a593Smuzhiyun spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 537*4882a593Smuzhiyun hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; 538*4882a593Smuzhiyun extcon = <&rk_headset>; 539*4882a593Smuzhiyun }; 540*4882a593Smuzhiyun}; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun&hdmirx_ctrler { 543*4882a593Smuzhiyun status = "okay"; 544*4882a593Smuzhiyun hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; 545*4882a593Smuzhiyun pinctrl-names = "default"; 546*4882a593Smuzhiyun pinctrl-0 = <&hdmim1_rx &hdmirx_det>; 547*4882a593Smuzhiyun}; 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun&i2s5_8ch { 550*4882a593Smuzhiyun status = "okay"; 551*4882a593Smuzhiyun}; 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun&mdio0 { 554*4882a593Smuzhiyun rgmii_phy: phy@1 { 555*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 556*4882a593Smuzhiyun reg = <0x1>; 557*4882a593Smuzhiyun }; 558*4882a593Smuzhiyun}; 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun&mipi_dcphy0 { 561*4882a593Smuzhiyun status = "okay"; 562*4882a593Smuzhiyun}; 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun&mipi_dcphy1 { 565*4882a593Smuzhiyun status = "disabled"; 566*4882a593Smuzhiyun}; 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun&pcie2x1l0 { 569*4882a593Smuzhiyun reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; 570*4882a593Smuzhiyun status = "okay"; 571*4882a593Smuzhiyun}; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun&pcie2x1l1 { 574*4882a593Smuzhiyun reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 575*4882a593Smuzhiyun pinctrl-names = "default"; 576*4882a593Smuzhiyun pinctrl-0 = <&rtl8111_isolate>; 577*4882a593Smuzhiyun status = "okay"; 578*4882a593Smuzhiyun}; 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun&pcie30phy { 581*4882a593Smuzhiyun rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>; 582*4882a593Smuzhiyun status = "okay"; 583*4882a593Smuzhiyun}; 584*4882a593Smuzhiyun 585*4882a593Smuzhiyun&pcie3x4 { 586*4882a593Smuzhiyun reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 587*4882a593Smuzhiyun vpcie3v3-supply = <&vcc3v3_pcie30>; 588*4882a593Smuzhiyun status = "disabled"; 589*4882a593Smuzhiyun}; 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun&pinctrl { 592*4882a593Smuzhiyun cam { 593*4882a593Smuzhiyun mipicsi0_pwr: mipicsi0-pwr { 594*4882a593Smuzhiyun rockchip,pins = 595*4882a593Smuzhiyun /* camera power en */ 596*4882a593Smuzhiyun <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 597*4882a593Smuzhiyun }; 598*4882a593Smuzhiyun mipicsi1_pwr: mipicsi1-pwr { 599*4882a593Smuzhiyun rockchip,pins = 600*4882a593Smuzhiyun /* camera power en */ 601*4882a593Smuzhiyun <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 602*4882a593Smuzhiyun }; 603*4882a593Smuzhiyun mipidcphy0_pwr: mipidcphy0-pwr { 604*4882a593Smuzhiyun rockchip,pins = 605*4882a593Smuzhiyun /* camera power en */ 606*4882a593Smuzhiyun <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 607*4882a593Smuzhiyun }; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun dp { 611*4882a593Smuzhiyun dp1_hpd: dp1-hpd { 612*4882a593Smuzhiyun rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 613*4882a593Smuzhiyun }; 614*4882a593Smuzhiyun }; 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun hdmi { 617*4882a593Smuzhiyun hdmirx_det: hdmirx-det { 618*4882a593Smuzhiyun rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; 619*4882a593Smuzhiyun }; 620*4882a593Smuzhiyun }; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun headphone { 623*4882a593Smuzhiyun hp_det: hp-det { 624*4882a593Smuzhiyun rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 625*4882a593Smuzhiyun }; 626*4882a593Smuzhiyun }; 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun hym8563 { 629*4882a593Smuzhiyun hym8563_int: hym8563-int { 630*4882a593Smuzhiyun rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 631*4882a593Smuzhiyun }; 632*4882a593Smuzhiyun }; 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun lcd { 635*4882a593Smuzhiyun lcd_rst_gpio: lcd-rst-gpio { 636*4882a593Smuzhiyun rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 637*4882a593Smuzhiyun }; 638*4882a593Smuzhiyun }; 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun rtl8111 { 641*4882a593Smuzhiyun rtl8111_isolate: rtl8111-isolate { 642*4882a593Smuzhiyun rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 643*4882a593Smuzhiyun }; 644*4882a593Smuzhiyun }; 645*4882a593Smuzhiyun 646*4882a593Smuzhiyun touch { 647*4882a593Smuzhiyun touch_gpio: touch-gpio { 648*4882a593Smuzhiyun rockchip,pins = 649*4882a593Smuzhiyun <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, 650*4882a593Smuzhiyun <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 651*4882a593Smuzhiyun }; 652*4882a593Smuzhiyun }; 653*4882a593Smuzhiyun 654*4882a593Smuzhiyun usb { 655*4882a593Smuzhiyun vcc5v0_host_en: vcc5v0-host-en { 656*4882a593Smuzhiyun rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 657*4882a593Smuzhiyun }; 658*4882a593Smuzhiyun }; 659*4882a593Smuzhiyun 660*4882a593Smuzhiyun usb-typec { 661*4882a593Smuzhiyun usbc0_int: usbc0-int { 662*4882a593Smuzhiyun rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; 663*4882a593Smuzhiyun }; 664*4882a593Smuzhiyun 665*4882a593Smuzhiyun typec5v_pwren: typec5v-pwren { 666*4882a593Smuzhiyun rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 667*4882a593Smuzhiyun }; 668*4882a593Smuzhiyun }; 669*4882a593Smuzhiyun 670*4882a593Smuzhiyun wireless-bluetooth { 671*4882a593Smuzhiyun uart8_gpios: uart8-gpios { 672*4882a593Smuzhiyun rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 673*4882a593Smuzhiyun }; 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun bt_reset_gpio: bt-reset-gpio { 676*4882a593Smuzhiyun rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 677*4882a593Smuzhiyun }; 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun bt_wake_gpio: bt-wake-gpio { 680*4882a593Smuzhiyun rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; 681*4882a593Smuzhiyun }; 682*4882a593Smuzhiyun 683*4882a593Smuzhiyun bt_irq_gpio: bt-irq-gpio { 684*4882a593Smuzhiyun rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; 685*4882a593Smuzhiyun }; 686*4882a593Smuzhiyun }; 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun wireless-wlan { 689*4882a593Smuzhiyun wifi_host_wake_irq: wifi-host-wake-irq { 690*4882a593Smuzhiyun rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; 691*4882a593Smuzhiyun }; 692*4882a593Smuzhiyun 693*4882a593Smuzhiyun wifi_poweren_gpio: wifi-poweren-gpio { 694*4882a593Smuzhiyun rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 695*4882a593Smuzhiyun }; 696*4882a593Smuzhiyun }; 697*4882a593Smuzhiyun}; 698*4882a593Smuzhiyun 699*4882a593Smuzhiyun&pwm2 { 700*4882a593Smuzhiyun status = "okay"; 701*4882a593Smuzhiyun}; 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun&sata0 { 704*4882a593Smuzhiyun status = "okay"; 705*4882a593Smuzhiyun}; 706*4882a593Smuzhiyun 707*4882a593Smuzhiyun&u2phy1_otg { 708*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 709*4882a593Smuzhiyun}; 710*4882a593Smuzhiyun 711*4882a593Smuzhiyun&u2phy2_host { 712*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 713*4882a593Smuzhiyun}; 714*4882a593Smuzhiyun 715*4882a593Smuzhiyun&u2phy3_host { 716*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 717*4882a593Smuzhiyun}; 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun&uart8 { 720*4882a593Smuzhiyun status = "okay"; 721*4882a593Smuzhiyun pinctrl-names = "default"; 722*4882a593Smuzhiyun pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; 723*4882a593Smuzhiyun}; 724*4882a593Smuzhiyun 725*4882a593Smuzhiyun&usbdp_phy0 { 726*4882a593Smuzhiyun orientation-switch; 727*4882a593Smuzhiyun svid = <0xff01>; 728*4882a593Smuzhiyun sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 729*4882a593Smuzhiyun sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 730*4882a593Smuzhiyun 731*4882a593Smuzhiyun port { 732*4882a593Smuzhiyun #address-cells = <1>; 733*4882a593Smuzhiyun #size-cells = <0>; 734*4882a593Smuzhiyun usbdp_phy0_orientation_switch: endpoint@0 { 735*4882a593Smuzhiyun reg = <0>; 736*4882a593Smuzhiyun remote-endpoint = <&usbc0_orien_sw>; 737*4882a593Smuzhiyun }; 738*4882a593Smuzhiyun 739*4882a593Smuzhiyun usbdp_phy0_dp_altmode_mux: endpoint@1 { 740*4882a593Smuzhiyun reg = <1>; 741*4882a593Smuzhiyun remote-endpoint = <&dp_altmode_mux>; 742*4882a593Smuzhiyun }; 743*4882a593Smuzhiyun }; 744*4882a593Smuzhiyun}; 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun&usbdp_phy1 { 747*4882a593Smuzhiyun rockchip,dp-lane-mux = <2 3>; 748*4882a593Smuzhiyun}; 749*4882a593Smuzhiyun 750*4882a593Smuzhiyun&usbdrd_dwc3_0 { 751*4882a593Smuzhiyun dr_mode = "otg"; 752*4882a593Smuzhiyun usb-role-switch; 753*4882a593Smuzhiyun port { 754*4882a593Smuzhiyun #address-cells = <1>; 755*4882a593Smuzhiyun #size-cells = <0>; 756*4882a593Smuzhiyun dwc3_0_role_switch: endpoint@0 { 757*4882a593Smuzhiyun reg = <0>; 758*4882a593Smuzhiyun remote-endpoint = <&usbc0_role_sw>; 759*4882a593Smuzhiyun }; 760*4882a593Smuzhiyun }; 761*4882a593Smuzhiyun}; 762*4882a593Smuzhiyun 763*4882a593Smuzhiyun&usbhost3_0 { 764*4882a593Smuzhiyun status = "disabled"; 765*4882a593Smuzhiyun}; 766*4882a593Smuzhiyun 767*4882a593Smuzhiyun&usbhost_dwc3_0 { 768*4882a593Smuzhiyun status = "disabled"; 769*4882a593Smuzhiyun}; 770*4882a593Smuzhiyun 771