1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun&spi2 { 11*4882a593Smuzhiyun status = "okay"; 12*4882a593Smuzhiyun assigned-clocks = <&cru CLK_SPI2>; 13*4882a593Smuzhiyun assigned-clock-rates = <200000000>; 14*4882a593Smuzhiyun num-cs = <2>; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun rk806master: rk806master@0 { 17*4882a593Smuzhiyun compatible = "rockchip,rk806"; 18*4882a593Smuzhiyun spi-max-frequency = <1000000>; 19*4882a593Smuzhiyun reg = <0x0>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 22*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun pinctrl-names = "default", "pmic-power-off"; 25*4882a593Smuzhiyun pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; 26*4882a593Smuzhiyun pinctrl-1 = <&rk806_dvs1_pwrdn>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 2800mv-3500mv */ 29*4882a593Smuzhiyun low_voltage_threshold = <3000>; 30*4882a593Smuzhiyun /* 2700mv-3400mv */ 31*4882a593Smuzhiyun shutdown_voltage_threshold = <2700>; 32*4882a593Smuzhiyun /* 140 160 */ 33*4882a593Smuzhiyun shutdown_temperture_threshold = <160>; 34*4882a593Smuzhiyun hotdie_temperture_threshold = <115>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 0: restart PMU; 37*4882a593Smuzhiyun * 1: reset all the power off reset registers, 38*4882a593Smuzhiyun * forcing the state to switch to ACTIVE mode; 39*4882a593Smuzhiyun * 2: Reset all the power off reset registers, 40*4882a593Smuzhiyun * forcing the state to switch to ACTIVE mode, 41*4882a593Smuzhiyun * and simultaneously pull down the RESETB PIN for 5mS before releasing 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun pmic-reset-func = <1>; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun vcc1-supply = <&vcc5v0_sys>; 46*4882a593Smuzhiyun vcc2-supply = <&vcc5v0_sys>; 47*4882a593Smuzhiyun vcc3-supply = <&vcc5v0_sys>; 48*4882a593Smuzhiyun vcc4-supply = <&vcc5v0_sys>; 49*4882a593Smuzhiyun vcc5-supply = <&vcc5v0_sys>; 50*4882a593Smuzhiyun vcc6-supply = <&vcc5v0_sys>; 51*4882a593Smuzhiyun vcc7-supply = <&vcc5v0_sys>; 52*4882a593Smuzhiyun vcc8-supply = <&vcc5v0_sys>; 53*4882a593Smuzhiyun vcc9-supply = <&vcc5v0_sys>; 54*4882a593Smuzhiyun vcc10-supply = <&vcc5v0_sys>; 55*4882a593Smuzhiyun vcc11-supply = <&vcc_2v0_pldo_s3>; 56*4882a593Smuzhiyun vcc12-supply = <&vcc5v0_sys>; 57*4882a593Smuzhiyun vcc13-supply = <&vcc_1v1_nldo_s3>; 58*4882a593Smuzhiyun vcc14-supply = <&vcc_1v1_nldo_s3>; 59*4882a593Smuzhiyun vcca-supply = <&vcc5v0_sys>; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun pwrkey { 62*4882a593Smuzhiyun status = "okay"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun pinctrl_rk806: pinctrl_rk806 { 66*4882a593Smuzhiyun gpio-controller; 67*4882a593Smuzhiyun #gpio-cells = <2>; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun rk806_dvs1_null: rk806_dvs1_null { 70*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 71*4882a593Smuzhiyun function = "pin_fun0"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun rk806_dvs1_slp: rk806_dvs1_slp { 75*4882a593Smuzhiyun pins = "gpio_pwrctrl1"; 76*4882a593Smuzhiyun function = "pin_fun1"; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { 80*4882a593Smuzhiyun pins = "gpio_pwrctrl1"; 81*4882a593Smuzhiyun function = "pin_fun2"; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun rk806_dvs1_rst: rk806_dvs1_rst { 85*4882a593Smuzhiyun pins = "gpio_pwrctrl1"; 86*4882a593Smuzhiyun function = "pin_fun3"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun rk806_dvs2_null: rk806_dvs2_null { 90*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 91*4882a593Smuzhiyun function = "pin_fun0"; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun rk806_dvs2_slp: rk806_dvs2_slp { 95*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 96*4882a593Smuzhiyun function = "pin_fun1"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { 100*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 101*4882a593Smuzhiyun function = "pin_fun2"; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun rk806_dvs2_rst: rk806_dvs2_rst { 105*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 106*4882a593Smuzhiyun function = "pin_fun3"; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun rk806_dvs2_dvs: rk806_dvs2_dvs { 110*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 111*4882a593Smuzhiyun function = "pin_fun4"; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun rk806_dvs2_gpio: rk806_dvs2_gpio { 115*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 116*4882a593Smuzhiyun function = "pin_fun5"; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun rk806_dvs3_null: rk806_dvs3_null { 120*4882a593Smuzhiyun pins = "gpio_pwrctrl3"; 121*4882a593Smuzhiyun function = "pin_fun0"; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun rk806_dvs3_slp: rk806_dvs3_slp { 125*4882a593Smuzhiyun pins = "gpio_pwrctrl3"; 126*4882a593Smuzhiyun function = "pin_fun1"; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { 130*4882a593Smuzhiyun pins = "gpio_pwrctrl3"; 131*4882a593Smuzhiyun function = "pin_fun2"; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun rk806_dvs3_rst: rk806_dvs3_rst { 135*4882a593Smuzhiyun pins = "gpio_pwrctrl3"; 136*4882a593Smuzhiyun function = "pin_fun3"; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun rk806_dvs3_dvs: rk806_dvs3_dvs { 140*4882a593Smuzhiyun pins = "gpio_pwrctrl3"; 141*4882a593Smuzhiyun function = "pin_fun4"; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun rk806_dvs3_gpio: rk806_dvs3_gpio { 145*4882a593Smuzhiyun pins = "gpio_pwrctrl3"; 146*4882a593Smuzhiyun function = "pin_fun5"; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun regulators { 151*4882a593Smuzhiyun vdd_gpu_s0: DCDC_REG1 { 152*4882a593Smuzhiyun regulator-boot-on; 153*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 154*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 155*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 156*4882a593Smuzhiyun regulator-name = "vdd_gpu_s0"; 157*4882a593Smuzhiyun regulator-enable-ramp-delay = <400>; 158*4882a593Smuzhiyun regulator-state-mem { 159*4882a593Smuzhiyun regulator-off-in-suspend; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun vdd_npu_s0: DCDC_REG2 { 164*4882a593Smuzhiyun regulator-always-on; 165*4882a593Smuzhiyun regulator-boot-on; 166*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 167*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 168*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 169*4882a593Smuzhiyun regulator-name = "vdd_npu_s0"; 170*4882a593Smuzhiyun regulator-state-mem { 171*4882a593Smuzhiyun regulator-off-in-suspend; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun vdd_log_s0: DCDC_REG3 { 176*4882a593Smuzhiyun regulator-always-on; 177*4882a593Smuzhiyun regulator-boot-on; 178*4882a593Smuzhiyun regulator-min-microvolt = <675000>; 179*4882a593Smuzhiyun regulator-max-microvolt = <750000>; 180*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 181*4882a593Smuzhiyun regulator-name = "vdd_log_s0"; 182*4882a593Smuzhiyun regulator-state-mem { 183*4882a593Smuzhiyun regulator-off-in-suspend; 184*4882a593Smuzhiyun regulator-suspend-microvolt = <750000>; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun vdd_vdenc_s0: DCDC_REG4 { 189*4882a593Smuzhiyun regulator-always-on; 190*4882a593Smuzhiyun regulator-boot-on; 191*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 192*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 193*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 194*4882a593Smuzhiyun regulator-name = "vdd_vdenc_s0"; 195*4882a593Smuzhiyun regulator-state-mem { 196*4882a593Smuzhiyun regulator-off-in-suspend; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun vdd_gpu_mem_s0: DCDC_REG5 { 201*4882a593Smuzhiyun regulator-boot-on; 202*4882a593Smuzhiyun regulator-min-microvolt = <675000>; 203*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 204*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 205*4882a593Smuzhiyun regulator-enable-ramp-delay = <400>; 206*4882a593Smuzhiyun regulator-name = "vdd_gpu_mem_s0"; 207*4882a593Smuzhiyun regulator-state-mem { 208*4882a593Smuzhiyun regulator-off-in-suspend; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun vdd_npu_mem_s0: DCDC_REG6 { 213*4882a593Smuzhiyun regulator-always-on; 214*4882a593Smuzhiyun regulator-boot-on; 215*4882a593Smuzhiyun regulator-min-microvolt = <675000>; 216*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 217*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 218*4882a593Smuzhiyun regulator-name = "vdd_npu_mem_s0"; 219*4882a593Smuzhiyun regulator-state-mem { 220*4882a593Smuzhiyun regulator-off-in-suspend; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun vcc_2v0_pldo_s3: DCDC_REG7 { 225*4882a593Smuzhiyun regulator-always-on; 226*4882a593Smuzhiyun regulator-boot-on; 227*4882a593Smuzhiyun regulator-min-microvolt = <2000000>; 228*4882a593Smuzhiyun regulator-max-microvolt = <2000000>; 229*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 230*4882a593Smuzhiyun regulator-name = "vdd_2v0_pldo_s3"; 231*4882a593Smuzhiyun regulator-state-mem { 232*4882a593Smuzhiyun regulator-on-in-suspend; 233*4882a593Smuzhiyun regulator-suspend-microvolt = <2000000>; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun vdd_vdenc_mem_s0: DCDC_REG8 { 238*4882a593Smuzhiyun regulator-always-on; 239*4882a593Smuzhiyun regulator-boot-on; 240*4882a593Smuzhiyun regulator-min-microvolt = <675000>; 241*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 242*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 243*4882a593Smuzhiyun regulator-name = "vdd_vdenc_mem_s0"; 244*4882a593Smuzhiyun regulator-state-mem { 245*4882a593Smuzhiyun regulator-off-in-suspend; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun vdd2_ddr_s3: DCDC_REG9 { 250*4882a593Smuzhiyun regulator-always-on; 251*4882a593Smuzhiyun regulator-boot-on; 252*4882a593Smuzhiyun regulator-name = "vdd2_ddr_s3"; 253*4882a593Smuzhiyun regulator-state-mem { 254*4882a593Smuzhiyun regulator-on-in-suspend; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun vcc_1v1_nldo_s3: DCDC_REG10 { 259*4882a593Smuzhiyun regulator-always-on; 260*4882a593Smuzhiyun regulator-boot-on; 261*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 262*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 263*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 264*4882a593Smuzhiyun regulator-name = "vcc_1v1_nldo_s3"; 265*4882a593Smuzhiyun regulator-state-mem { 266*4882a593Smuzhiyun regulator-on-in-suspend; 267*4882a593Smuzhiyun regulator-suspend-microvolt = <1100000>; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun avcc_1v8_s0: PLDO_REG1 { 272*4882a593Smuzhiyun regulator-always-on; 273*4882a593Smuzhiyun regulator-boot-on; 274*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 275*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 276*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 277*4882a593Smuzhiyun regulator-name = "avcc_1v8_s0"; 278*4882a593Smuzhiyun regulator-state-mem { 279*4882a593Smuzhiyun regulator-off-in-suspend; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun vdd1_1v8_ddr_s3: PLDO_REG2 { 284*4882a593Smuzhiyun regulator-always-on; 285*4882a593Smuzhiyun regulator-boot-on; 286*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 287*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 288*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 289*4882a593Smuzhiyun regulator-name = "vdd1_1v8_ddr_s3"; 290*4882a593Smuzhiyun regulator-state-mem { 291*4882a593Smuzhiyun regulator-on-in-suspend; 292*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun avcc_1v8_codec_s0: PLDO_REG3 { 297*4882a593Smuzhiyun regulator-always-on; 298*4882a593Smuzhiyun regulator-boot-on; 299*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 300*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 301*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 302*4882a593Smuzhiyun regulator-name = "avcc_1v8_codec_s0"; 303*4882a593Smuzhiyun regulator-state-mem { 304*4882a593Smuzhiyun regulator-off-in-suspend; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun vcc_3v3_s3: PLDO_REG4 { 309*4882a593Smuzhiyun regulator-always-on; 310*4882a593Smuzhiyun regulator-boot-on; 311*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 312*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 313*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 314*4882a593Smuzhiyun regulator-name = "vcc_3v3_s3"; 315*4882a593Smuzhiyun regulator-state-mem { 316*4882a593Smuzhiyun regulator-on-in-suspend; 317*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun vccio_sd_s0: PLDO_REG5 { 322*4882a593Smuzhiyun regulator-always-on; 323*4882a593Smuzhiyun regulator-boot-on; 324*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 325*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 326*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 327*4882a593Smuzhiyun regulator-name = "vccio_sd_s0"; 328*4882a593Smuzhiyun regulator-state-mem { 329*4882a593Smuzhiyun regulator-off-in-suspend; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun }; 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun vccio_1v8_s3: PLDO_REG6 { 334*4882a593Smuzhiyun regulator-always-on; 335*4882a593Smuzhiyun regulator-boot-on; 336*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 337*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 338*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 339*4882a593Smuzhiyun regulator-name = "vccio_1v8_s3"; 340*4882a593Smuzhiyun regulator-state-mem { 341*4882a593Smuzhiyun regulator-on-in-suspend; 342*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun vdd_0v75_s3: NLDO_REG1 { 347*4882a593Smuzhiyun regulator-always-on; 348*4882a593Smuzhiyun regulator-boot-on; 349*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 350*4882a593Smuzhiyun regulator-max-microvolt = <750000>; 351*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 352*4882a593Smuzhiyun regulator-name = "vdd_0v75_s3"; 353*4882a593Smuzhiyun regulator-state-mem { 354*4882a593Smuzhiyun regulator-on-in-suspend; 355*4882a593Smuzhiyun regulator-suspend-microvolt = <750000>; 356*4882a593Smuzhiyun }; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun vdd2l_0v9_ddr_s3: NLDO_REG2 { 360*4882a593Smuzhiyun regulator-always-on; 361*4882a593Smuzhiyun regulator-boot-on; 362*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 363*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 364*4882a593Smuzhiyun regulator-name = "vdd2l_0v9_ddr_s3"; 365*4882a593Smuzhiyun regulator-state-mem { 366*4882a593Smuzhiyun regulator-on-in-suspend; 367*4882a593Smuzhiyun regulator-suspend-microvolt = <900000>; 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun vdd_0v75_hdmi_edp_s0: NLDO_REG3 { 372*4882a593Smuzhiyun regulator-always-on; 373*4882a593Smuzhiyun regulator-boot-on; 374*4882a593Smuzhiyun regulator-min-microvolt = <837500>; 375*4882a593Smuzhiyun regulator-max-microvolt = <837500>; 376*4882a593Smuzhiyun regulator-name = "vdd_0v75_hdmi_edp_s0"; 377*4882a593Smuzhiyun regulator-state-mem { 378*4882a593Smuzhiyun regulator-off-in-suspend; 379*4882a593Smuzhiyun }; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun avdd_0v75_s0: NLDO_REG4 { 383*4882a593Smuzhiyun regulator-always-on; 384*4882a593Smuzhiyun regulator-boot-on; 385*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 386*4882a593Smuzhiyun regulator-max-microvolt = <750000>; 387*4882a593Smuzhiyun regulator-name = "avdd_0v75_s0"; 388*4882a593Smuzhiyun regulator-state-mem { 389*4882a593Smuzhiyun regulator-off-in-suspend; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun vdd_0v85_s0: NLDO_REG5 { 394*4882a593Smuzhiyun regulator-always-on; 395*4882a593Smuzhiyun regulator-boot-on; 396*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 397*4882a593Smuzhiyun regulator-max-microvolt = <850000>; 398*4882a593Smuzhiyun regulator-name = "vdd_0v85_s0"; 399*4882a593Smuzhiyun regulator-state-mem { 400*4882a593Smuzhiyun regulator-off-in-suspend; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun }; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun rk806slave: rk806slave@1 { 407*4882a593Smuzhiyun compatible = "rockchip,rk806"; 408*4882a593Smuzhiyun spi-max-frequency = <1000000>; 409*4882a593Smuzhiyun reg = <0x01>; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 412*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun pinctrl-names = "default"; 415*4882a593Smuzhiyun pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun /* 0: restart PMU; 418*4882a593Smuzhiyun * 1: reset all the power off reset registers, 419*4882a593Smuzhiyun * forcing the state to switch to ACTIVE mode; 420*4882a593Smuzhiyun * 2: Reset all the power off reset registers, 421*4882a593Smuzhiyun * forcing the state to switch to ACTIVE mode, 422*4882a593Smuzhiyun * and simultaneously pull down the RESETB PIN for 5mS before releasing 423*4882a593Smuzhiyun */ 424*4882a593Smuzhiyun pmic-reset-func = <1>; 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun vcc1-supply = <&vcc5v0_sys>; 427*4882a593Smuzhiyun vcc2-supply = <&vcc5v0_sys>; 428*4882a593Smuzhiyun vcc3-supply = <&vcc5v0_sys>; 429*4882a593Smuzhiyun vcc4-supply = <&vcc5v0_sys>; 430*4882a593Smuzhiyun vcc5-supply = <&vcc5v0_sys>; 431*4882a593Smuzhiyun vcc6-supply = <&vcc5v0_sys>; 432*4882a593Smuzhiyun vcc7-supply = <&vcc5v0_sys>; 433*4882a593Smuzhiyun vcc8-supply = <&vcc5v0_sys>; 434*4882a593Smuzhiyun vcc9-supply = <&vcc5v0_sys>; 435*4882a593Smuzhiyun vcc10-supply = <&vcc5v0_sys>; 436*4882a593Smuzhiyun vcc11-supply = <&vcc_2v0_pldo_s3>; 437*4882a593Smuzhiyun vcc12-supply = <&vcc5v0_sys>; 438*4882a593Smuzhiyun vcc13-supply = <&vcc_1v1_nldo_s3>; 439*4882a593Smuzhiyun vcc14-supply = <&vcc_2v0_pldo_s3>; 440*4882a593Smuzhiyun vcca-supply = <&vcc5v0_sys>; 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun pwrkey { 443*4882a593Smuzhiyun status = "disabled"; 444*4882a593Smuzhiyun }; 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun pinctrl_slave_rk806: pinctrl_slave_rk806 { 447*4882a593Smuzhiyun gpio-controller; 448*4882a593Smuzhiyun #gpio-cells = <2>; 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun rk806_slave_dvs1_null: rk806_slave_dvs1_null { 451*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 452*4882a593Smuzhiyun function = "pin_fun0"; 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun rk806_slave_dvs1_slp: rk806_slave_dvs1_slp { 456*4882a593Smuzhiyun pins = "gpio_pwrctrl1"; 457*4882a593Smuzhiyun function = "pin_fun1"; 458*4882a593Smuzhiyun }; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun rk806_slave_dvs1_pwrdn: rk806_slave_dvs1_pwrdn { 461*4882a593Smuzhiyun pins = "gpio_pwrctrl1"; 462*4882a593Smuzhiyun function = "pin_fun2"; 463*4882a593Smuzhiyun }; 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun rk806_slave_dvs1_rst: rk806_slave_dvs1_rst { 466*4882a593Smuzhiyun pins = "gpio_pwrctrl1"; 467*4882a593Smuzhiyun function = "pin_fun3"; 468*4882a593Smuzhiyun }; 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun rk806_slave_dvs2_null: rk806_slave_dvs2_null { 471*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 472*4882a593Smuzhiyun function = "pin_fun0"; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun rk806_slave_dvs2_slp: rk806_slave_dvs2_slp { 476*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 477*4882a593Smuzhiyun function = "pin_fun1"; 478*4882a593Smuzhiyun }; 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun rk806_slave_dvs2_pwrdn: rk806_slave_dvs2_pwrdn { 481*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 482*4882a593Smuzhiyun function = "pin_fun2"; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun 485*4882a593Smuzhiyun rk806_slave_dvs2_rst: rk806_slave_dvs2_rst { 486*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 487*4882a593Smuzhiyun function = "pin_fun3"; 488*4882a593Smuzhiyun }; 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun rk806_slave_dvs2_dvs: rk806_slave_dvs2_dvs { 491*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 492*4882a593Smuzhiyun function = "pin_fun4"; 493*4882a593Smuzhiyun }; 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun rk806_slave_dvs2_gpio: rk806_slave_dvs2_gpio { 496*4882a593Smuzhiyun pins = "gpio_pwrctrl2"; 497*4882a593Smuzhiyun function = "pin_fun5"; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun rk806_slave_dvs3_null: rk806_slave_dvs3_null { 501*4882a593Smuzhiyun pins = "gpio_pwrctrl3"; 502*4882a593Smuzhiyun function = "pin_fun0"; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun rk806_slave_dvs3_slp: rk806_slave_dvs3_slp { 506*4882a593Smuzhiyun pins = "gpio_pwrctrl3"; 507*4882a593Smuzhiyun function = "pin_fun1"; 508*4882a593Smuzhiyun }; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun rk806_slave_dvs3_pwrdn: rk806_slave_dvs3_pwrdn { 511*4882a593Smuzhiyun pins = "gpio_pwrctrl3"; 512*4882a593Smuzhiyun function = "pin_fun2"; 513*4882a593Smuzhiyun }; 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun rk806_slave_dvs3_rst: rk806_slave_dvs3_rst { 516*4882a593Smuzhiyun pins = "gpio_pwrctrl3"; 517*4882a593Smuzhiyun function = "pin_fun3"; 518*4882a593Smuzhiyun }; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun rk806_slave_dvs3_dvs: rk806_slave_dvs3_dvs { 521*4882a593Smuzhiyun pins = "gpio_pwrctrl3"; 522*4882a593Smuzhiyun function = "pin_fun4"; 523*4882a593Smuzhiyun }; 524*4882a593Smuzhiyun 525*4882a593Smuzhiyun rk806_slave_dvs3_gpio: rk806_slave_dvs3_gpio { 526*4882a593Smuzhiyun pins = "gpio_pwrctrl3"; 527*4882a593Smuzhiyun function = "pin_fun5"; 528*4882a593Smuzhiyun }; 529*4882a593Smuzhiyun }; 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun regulators { 532*4882a593Smuzhiyun vdd_cpu_big1_s0: DCDC_REG1 { 533*4882a593Smuzhiyun regulator-always-on; 534*4882a593Smuzhiyun regulator-boot-on; 535*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 536*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 537*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 538*4882a593Smuzhiyun regulator-name = "vdd_cpu_big1_s0"; 539*4882a593Smuzhiyun regulator-state-mem { 540*4882a593Smuzhiyun regulator-off-in-suspend; 541*4882a593Smuzhiyun }; 542*4882a593Smuzhiyun }; 543*4882a593Smuzhiyun 544*4882a593Smuzhiyun vdd_cpu_big0_s0: DCDC_REG2 { 545*4882a593Smuzhiyun regulator-always-on; 546*4882a593Smuzhiyun regulator-boot-on; 547*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 548*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 549*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 550*4882a593Smuzhiyun regulator-name = "vdd_cpu_big0_s0"; 551*4882a593Smuzhiyun regulator-state-mem { 552*4882a593Smuzhiyun regulator-off-in-suspend; 553*4882a593Smuzhiyun }; 554*4882a593Smuzhiyun }; 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun vdd_cpu_lit_s0: DCDC_REG3 { 557*4882a593Smuzhiyun regulator-always-on; 558*4882a593Smuzhiyun regulator-boot-on; 559*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 560*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 561*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 562*4882a593Smuzhiyun regulator-name = "vdd_cpu_lit_s0"; 563*4882a593Smuzhiyun regulator-state-mem { 564*4882a593Smuzhiyun regulator-off-in-suspend; 565*4882a593Smuzhiyun }; 566*4882a593Smuzhiyun }; 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun vcc_3v3_s0: DCDC_REG4 { 569*4882a593Smuzhiyun regulator-always-on; 570*4882a593Smuzhiyun regulator-boot-on; 571*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 572*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 573*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 574*4882a593Smuzhiyun regulator-name = "vcc_3v3_s0"; 575*4882a593Smuzhiyun regulator-state-mem { 576*4882a593Smuzhiyun regulator-off-in-suspend; 577*4882a593Smuzhiyun }; 578*4882a593Smuzhiyun }; 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun vdd_cpu_big1_mem_s0: DCDC_REG5 { 581*4882a593Smuzhiyun regulator-always-on; 582*4882a593Smuzhiyun regulator-boot-on; 583*4882a593Smuzhiyun regulator-min-microvolt = <675000>; 584*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 585*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 586*4882a593Smuzhiyun regulator-name = "vdd_cpu_big1_mem_s0"; 587*4882a593Smuzhiyun regulator-state-mem { 588*4882a593Smuzhiyun regulator-off-in-suspend; 589*4882a593Smuzhiyun }; 590*4882a593Smuzhiyun }; 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun 593*4882a593Smuzhiyun vdd_cpu_big0_mem_s0: DCDC_REG6 { 594*4882a593Smuzhiyun regulator-always-on; 595*4882a593Smuzhiyun regulator-boot-on; 596*4882a593Smuzhiyun regulator-min-microvolt = <675000>; 597*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 598*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 599*4882a593Smuzhiyun regulator-name = "vdd_cpu_big0_mem_s0"; 600*4882a593Smuzhiyun regulator-state-mem { 601*4882a593Smuzhiyun regulator-off-in-suspend; 602*4882a593Smuzhiyun }; 603*4882a593Smuzhiyun }; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun vcc_1v8_s0: DCDC_REG7 { 606*4882a593Smuzhiyun regulator-always-on; 607*4882a593Smuzhiyun regulator-boot-on; 608*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 609*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 610*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 611*4882a593Smuzhiyun regulator-name = "vcc_1v8_s0"; 612*4882a593Smuzhiyun regulator-state-mem { 613*4882a593Smuzhiyun regulator-off-in-suspend; 614*4882a593Smuzhiyun }; 615*4882a593Smuzhiyun }; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun vdd_cpu_lit_mem_s0: DCDC_REG8 { 618*4882a593Smuzhiyun regulator-always-on; 619*4882a593Smuzhiyun regulator-boot-on; 620*4882a593Smuzhiyun regulator-min-microvolt = <675000>; 621*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 622*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 623*4882a593Smuzhiyun regulator-name = "vdd_cpu_lit_mem_s0"; 624*4882a593Smuzhiyun regulator-state-mem { 625*4882a593Smuzhiyun regulator-off-in-suspend; 626*4882a593Smuzhiyun }; 627*4882a593Smuzhiyun }; 628*4882a593Smuzhiyun 629*4882a593Smuzhiyun vddq_ddr_s0: DCDC_REG9 { 630*4882a593Smuzhiyun regulator-always-on; 631*4882a593Smuzhiyun regulator-boot-on; 632*4882a593Smuzhiyun regulator-name = "vddq_ddr_s0"; 633*4882a593Smuzhiyun regulator-state-mem { 634*4882a593Smuzhiyun regulator-off-in-suspend; 635*4882a593Smuzhiyun }; 636*4882a593Smuzhiyun }; 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun vdd_ddr_s0: DCDC_REG10 { 639*4882a593Smuzhiyun regulator-always-on; 640*4882a593Smuzhiyun regulator-boot-on; 641*4882a593Smuzhiyun regulator-min-microvolt = <675000>; 642*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 643*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 644*4882a593Smuzhiyun regulator-name = "vdd_ddr_s0"; 645*4882a593Smuzhiyun regulator-state-mem { 646*4882a593Smuzhiyun regulator-off-in-suspend; 647*4882a593Smuzhiyun }; 648*4882a593Smuzhiyun }; 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun vcc_1v8_cam_s0: PLDO_REG1 { 651*4882a593Smuzhiyun regulator-always-on; 652*4882a593Smuzhiyun regulator-boot-on; 653*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 654*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 655*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 656*4882a593Smuzhiyun regulator-name = "vcc_1v8_cam_s0"; 657*4882a593Smuzhiyun regulator-state-mem { 658*4882a593Smuzhiyun regulator-off-in-suspend; 659*4882a593Smuzhiyun }; 660*4882a593Smuzhiyun }; 661*4882a593Smuzhiyun 662*4882a593Smuzhiyun avdd1v8_ddr_pll_s0: PLDO_REG2 { 663*4882a593Smuzhiyun regulator-always-on; 664*4882a593Smuzhiyun regulator-boot-on; 665*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 666*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 667*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 668*4882a593Smuzhiyun regulator-name = "avdd1v8_ddr_pll_s0"; 669*4882a593Smuzhiyun regulator-state-mem { 670*4882a593Smuzhiyun regulator-off-in-suspend; 671*4882a593Smuzhiyun }; 672*4882a593Smuzhiyun }; 673*4882a593Smuzhiyun 674*4882a593Smuzhiyun vdd_1v8_pll_s0: PLDO_REG3 { 675*4882a593Smuzhiyun regulator-always-on; 676*4882a593Smuzhiyun regulator-boot-on; 677*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 678*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 679*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 680*4882a593Smuzhiyun regulator-name = "vdd_1v8_pll_s0"; 681*4882a593Smuzhiyun regulator-state-mem { 682*4882a593Smuzhiyun regulator-off-in-suspend; 683*4882a593Smuzhiyun }; 684*4882a593Smuzhiyun }; 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun vcc_3v3_sd_s0: PLDO_REG4 { 687*4882a593Smuzhiyun regulator-always-on; 688*4882a593Smuzhiyun regulator-boot-on; 689*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 690*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 691*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 692*4882a593Smuzhiyun regulator-name = "vcc_3v3_sd_s0"; 693*4882a593Smuzhiyun regulator-state-mem { 694*4882a593Smuzhiyun regulator-off-in-suspend; 695*4882a593Smuzhiyun }; 696*4882a593Smuzhiyun }; 697*4882a593Smuzhiyun 698*4882a593Smuzhiyun vcc_2v8_cam_s0: PLDO_REG5 { 699*4882a593Smuzhiyun regulator-always-on; 700*4882a593Smuzhiyun regulator-boot-on; 701*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 702*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 703*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 704*4882a593Smuzhiyun regulator-name = "vcc_2v8_cam_s0"; 705*4882a593Smuzhiyun regulator-state-mem { 706*4882a593Smuzhiyun regulator-off-in-suspend; 707*4882a593Smuzhiyun }; 708*4882a593Smuzhiyun }; 709*4882a593Smuzhiyun 710*4882a593Smuzhiyun pldo6_s3: PLDO_REG6 { 711*4882a593Smuzhiyun regulator-always-on; 712*4882a593Smuzhiyun regulator-boot-on; 713*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 714*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 715*4882a593Smuzhiyun regulator-name = "pldo6_s3"; 716*4882a593Smuzhiyun regulator-state-mem { 717*4882a593Smuzhiyun regulator-on-in-suspend; 718*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 719*4882a593Smuzhiyun }; 720*4882a593Smuzhiyun }; 721*4882a593Smuzhiyun 722*4882a593Smuzhiyun vdd_0v75_pll_s0: NLDO_REG1 { 723*4882a593Smuzhiyun regulator-always-on; 724*4882a593Smuzhiyun regulator-boot-on; 725*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 726*4882a593Smuzhiyun regulator-max-microvolt = <750000>; 727*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 728*4882a593Smuzhiyun regulator-name = "vdd_0v75_pll_s0"; 729*4882a593Smuzhiyun regulator-state-mem { 730*4882a593Smuzhiyun regulator-off-in-suspend; 731*4882a593Smuzhiyun }; 732*4882a593Smuzhiyun }; 733*4882a593Smuzhiyun 734*4882a593Smuzhiyun vdd_ddr_pll_s0: NLDO_REG2 { 735*4882a593Smuzhiyun regulator-always-on; 736*4882a593Smuzhiyun regulator-boot-on; 737*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 738*4882a593Smuzhiyun regulator-max-microvolt = <850000>; 739*4882a593Smuzhiyun regulator-name = "vdd_ddr_pll_s0"; 740*4882a593Smuzhiyun regulator-state-mem { 741*4882a593Smuzhiyun regulator-off-in-suspend; 742*4882a593Smuzhiyun }; 743*4882a593Smuzhiyun }; 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun avdd_0v85_s0: NLDO_REG3 { 746*4882a593Smuzhiyun regulator-always-on; 747*4882a593Smuzhiyun regulator-boot-on; 748*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 749*4882a593Smuzhiyun regulator-max-microvolt = <850000>; 750*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 751*4882a593Smuzhiyun regulator-name = "avdd_0v85_s0"; 752*4882a593Smuzhiyun regulator-state-mem { 753*4882a593Smuzhiyun regulator-off-in-suspend; 754*4882a593Smuzhiyun }; 755*4882a593Smuzhiyun }; 756*4882a593Smuzhiyun 757*4882a593Smuzhiyun avdd_1v2_cam_s0: NLDO_REG4 { 758*4882a593Smuzhiyun regulator-always-on; 759*4882a593Smuzhiyun regulator-boot-on; 760*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 761*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 762*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 763*4882a593Smuzhiyun regulator-name = "avdd_1v2_cam_s0"; 764*4882a593Smuzhiyun regulator-state-mem { 765*4882a593Smuzhiyun regulator-off-in-suspend; 766*4882a593Smuzhiyun }; 767*4882a593Smuzhiyun }; 768*4882a593Smuzhiyun 769*4882a593Smuzhiyun avdd_1v2_s0: NLDO_REG5 { 770*4882a593Smuzhiyun regulator-always-on; 771*4882a593Smuzhiyun regulator-boot-on; 772*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 773*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 774*4882a593Smuzhiyun regulator-ramp-delay = <12500>; 775*4882a593Smuzhiyun regulator-name = "avdd_1v2_s0"; 776*4882a593Smuzhiyun regulator-state-mem { 777*4882a593Smuzhiyun regulator-off-in-suspend; 778*4882a593Smuzhiyun }; 779*4882a593Smuzhiyun }; 780*4882a593Smuzhiyun }; 781*4882a593Smuzhiyun }; 782*4882a593Smuzhiyun}; 783