1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun aliases { 9*4882a593Smuzhiyun mmc0 = &sdhci; 10*4882a593Smuzhiyun mmc1 = &sdmmc; 11*4882a593Smuzhiyun mmc2 = &sdio; 12*4882a593Smuzhiyun }; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun chosen: chosen { 15*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTUUID=614e0000-0000 rw rootwait"; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun cspmu: cspmu@fd10c000 { 19*4882a593Smuzhiyun compatible = "rockchip,cspmu"; 20*4882a593Smuzhiyun reg = <0x0 0xfd10c000 0x0 0x1000>, 21*4882a593Smuzhiyun <0x0 0xfd10d000 0x0 0x1000>, 22*4882a593Smuzhiyun <0x0 0xfd10e000 0x0 0x1000>, 23*4882a593Smuzhiyun <0x0 0xfd10f000 0x0 0x1000>, 24*4882a593Smuzhiyun <0x0 0xfd12c000 0x0 0x1000>, 25*4882a593Smuzhiyun <0x0 0xfd12d000 0x0 0x1000>, 26*4882a593Smuzhiyun <0x0 0xfd12e000 0x0 0x1000>, 27*4882a593Smuzhiyun <0x0 0xfd12f000 0x0 0x1000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun debug: debug@fd104000 { 31*4882a593Smuzhiyun compatible = "rockchip,debug"; 32*4882a593Smuzhiyun reg = <0x0 0xfd104000 0x0 0x1000>, 33*4882a593Smuzhiyun <0x0 0xfd105000 0x0 0x1000>, 34*4882a593Smuzhiyun <0x0 0xfd106000 0x0 0x1000>, 35*4882a593Smuzhiyun <0x0 0xfd107000 0x0 0x1000>, 36*4882a593Smuzhiyun <0x0 0xfd124000 0x0 0x1000>, 37*4882a593Smuzhiyun <0x0 0xfd125000 0x0 0x1000>, 38*4882a593Smuzhiyun <0x0 0xfd126000 0x0 0x1000>, 39*4882a593Smuzhiyun <0x0 0xfd127000 0x0 0x1000>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun fiq_debugger: fiq-debugger { 43*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 44*4882a593Smuzhiyun rockchip,serial-id = <2>; 45*4882a593Smuzhiyun rockchip,wake-irq = <0>; 46*4882a593Smuzhiyun /* If enable uart uses irq instead of fiq */ 47*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 48*4882a593Smuzhiyun rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 49*4882a593Smuzhiyun interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_LOW>; 50*4882a593Smuzhiyun pinctrl-names = "default"; 51*4882a593Smuzhiyun pinctrl-0 = <&uart2m0_xfer>; 52*4882a593Smuzhiyun status = "okay"; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun firmware { 56*4882a593Smuzhiyun optee: optee { 57*4882a593Smuzhiyun compatible = "linaro,optee-tz"; 58*4882a593Smuzhiyun method = "smc"; 59*4882a593Smuzhiyun //status = "disabled"; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun reserved-memory { 64*4882a593Smuzhiyun #address-cells = <2>; 65*4882a593Smuzhiyun #size-cells = <2>; 66*4882a593Smuzhiyun ranges; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun cma { 69*4882a593Smuzhiyun compatible = "shared-dma-pool"; 70*4882a593Smuzhiyun reusable; 71*4882a593Smuzhiyun size = <0x0 (8 * 0x100000)>; 72*4882a593Smuzhiyun linux,cma-default; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun drm_logo: drm-logo@00000000 { 76*4882a593Smuzhiyun compatible = "rockchip,drm-logo"; 77*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x0>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun drm_cubic_lut: drm-cubic-lut@00000000 { 81*4882a593Smuzhiyun compatible = "rockchip,drm-cubic-lut"; 82*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x0>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun ramoops: ramoops@110000 { 86*4882a593Smuzhiyun compatible = "ramoops"; 87*4882a593Smuzhiyun reg = <0x0 0x110000 0x0 0xf0000>; 88*4882a593Smuzhiyun record-size = <0x20000>; 89*4882a593Smuzhiyun console-size = <0x80000>; 90*4882a593Smuzhiyun ftrace-size = <0x00000>; 91*4882a593Smuzhiyun pmsg-size = <0x50000>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun}; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun&display_subsystem { 97*4882a593Smuzhiyun memory-region = <&drm_logo>; 98*4882a593Smuzhiyun memory-region-names = "drm-logo"; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun&dfi { 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun}; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun&dmc { 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun center-supply = <&vdd_ddr_s0>; 108*4882a593Smuzhiyun mem-supply = <&vdd_log_s0>; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun&rng { 112*4882a593Smuzhiyun status = "okay"; 113*4882a593Smuzhiyun}; 114