1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/display/media-bus-format.h> 8#define LINK_FREQ 700000000 9 10 11&mipi_dcphy0 { 12 status = "okay"; 13}; 14 15&mipi_dcphy1 { 16 status = "okay"; 17}; 18 19&csi2_dcphy0 { 20 status = "okay"; 21 22 ports { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 port@0 { 26 reg = <0>; 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 csidcphy0_in: endpoint@1 { 31 reg = <1>; 32 remote-endpoint = <&rk1608_dphy0_out>; 33 data-lanes = <1 2>; 34 }; 35 }; 36 port@1 { 37 reg = <1>; 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 csidcphy0_out: endpoint@0 { 42 reg = <0>; 43 remote-endpoint = <&mipi0_csi2_input>; 44 }; 45 }; 46 }; 47}; 48 49&csi2_dcphy1 { 50 status = "okay"; 51 52 ports { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 port@0 { 56 reg = <0>; 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 csidcphy1_in: endpoint@1 { 61 reg = <1>; 62 remote-endpoint = <&imx464_out>; 63 data-lanes = <1 2>; 64 }; 65 }; 66 port@1 { 67 reg = <1>; 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 csidcphy1_out: endpoint@0 { 72 reg = <0>; 73 remote-endpoint = <&mipi1_csi2_input>; 74 }; 75 }; 76 }; 77}; 78 79&csi2_dphy0_hw { 80 status = "okay"; 81}; 82 83&csi2_dphy1_hw { 84 status = "okay"; 85}; 86 87&csi2_dphy1 { 88 status = "okay"; 89 90 ports { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 port@0 { 94 reg = <0>; 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 csidphy1_in: endpoint@1 { 99 reg = <1>; 100 remote-endpoint = <&imx464_out0>; 101 data-lanes = <1 2>; 102 }; 103 }; 104 port@1 { 105 reg = <1>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 109 csidphy1_out: endpoint@0 { 110 reg = <0>; 111 remote-endpoint = <&mipi2_csi2_input>; 112 }; 113 }; 114 }; 115}; 116 117&csi2_dphy2 { 118 status = "okay"; 119 120 ports { 121 #address-cells = <1>; 122 #size-cells = <0>; 123 port@0 { 124 reg = <0>; 125 #address-cells = <1>; 126 #size-cells = <0>; 127 128 csidphy2_in: endpoint@1 { 129 reg = <1>; 130 remote-endpoint = <&imx464_out1>; 131 data-lanes = <1 2>; 132 }; 133 }; 134 port@1 { 135 reg = <1>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 csidphy2_out: endpoint@0 { 140 reg = <0>; 141 remote-endpoint = <&mipi3_csi2_input>; 142 }; 143 }; 144 }; 145}; 146 147&csi2_dphy4 { 148 status = "okay"; 149 150 ports { 151 #address-cells = <1>; 152 #size-cells = <0>; 153 port@0 { 154 reg = <0>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 158 csidphy4_in: endpoint@1 { 159 reg = <1>; 160 remote-endpoint = <&imx464_out2>; 161 data-lanes = <1 2>; 162 }; 163 }; 164 port@1 { 165 reg = <1>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 169 csidphy4_out: endpoint@0 { 170 reg = <0>; 171 remote-endpoint = <&mipi4_csi2_input>; 172 }; 173 }; 174 }; 175}; 176 177&csi2_dphy5 { 178 status = "okay"; 179 180 ports { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 port@0 { 184 reg = <0>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 188 csidphy5_in: endpoint@1 { 189 reg = <1>; 190 remote-endpoint = <&imx464_out3>; 191 data-lanes = <1 2>; 192 }; 193 }; 194 port@1 { 195 reg = <1>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 csidphy5_out: endpoint@0 { 200 reg = <0>; 201 remote-endpoint = <&mipi5_csi2_input>; 202 }; 203 }; 204 }; 205}; 206 207&mipi0_csi2 { 208 status = "okay"; 209 210 ports { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 214 port@0 { 215 reg = <0>; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 219 mipi0_csi2_input: endpoint@1 { 220 reg = <1>; 221 remote-endpoint = <&csidcphy0_out>; 222 }; 223 }; 224 225 port@1 { 226 reg = <1>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 230 mipi0_csi2_output: endpoint@0 { 231 reg = <0>; 232 remote-endpoint = <&cif_mipi_in0>; 233 }; 234 }; 235 }; 236}; 237 238&mipi1_csi2 { 239 status = "okay"; 240 241 ports { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 245 port@0 { 246 reg = <0>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 250 mipi1_csi2_input: endpoint@1 { 251 reg = <1>; 252 remote-endpoint = <&csidcphy1_out>; 253 }; 254 }; 255 256 port@1 { 257 reg = <1>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 261 mipi1_csi2_output: endpoint@0 { 262 reg = <0>; 263 remote-endpoint = <&cif_mipi_in1>; 264 }; 265 }; 266 }; 267}; 268 269&mipi2_csi2 { 270 status = "okay"; 271 272 ports { 273 #address-cells = <1>; 274 #size-cells = <0>; 275 276 port@0 { 277 reg = <0>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 281 mipi2_csi2_input: endpoint@1 { 282 reg = <1>; 283 remote-endpoint = <&csidphy1_out>; 284 }; 285 }; 286 287 port@1 { 288 reg = <1>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 292 mipi2_csi2_output: endpoint@0 { 293 reg = <0>; 294 remote-endpoint = <&cif_mipi_in2>; 295 }; 296 }; 297 }; 298}; 299 300&mipi3_csi2 { 301 status = "okay"; 302 303 ports { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 307 port@0 { 308 reg = <0>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 312 mipi3_csi2_input: endpoint@1 { 313 reg = <1>; 314 remote-endpoint = <&csidphy2_out>; 315 }; 316 }; 317 318 port@1 { 319 reg = <1>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 323 mipi3_csi2_output: endpoint@0 { 324 reg = <0>; 325 remote-endpoint = <&cif_mipi_in3>; 326 }; 327 }; 328 }; 329}; 330 331&mipi4_csi2 { 332 status = "okay"; 333 334 ports { 335 #address-cells = <1>; 336 #size-cells = <0>; 337 338 port@0 { 339 reg = <0>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 343 mipi4_csi2_input: endpoint@1 { 344 reg = <1>; 345 remote-endpoint = <&csidphy4_out>; 346 }; 347 }; 348 349 port@1 { 350 reg = <1>; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 354 mipi4_csi2_output: endpoint@0 { 355 reg = <0>; 356 remote-endpoint = <&cif_mipi_in4>; 357 }; 358 }; 359 }; 360}; 361 362&mipi5_csi2 { 363 status = "okay"; 364 365 ports { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 369 port@0 { 370 reg = <0>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 374 mipi5_csi2_input: endpoint@1 { 375 reg = <1>; 376 remote-endpoint = <&csidphy5_out>; 377 }; 378 }; 379 380 port@1 { 381 reg = <1>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 385 mipi5_csi2_output: endpoint@0 { 386 reg = <0>; 387 remote-endpoint = <&cif_mipi_in5>; 388 }; 389 }; 390 }; 391}; 392 393&rkcif { 394 status = "okay"; 395}; 396 397&rkcif_mipi_lvds { 398 status = "okay"; 399 400 port { 401 cif_mipi_in0: endpoint { 402 remote-endpoint = <&mipi0_csi2_output>; 403 }; 404 }; 405}; 406 407&rkcif_mipi_lvds_sditf { 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "okay"; 411 rockchip,combine-index = <0>; 412 ports { 413 #address-cells = <1>; 414 #size-cells = <0>; 415 port@0 { 416 reg = <0>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 mipi_lvds_sditf_in: endpoint@1 { 420 reg = <1>; 421 remote-endpoint = <&imx464_out7>; 422 data-lanes = <1 2>; 423 }; 424 }; 425 426 port@1 { 427 reg = <1>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 mipi_lvds_sditf: endpoint@0 { 431 reg = <0>; 432 remote-endpoint = <&isp0_vir0>; 433 }; 434 }; 435 }; 436}; 437 438&rkcif_mipi_lvds_sditf_vir1 { 439 #address-cells = <1>; 440 #size-cells = <0>; 441 status = "okay"; 442 rockchip,combine-index = <1>; 443 ports { 444 #address-cells = <1>; 445 #size-cells = <0>; 446 port@0 { 447 reg = <0>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 mipi_lvds_sditf_vir1_in: endpoint@1 { 451 reg = <1>; 452 remote-endpoint = <&imx464_out6>; 453 data-lanes = <1 2>; 454 }; 455 }; 456 457 port@1 { 458 reg = <1>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 mipi_lvds_sditf_vir1: endpoint@0 { 462 reg = <0>; 463 remote-endpoint = <&isp0_vir3>; 464 }; 465 }; 466 }; 467}; 468 469&rkcif_mipi_lvds_sditf_vir2 { 470 address-cells = <1>; 471 #size-cells = <0>; 472 status = "okay"; 473 rockchip,combine-index = <2>; 474 ports { 475 #address-cells = <1>; 476 #size-cells = <0>; 477 port@0 { 478 reg = <0>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 mipi_lvds_sditf_vir2_in: endpoint@1 { 482 reg = <1>; 483 remote-endpoint = <&imx464_out5>; 484 data-lanes = <1 2>; 485 }; 486 }; 487 488 port@1 { 489 reg = <1>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 mipi_lvds_sditf_vir2: endpoint { 493 remote-endpoint = <&isp1_vir3>; 494 }; 495 }; 496 }; 497}; 498 499&rkcif_mipi_lvds1_sditf { 500 status = "okay"; 501 502 port { 503 mipi1_lvds_sditf: endpoint { 504 remote-endpoint = <&isp1_vir0>; 505 }; 506 }; 507}; 508 509&rkcif_mipi_lvds1 { 510 status = "okay"; 511 512 port { 513 cif_mipi_in1: endpoint { 514 remote-endpoint = <&mipi1_csi2_output>; 515 }; 516 }; 517}; 518 519&rkcif_mipi_lvds2 { 520 status = "okay"; 521 522 port { 523 cif_mipi_in2: endpoint { 524 remote-endpoint = <&mipi2_csi2_output>; 525 }; 526 }; 527}; 528 529&rkcif_mipi_lvds2_sditf { 530 status = "okay"; 531 532 port { 533 mipi2_lvds_sditf: endpoint { 534 remote-endpoint = <&isp0_vir1>; 535 }; 536 }; 537}; 538 539&rkcif_mipi_lvds3 { 540 status = "okay"; 541 542 port { 543 cif_mipi_in3: endpoint { 544 remote-endpoint = <&mipi3_csi2_output>; 545 }; 546 }; 547}; 548 549&rkcif_mipi_lvds3_sditf { 550 status = "okay"; 551 552 port { 553 mipi3_lvds_sditf: endpoint { 554 remote-endpoint = <&isp1_vir1>; 555 }; 556 }; 557}; 558 559&rkcif_mipi_lvds4 { 560 status = "okay"; 561 562 port { 563 cif_mipi_in4: endpoint { 564 remote-endpoint = <&mipi4_csi2_output>; 565 }; 566 }; 567}; 568 569&rkcif_mipi_lvds4_sditf { 570 status = "okay"; 571 572 port { 573 mipi4_lvds_sditf: endpoint { 574 remote-endpoint = <&isp0_vir2>; 575 }; 576 }; 577}; 578 579&rkcif_mipi_lvds5 { 580 status = "okay"; 581 582 port { 583 cif_mipi_in5: endpoint { 584 remote-endpoint = <&mipi5_csi2_output>; 585 }; 586 }; 587}; 588 589&rkcif_mipi_lvds5_sditf { 590 status = "okay"; 591 592 port { 593 mipi5_lvds_sditf: endpoint { 594 remote-endpoint = <&isp1_vir2>; 595 }; 596 }; 597}; 598 599&rkcif_mmu { 600 status = "okay"; 601}; 602 603&rkisp0 { 604 status = "okay"; 605}; 606 607&isp0_mmu { 608 status = "okay"; 609}; 610 611&rkisp0_vir0 { 612 status = "okay"; 613 614 port { 615 #address-cells = <1>; 616 #size-cells = <0>; 617 618 isp0_vir0: endpoint@0 { 619 reg = <0>; 620 remote-endpoint = <&mipi_lvds_sditf>; 621 }; 622 }; 623}; 624 625&rkisp0_vir1 { 626 status = "okay"; 627 628 port { 629 #address-cells = <1>; 630 #size-cells = <0>; 631 632 isp0_vir1: endpoint@0 { 633 reg = <0>; 634 remote-endpoint = <&mipi2_lvds_sditf>; 635 }; 636 }; 637}; 638 639&rkisp0_vir2 { 640 status = "okay"; 641 642 port { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 646 isp0_vir2: endpoint@0 { 647 reg = <0>; 648 remote-endpoint = <&mipi4_lvds_sditf>; 649 }; 650 }; 651}; 652 653&rkisp0_vir3 { 654 status = "okay"; 655 656 port { 657 #address-cells = <1>; 658 #size-cells = <0>; 659 660 isp0_vir3: endpoint@0 { 661 reg = <0>; 662 remote-endpoint = <&mipi_lvds_sditf_vir1>; 663 }; 664 }; 665}; 666 667&rkisp1 { 668 status = "okay"; 669}; 670 671&isp1_mmu { 672 status = "okay"; 673}; 674 675&rkisp1_vir0 { 676 status = "okay"; 677 678 port { 679 #address-cells = <1>; 680 #size-cells = <0>; 681 682 isp1_vir0: endpoint@0 { 683 reg = <0>; 684 remote-endpoint = <&mipi1_lvds_sditf>; 685 }; 686 }; 687}; 688 689&rkisp1_vir1 { 690 status = "okay"; 691 692 port { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 696 isp1_vir1: endpoint@0 { 697 reg = <0>; 698 remote-endpoint = <&mipi3_lvds_sditf>; 699 }; 700 }; 701}; 702 703&rkisp1_vir2 { 704 status = "okay"; 705 706 port { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 710 isp1_vir2: endpoint@0 { 711 reg = <0>; 712 remote-endpoint = <&mipi5_lvds_sditf>; 713 }; 714 }; 715}; 716 717&rkisp1_vir3 { 718 status = "okay"; 719 720 port { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 724 isp1_vir3: endpoint@0 { 725 reg = <0>; 726 remote-endpoint = <&mipi_lvds_sditf_vir2>; 727 }; 728 }; 729}; 730 731&pinctrl { 732 cam { 733 vcc_cam_2_3_pwr: vcc_cam_2_3_pwr { 734 rockchip,pins = 735 /* camera power en */ 736 <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 737 }; 738 vcc_cam_4_5_pwr: vcc_cam_4_5_pwr { 739 rockchip,pins = 740 /* camera power en */ 741 <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 742 }; 743 vcc_cam_8_9_pwr: vcc_cam_8_9_pwr { 744 rockchip,pins = 745 /* camera power en */ 746 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 747 }; 748 }; 749}; 750 751 752/ { 753 cam_ircut0: cam_ircut { 754 status = "okay"; 755 compatible = "rockchip,ircut"; 756 ircut-open-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; 757 ircut-close-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; 758 rockchip,camera-module-index = <0>; 759 rockchip,camera-module-facing = "back"; 760 }; 761 762 vcc_cam_2_3: vcc-cam-2-3 { 763 compatible = "regulator-fixed"; 764 gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 765 pinctrl-names = "default"; 766 pinctrl-0 = <&vcc_cam_2_3_pwr>; 767 regulator-name = "vcc_cam_2_3"; 768 enable-active-high; 769 }; 770 771 vcc_cam_4_5: vcc-cam-4-5 { 772 compatible = "regulator-fixed"; 773 gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; 774 pinctrl-names = "default"; 775 pinctrl-0 = <&vcc_cam_4_5_pwr>; 776 regulator-name = "vcc_cam_4_5"; 777 enable-active-high; 778 }; 779 780 vcc_cam_8_9: vcc-cam-8-9 { 781 compatible = "regulator-fixed"; 782 gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&vcc_cam_8_9_pwr>; 785 regulator-name = "vcc_cam_8_9"; 786 enable-active-high; 787 }; 788}; 789 790&i2c7 { 791 status = "okay"; 792 pinctrl-0 = <&i2c7m0_xfer>; 793 794 /* hardware cam 1 */ 795 imx464: imx464@10 { 796 compatible = "sony,imx464"; 797 reg = <0x10>; 798 clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; 799 clock-names = "xvclk"; 800 pinctrl-names = "default"; 801 pinctrl-0 = <&mipim0_camera2_clk>; 802 power-domains = <&power RK3588_PD_VI>; 803 pwdn-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; 804 avdd-supply = <&vcc_mipicsi1>; 805 rockchip,camera-module-index = <0>; 806 rockchip,camera-module-facing = "back"; 807 rockchip,camera-module-name = "CMK-OT1980-PX1"; 808 rockchip,camera-module-lens-name = "SHG102"; 809 port { 810 imx464_out: endpoint { 811 remote-endpoint = <&csidcphy1_in>; 812 data-lanes = <1 2>; 813 }; 814 }; 815 }; 816 817 /* hardware cam 2 */ 818 imx464_0: imx464-0@1a { 819 compatible = "sony,imx464"; 820 status = "okay"; 821 reg = <0x1a>; 822 clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; 823 clock-names = "xvclk"; 824 power-domains = <&power RK3588_PD_VI>; 825 pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; 826 pinctrl-names = "default"; 827 pinctrl-0 = <&mipim0_camera3_clk>; 828 avdd-supply = <&vcc_cam_2_3>; 829 rockchip,camera-module-index = <1>; 830 rockchip,camera-module-facing = "back"; 831 rockchip,camera-module-name = "CMK-OT1980-PX1"; 832 rockchip,camera-module-lens-name = "SHG102"; 833 port { 834 imx464_out0: endpoint { 835 remote-endpoint = <&csidphy1_in>; 836 data-lanes = <1 2>; 837 }; 838 }; 839 }; 840 841 /* hardware cam 3 */ 842 imx464_1: imx464-1@36 { 843 compatible = "sony,imx464"; 844 status = "okay"; 845 reg = <0x36>; 846 clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; 847 clock-names = "xvclk"; 848 power-domains = <&power RK3588_PD_VI>; 849 //pinctrl-names = "default"; 850 //pinctrl-0 = <&mipim0_camera3_clk>; //same 851 pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; 852 avdd-supply = <&vcc_cam_2_3>; 853 rockchip,camera-module-index = <2>; 854 rockchip,camera-module-facing = "back"; 855 rockchip,camera-module-name = "CMK-OT1980-PX1"; 856 rockchip,camera-module-lens-name = "SHG102"; 857 port { 858 imx464_out1: endpoint { 859 remote-endpoint = <&csidphy2_in>; 860 data-lanes = <1 2>; 861 }; 862 }; 863 }; 864}; 865 866&i2c4 { 867 status = "okay"; 868 pinctrl-0 = <&i2c4m1_xfer>; 869 870 /* hardware cam 4 */ 871 imx464_2: imx464-2@1a { 872 compatible = "sony,imx464"; 873 status = "okay"; 874 reg = <0x1a>; 875 clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; 876 clock-names = "xvclk"; 877 power-domains = <&power RK3588_PD_VI>; 878 pinctrl-names = "default"; 879 pinctrl-0 = <&mipim0_camera4_clk>; 880 avdd-supply = <&vcc_cam_4_5>; 881 pwdn-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; 882 rockchip,camera-module-index = <3>; 883 rockchip,camera-module-facing = "back"; 884 rockchip,camera-module-name = "CMK-OT1980-PX1"; 885 rockchip,camera-module-lens-name = "SHG102"; 886 port { 887 imx464_out2: endpoint { 888 remote-endpoint = <&csidphy4_in>; 889 data-lanes = <1 2>; 890 }; 891 }; 892 }; 893 894 /* hardware cam 5 */ 895 imx464_3: imx464-3@36 { 896 compatible = "sony,imx464"; 897 status = "okay"; 898 reg = <0x36>; 899 clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; 900 clock-names = "xvclk"; 901 power-domains = <&power RK3588_PD_VI>; 902 //pinctrl-names = "default"; 903 //pinctrl-0 = <&mipim0_camera4_clk>; 904 avdd-supply = <&vcc_cam_4_5>; 905 pwdn-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; 906 rockchip,camera-module-index = <4>; 907 rockchip,camera-module-facing = "back"; 908 rockchip,camera-module-name = "CMK-OT1980-PX1"; 909 rockchip,camera-module-lens-name = "SHG102"; 910 port { 911 imx464_out3: endpoint { 912 remote-endpoint = <&csidphy5_in>; 913 data-lanes = <1 2>; 914 }; 915 }; 916 }; 917}; 918 919&i2c2 { 920 status = "okay"; 921 pinctrl-0 = <&i2c2m4_xfer>; 922 923 /* hardware cam 6 */ 924 imx464_4: imx464-4@1a { 925 compatible = "sony,imx464"; 926 status = "disabled"; 927 reg = <0x1a>; 928 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; 929 clock-names = "xvclk"; 930 power-domains = <&power RK3588_PD_VI>; 931 //pinctrl-names = "default"; 932 //pinctrl-0 = <&mipim0_camera1_clk>; 933 avdd-supply = <&vcc_mipicsi0>; 934 pwdn-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; 935 rockchip,camera-module-index = <8>; 936 rockchip,camera-module-facing = "back"; 937 rockchip,camera-module-name = "CMK-OT1980-PX1"; 938 rockchip,camera-module-lens-name = "SHG102"; 939 port { 940 imx464_out4: endpoint { 941 //remote-endpoint = <&mipi_lvds_sditf_vir3>; 942 data-lanes = <1 2>; 943 }; 944 }; 945 }; 946 947 /* hardware cam 7 */ 948 imx464_5: imx464-5@36 { 949 compatible = "sony,imx464"; 950 status = "okay"; 951 reg = <0x36>; 952 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; 953 clock-names = "xvclk"; 954 power-domains = <&power RK3588_PD_VI>; 955 pinctrl-names = "default"; 956 pinctrl-0 = <&mipim0_camera1_clk>; 957 avdd-supply = <&vcc_mipicsi0>; 958 pwdn-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; 959 rockchip,camera-module-index = <7>; 960 rockchip,camera-module-facing = "back"; 961 rockchip,camera-module-name = "CMK-OT1980-PX1"; 962 rockchip,camera-module-lens-name = "SHG102"; 963 port { 964 imx464_out5: endpoint { 965 remote-endpoint = <&mipi_lvds_sditf_vir2_in>; 966 data-lanes = <1 2>; 967 }; 968 }; 969 }; 970}; 971 972&i2c3 { 973 status = "okay"; 974 pinctrl-0 = <&i2c3m0_xfer>; 975 976 /* hardware cam 8 */ 977 imx464_6: imx464-6@1a { 978 compatible = "sony,imx464"; 979 status = "okay"; 980 reg = <0x1a>; 981 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; 982 clock-names = "xvclk"; 983 power-domains = <&power RK3588_PD_VI>; 984 //pinctrl-names = "default"; 985 //pinctrl-0 = <&mipim0_camera1_clk>; 986 avdd-supply = <&vcc_cam_8_9>; 987 pwdn-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; 988 rockchip,camera-module-index = <6>; 989 rockchip,camera-module-facing = "back"; 990 rockchip,camera-module-name = "CMK-OT1980-PX1"; 991 rockchip,camera-module-lens-name = "SHG102"; 992 port { 993 imx464_out6: endpoint { 994 remote-endpoint = <&mipi_lvds_sditf_vir1_in>; 995 data-lanes = <1 2>; 996 }; 997 }; 998 }; 999 1000 /* hardware cam 9 */ 1001 imx464_7: imx464-7@36 { 1002 compatible = "sony,imx464"; 1003 status = "okay"; 1004 reg = <0x36>; 1005 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; 1006 clock-names = "xvclk"; 1007 power-domains = <&power RK3588_PD_VI>; 1008 //pinctrl-names = "default"; 1009 //pinctrl-0 = <&mipim0_camera1_clk>; 1010 avdd-supply = <&vcc_cam_8_9>; 1011 pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; 1012 rockchip,camera-module-index = <5>; 1013 rockchip,camera-module-facing = "back"; 1014 rockchip,camera-module-name = "CMK-OT1980-PX1"; 1015 rockchip,camera-module-lens-name = "SHG102"; 1016 port { 1017 imx464_out7: endpoint { 1018 remote-endpoint = <&mipi_lvds_sditf_in>; 1019 data-lanes = <1 2>; 1020 }; 1021 }; 1022 }; 1023 1024 preisp_dmy: preisp_dmy@37 { 1025 status = "okay"; 1026 compatible = "pisp_dmy"; 1027 reg = <0x37>; 1028 1029 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; 1030 clock-names = "xvclk"; 1031 1032 rockchip,camera-module-index = <10>; 1033 rockchip,camera-module-facing = "back"; 1034 rockchip,camera-module-name = "CMK-OT1980-PX1"; 1035 rockchip,camera-module-lens-name = "SHG102"; 1036 port { 1037 preisp_dmy_out0: endpoint { 1038 remote-endpoint = <&rk1608_in0>; 1039 data-lanes = <1 2 3 4>; 1040 }; 1041 }; 1042 }; 1043}; 1044 1045&spi4 { 1046 status = "okay"; 1047 //assigned-clocks = <&cru CLK_SPI0>; 1048 //assigned-clock-rates = <100000000>; 1049 //rx-sample-delay-ns = <10>; 1050 //dma-names = "tx", "rx"; 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&spi4m1_cs0 &spi4m1_cs1 &spi4m1_pins>; 1053 1054 spi_rk1608@0 { 1055 compatible = "rockchip,rk1608"; 1056 status = "okay"; 1057 reg = <0>; 1058 spi-max-frequency = <50000000>; 1059 spi-min-frequency = <16000000>; 1060 1061 clocks = <&cru CLK_SPI4>; 1062 clock-names = "mclk"; 1063 1064 firmware-names = "rk1608.rkl"; 1065 1066 reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; 1067 irq-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; 1068 //wake-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; 1069 pwren-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&preisp_irq_gpios &preisp_pwren_gpios 1072 &preisp_reset_gpios &refclk_pins>; 1073 1074 /* regulator config */ 1075 vdd-core-regulator = "vdd_preisp"; 1076 vdd-core-microvolt = <1150000>; 1077 ports { 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 port@0 { 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 1084 reg = <0>; 1085 rk1608_out0: endpoint@0 { 1086 reg = <0>; 1087 remote-endpoint = <&rk1608_dphy0_in>; 1088 }; 1089 }; 1090 1091 port@1 { 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 1095 reg = <1>; 1096 rk1608_in0: endpoint@0 { 1097 reg = <0>; 1098 remote-endpoint = <&preisp_dmy_out0>; 1099 }; 1100 }; 1101 }; 1102 }; 1103}; 1104 1105&pinctrl { 1106 rk1608_gpios { 1107 preisp_irq_gpios: preisp-irq-gpios { 1108 rockchip,pins = 1109 <1 RK_PC4 0 &pcfg_pull_up>; 1110 }; 1111 preisp_reset_gpios: preisp-reset-gpios { 1112 rockchip,pins = 1113 <1 RK_PD5 0 &pcfg_output_low>; 1114 }; 1115 preisp_pwren_gpios: preisp-pwren-gpios { 1116 rockchip,pins = 1117 <1 RK_PC7 0 &pcfg_pull_up>; 1118 }; 1119 }; 1120}; 1121 1122/{ 1123 mipidphy0: mipidphy0 { 1124 compatible = "rockchip,rk1608-dphy"; 1125 status = "okay"; 1126 //rockchip,grf = <&grf>; 1127 id = <0>; 1128 1129 cam_nums = <1>; 1130 in_mipi = <1>; 1131 out_mipi = <0>; 1132 link-freqs = /bits/ 64 <LINK_FREQ>; 1133 1134 /* rk1608 i2c mode */ 1135 sensor_i2c_bus = <3>; 1136 sensor_i2c_addr = <0x36>; 1137 sensor-name = "IMX464"; 1138 1139 rockchip,camera-module-index = <9>; 1140 rockchip,camera-module-facing = "back"; 1141 rockchip,camera-module-name = "TongJu"; 1142 rockchip,camera-module-lens-name = "CHT842-MD"; 1143 1144 /* virtual-sensor mode */ 1145 link-sensor = <&imx464_7>; 1146 virtual-sub-sensor-config-0 { 1147 id = <1>; 1148 in_mipi = <2>; 1149 out_mipi = <1>; 1150 }; 1151 virtual-sub-sensor-config-1 { 1152 id = <2>; 1153 in_mipi = <3>; 1154 out_mipi = <1>; 1155 }; 1156 /* multi-sensor mode end */ 1157 1158 format-config-0 { 1159 data_type = <0x2b>; 1160 mipi_lane = <2>; 1161 mipi_lane_out = <4>; 1162 field = <1>; 1163 colorspace = <8>; 1164 code = <MEDIA_BUS_FMT_SRGGB10_1X10>; 1165 width = <2712>; 1166 height= <1538>; 1167 hactive = <2712>; 1168 vactive = <4614>; 1169 htotal = <3616>; 1170 vtotal = <4710>; 1171 inch0-info = <2712 1538 0x2b 0x2b 1>; 1172 outch0-info = <2712 4614 0x2b 0x2b 1>; 1173 hcrop = <2560>; 1174 vcrop = <1520>; 1175 }; 1176 1177 ports { 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 1181 port@0 { 1182 rk1608_dphy0_in: endpoint { 1183 remote-endpoint = <&rk1608_out0>; 1184 data-lanes = <1 2 3 4>; 1185 }; 1186 }; 1187 port@1 { 1188 rk1608_dphy0_out: endpoint { 1189 remote-endpoint = <&csidcphy0_in>; 1190 clock-lanes = <0>; 1191 data-lanes = <1 2 3 4>; 1192 clock-noncontinuous; 1193 link-freqs = /bits/ 64 <LINK_FREQ>; 1194 }; 1195 }; 1196 }; 1197 }; 1198}; 1199