1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include "dt-bindings/usb/pd.h" 8#include "rk3588.dtsi" 9#include "rk3588-evb.dtsi" 10#include "rk3588-rk806-dual.dtsi" 11 12/ { 13 pcie20_avdd0v85: pcie20-avdd0v85 { 14 compatible = "regulator-fixed"; 15 regulator-name = "pcie20_avdd0v85"; 16 regulator-boot-on; 17 regulator-always-on; 18 regulator-min-microvolt = <850000>; 19 regulator-max-microvolt = <850000>; 20 vin-supply = <&avdd_0v85_s0>; 21 }; 22 23 pcie20_avdd1v8: pcie20-avdd1v8 { 24 compatible = "regulator-fixed"; 25 regulator-name = "pcie20_avdd1v8"; 26 regulator-boot-on; 27 regulator-always-on; 28 regulator-min-microvolt = <1800000>; 29 regulator-max-microvolt = <1800000>; 30 vin-supply = <&avcc_1v8_s0>; 31 }; 32 33 pcie30_avdd0v75: pcie30-avdd0v75 { 34 compatible = "regulator-fixed"; 35 regulator-name = "pcie30_avdd0v75"; 36 regulator-boot-on; 37 regulator-always-on; 38 regulator-min-microvolt = <750000>; 39 regulator-max-microvolt = <750000>; 40 vin-supply = <&avdd_0v75_s0>; 41 }; 42 43 pcie30_avdd1v8: pcie30-avdd1v8 { 44 compatible = "regulator-fixed"; 45 regulator-name = "pcie30_avdd1v8"; 46 regulator-boot-on; 47 regulator-always-on; 48 regulator-min-microvolt = <1800000>; 49 regulator-max-microvolt = <1800000>; 50 vin-supply = <&avcc_1v8_s0>; 51 }; 52 53 vbus5v0_typec: vbus5v0-typec { 54 compatible = "regulator-fixed"; 55 regulator-name = "vbus5v0_typec"; 56 regulator-min-microvolt = <5000000>; 57 regulator-max-microvolt = <5000000>; 58 enable-active-high; 59 gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; 60 vin-supply = <&vcc5v0_usb>; 61 pinctrl-names = "default"; 62 pinctrl-0 = <&typec5v_pwren>; 63 }; 64 65 vcc3v3_lcd_n: vcc3v3-lcd0-n { 66 compatible = "regulator-fixed"; 67 regulator-name = "vcc3v3_lcd0_n"; 68 regulator-boot-on; 69 enable-active-high; 70 gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; 71 vin-supply = <&vcc_1v8_s0>; 72 }; 73 74 vcc3v3_pcie30: vcc3v3-pcie30 { 75 compatible = "regulator-fixed"; 76 regulator-name = "vcc3v3_pcie30"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 enable-active-high; 80 gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; 81 startup-delay-us = <5000>; 82 vin-supply = <&vcc12v_dcin>; 83 }; 84 85 vcc5v0_host: vcc5v0-host { 86 compatible = "regulator-fixed"; 87 regulator-name = "vcc5v0_host"; 88 regulator-boot-on; 89 regulator-always-on; 90 regulator-min-microvolt = <5000000>; 91 regulator-max-microvolt = <5000000>; 92 enable-active-high; 93 gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 94 vin-supply = <&vcc5v0_usb>; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&vcc5v0_host_en>; 97 }; 98 99 vcc_mipicsi0: vcc-mipicsi0-regulator { 100 compatible = "regulator-fixed"; 101 gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; 102 pinctrl-names = "default"; 103 pinctrl-0 = <&mipicsi0_pwr>; 104 regulator-name = "vcc_mipicsi0"; 105 enable-active-high; 106 }; 107 108 vcc_mipicsi1: vcc-mipicsi1-regulator { 109 compatible = "regulator-fixed"; 110 gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&mipicsi1_pwr>; 113 regulator-name = "vcc_mipicsi1"; 114 enable-active-high; 115 }; 116 117 vcc_mipidcphy0: vcc-mipidcphy0-regulator { 118 compatible = "regulator-fixed"; 119 gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&mipidcphy0_pwr>; 122 regulator-name = "vcc_mipidcphy0"; 123 enable-active-high; 124 }; 125}; 126 127&backlight { 128 pwms = <&pwm2 0 25000 0>; 129 status = "okay"; 130}; 131 132&combphy0_ps { 133 status = "okay"; 134}; 135 136&combphy1_ps { 137 status = "okay"; 138}; 139 140&combphy2_psu { 141 status = "okay"; 142}; 143 144&dp0 { 145 status = "okay"; 146}; 147 148&dp0_in_vp2 { 149 status = "okay"; 150}; 151 152&dp1 { 153 pinctrl-names = "default"; 154 pinctrl-0 = <&dp1_hpd>; 155 hpd-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; 156 status = "okay"; 157}; 158 159&dp1_in_vp2 { 160 status = "okay"; 161}; 162 163/* 164 * mipi_dcphy0 needs to be enabled 165 * when dsi0 is enabled 166 */ 167&dsi0 { 168 status = "okay"; 169}; 170 171&dsi0_in_vp2 { 172 status = "disabled"; 173}; 174 175&dsi0_in_vp3 { 176 status = "okay"; 177}; 178 179&dsi0_panel { 180 power-supply = <&vcc3v3_lcd_n>; 181 reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&lcd_rst_gpio>; 184}; 185 186/* 187 * mipi_dcphy1 needs to be enabled 188 * when dsi1 is enabled 189 */ 190&dsi1 { 191 status = "disabled"; 192}; 193 194&dsi1_in_vp2 { 195 status = "disabled"; 196}; 197 198&dsi1_in_vp3 { 199 status = "disabled"; 200}; 201 202&dsi1_panel { 203 power-supply = <&vcc3v3_lcd_n>; 204 205 /* 206 * because in hardware, the two screens share the reset pin, 207 * so reset-gpios need only in dsi1 enable and dsi0 disabled 208 * case. 209 */ 210 211 //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; 212 //pinctrl-names = "default"; 213 //pinctrl-0 = <&lcd_rst_gpio>; 214}; 215 216&hdmi0 { 217 enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 218 status = "okay"; 219}; 220 221&hdmi0_in_vp0 { 222 status = "okay"; 223}; 224 225&hdmi0_sound { 226 status = "okay"; 227}; 228 229&hdmi1 { 230 enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 231 status = "okay"; 232}; 233 234&hdmi1_in_vp1 { 235 status = "okay"; 236}; 237 238&hdmi1_sound { 239 status = "okay"; 240}; 241 242&hdptxphy_hdmi0 { 243 status = "okay"; 244}; 245 246&hdptxphy_hdmi1 { 247 status = "okay"; 248}; 249 250&i2c2 { 251 status = "okay"; 252 253 usbc0: fusb302@22 { 254 compatible = "fcs,fusb302"; 255 reg = <0x22>; 256 interrupt-parent = <&gpio3>; 257 interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&usbc0_int>; 260 vbus-supply = <&vbus5v0_typec>; 261 status = "okay"; 262 263 ports { 264 #address-cells = <1>; 265 #size-cells = <0>; 266 267 port@0 { 268 reg = <0>; 269 usbc0_role_sw: endpoint@0 { 270 remote-endpoint = <&dwc3_0_role_switch>; 271 }; 272 }; 273 }; 274 275 usb_con: connector { 276 compatible = "usb-c-connector"; 277 label = "USB-C"; 278 data-role = "dual"; 279 power-role = "dual"; 280 try-power-role = "sink"; 281 op-sink-microwatt = <1000000>; 282 sink-pdos = 283 <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; 284 source-pdos = 285 <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 286 287 altmodes { 288 #address-cells = <1>; 289 #size-cells = <0>; 290 291 altmode@0 { 292 reg = <0>; 293 svid = <0xff01>; 294 vdo = <0xffffffff>; 295 }; 296 }; 297 298 ports { 299 #address-cells = <1>; 300 #size-cells = <0>; 301 302 port@0 { 303 reg = <0>; 304 usbc0_orien_sw: endpoint { 305 remote-endpoint = <&usbdp_phy0_orientation_switch>; 306 }; 307 }; 308 309 port@1 { 310 reg = <1>; 311 dp_altmode_mux: endpoint { 312 remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; 313 }; 314 }; 315 }; 316 }; 317 }; 318 319 hym8563: hym8563@51 { 320 compatible = "haoyu,hym8563"; 321 reg = <0x51>; 322 #clock-cells = <0>; 323 clock-frequency = <32768>; 324 clock-output-names = "hym8563"; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&hym8563_int>; 327 interrupt-parent = <&gpio0>; 328 interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; 329 wakeup-source; 330 }; 331}; 332 333&i2c6 { 334 status = "okay"; 335 gt1x: gt1x@14 { 336 compatible = "goodix,gt1x"; 337 reg = <0x14>; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&touch_gpio>; 340 goodix,rst-gpio = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; 341 goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; 342 power-supply = <&vcc3v3_lcd_n>; 343 }; 344}; 345 346&i2s5_8ch { 347 status = "okay"; 348}; 349 350&i2s6_8ch { 351 status = "okay"; 352}; 353 354&mipi_dcphy0 { 355 status = "okay"; 356}; 357 358&mipi_dcphy1 { 359 status = "disabled"; 360}; 361 362&pcie2x1l0 { 363 reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; 364 status = "okay"; 365}; 366 367&pcie30phy { 368 rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>; 369 status = "okay"; 370}; 371 372&pcie3x4 { 373 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 374 vpcie3v3-supply = <&vcc3v3_pcie30>; 375 status = "okay"; 376}; 377 378&pinctrl { 379 cam { 380 mipicsi0_pwr: mipicsi0-pwr { 381 rockchip,pins = 382 /* camera power en */ 383 <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 384 }; 385 mipicsi1_pwr: mipicsi1-pwr { 386 rockchip,pins = 387 /* camera power en */ 388 <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 389 }; 390 mipidcphy0_pwr: mipidcphy0-pwr { 391 rockchip,pins = 392 /* camera power en */ 393 <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 394 }; 395 }; 396 397 dp { 398 dp1_hpd: dp1-hpd { 399 rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 400 }; 401 }; 402 403 hym8563 { 404 hym8563_int: hym8563-int { 405 rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 406 }; 407 }; 408 409 lcd { 410 lcd_rst_gpio: lcd-rst-gpio { 411 rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 412 }; 413 }; 414 415 touch { 416 touch_gpio: touch-gpio { 417 rockchip,pins = 418 <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, 419 <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; 420 }; 421 }; 422 423 usb { 424 vcc5v0_host_en: vcc5v0-host-en { 425 rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 426 }; 427 }; 428 429 usb-typec { 430 usbc0_int: usbc0-int { 431 rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; 432 }; 433 434 typec5v_pwren: typec5v-pwren { 435 rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 436 }; 437 }; 438}; 439 440&pwm2 { 441 status = "okay"; 442}; 443 444&route_dsi0 { 445 status = "okay"; 446 connect = <&vp3_out_dsi0>; 447}; 448 449&route_dsi1 { 450 status = "disabled"; 451 connect = <&vp3_out_dsi1>; 452}; 453 454&sata0 { 455 status = "okay"; 456}; 457 458&u2phy0_otg { 459 rockchip,typec-vbus-det; 460}; 461 462&u2phy1_otg { 463 phy-supply = <&vcc5v0_host>; 464}; 465 466&u2phy2_host { 467 phy-supply = <&vcc5v0_host>; 468}; 469 470&u2phy3_host { 471 phy-supply = <&vcc5v0_host>; 472}; 473 474&usbdp_phy0 { 475 orientation-switch; 476 svid = <0xff01>; 477 sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 478 sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 479 480 port { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 usbdp_phy0_orientation_switch: endpoint@0 { 484 reg = <0>; 485 remote-endpoint = <&usbc0_orien_sw>; 486 }; 487 488 usbdp_phy0_dp_altmode_mux: endpoint@1 { 489 reg = <1>; 490 remote-endpoint = <&dp_altmode_mux>; 491 }; 492 }; 493}; 494 495&usbdp_phy1 { 496 rockchip,dp-lane-mux = <2 3>; 497}; 498 499&usbdrd_dwc3_0 { 500 dr_mode = "otg"; 501 usb-role-switch; 502 port { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 dwc3_0_role_switch: endpoint@0 { 506 reg = <0>; 507 remote-endpoint = <&usbc0_role_sw>; 508 }; 509 }; 510}; 511 512&usbhost3_0 { 513 status = "disabled"; 514}; 515 516&usbhost_dwc3_0 { 517 status = "disabled"; 518}; 519