xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h"
8*4882a593Smuzhiyun#include "rk3588.dtsi"
9*4882a593Smuzhiyun#include "rk3588-evb.dtsi"
10*4882a593Smuzhiyun#include "rk3588-rk806-dual.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	es7202_sound_micarray: es7202-sound-micarray {
14*4882a593Smuzhiyun		status = "okay";
15*4882a593Smuzhiyun		compatible = "simple-audio-card";
16*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
17*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,sound-micarray";
18*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
19*4882a593Smuzhiyun		simple-audio-card,dai-link@0 {
20*4882a593Smuzhiyun			format = "pdm";
21*4882a593Smuzhiyun			cpu {
22*4882a593Smuzhiyun				sound-dai = <&pdm0>;
23*4882a593Smuzhiyun			};
24*4882a593Smuzhiyun			codec {
25*4882a593Smuzhiyun				sound-dai = <&es7202>;
26*4882a593Smuzhiyun			};
27*4882a593Smuzhiyun		};
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	es8388_sound: es8388-sound {
31*4882a593Smuzhiyun		status = "okay";
32*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
33*4882a593Smuzhiyun		rockchip,card-name = "rockchip-es8388";
34*4882a593Smuzhiyun		hp-det-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>;
35*4882a593Smuzhiyun		io-channels = <&saradc 3>;
36*4882a593Smuzhiyun		io-channel-names = "adc-detect";
37*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
38*4882a593Smuzhiyun		poll-interval = <100>;
39*4882a593Smuzhiyun		spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
40*4882a593Smuzhiyun		hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
41*4882a593Smuzhiyun		rockchip,format = "i2s";
42*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
43*4882a593Smuzhiyun		rockchip,cpu = <&i2s0_8ch>;
44*4882a593Smuzhiyun		rockchip,codec = <&es8388>;
45*4882a593Smuzhiyun		rockchip,audio-routing =
46*4882a593Smuzhiyun			"Headphone", "LOUT1",
47*4882a593Smuzhiyun			"Headphone", "ROUT1",
48*4882a593Smuzhiyun			"Speaker", "LOUT2",
49*4882a593Smuzhiyun			"Speaker", "ROUT2",
50*4882a593Smuzhiyun			"Headphone", "Headphone Power",
51*4882a593Smuzhiyun			"Headphone", "Headphone Power",
52*4882a593Smuzhiyun			"Speaker", "Speaker Power",
53*4882a593Smuzhiyun			"Speaker", "Speaker Power",
54*4882a593Smuzhiyun			"LINPUT1", "Main Mic",
55*4882a593Smuzhiyun			"LINPUT2", "Main Mic",
56*4882a593Smuzhiyun			"RINPUT1", "Headset Mic",
57*4882a593Smuzhiyun			"RINPUT2", "Headset Mic";
58*4882a593Smuzhiyun		pinctrl-names = "default";
59*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
60*4882a593Smuzhiyun		play-pause-key {
61*4882a593Smuzhiyun			label = "playpause";
62*4882a593Smuzhiyun			linux,code = <KEY_PLAYPAUSE>;
63*4882a593Smuzhiyun			press-threshold-microvolt = <2000>;
64*4882a593Smuzhiyun		};
65*4882a593Smuzhiyun	};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun	fan: pwm-fan {
68*4882a593Smuzhiyun		compatible = "pwm-fan";
69*4882a593Smuzhiyun		#cooling-cells = <2>;
70*4882a593Smuzhiyun		pwms = <&pwm6 0 50000 0>;
71*4882a593Smuzhiyun		cooling-levels = <0 50 100 150 200 255>;
72*4882a593Smuzhiyun		rockchip,temp-trips = <
73*4882a593Smuzhiyun			50000	1
74*4882a593Smuzhiyun			55000	2
75*4882a593Smuzhiyun			60000	3
76*4882a593Smuzhiyun			65000	4
77*4882a593Smuzhiyun			70000	5
78*4882a593Smuzhiyun		>;
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun	hall_sensor: hall-mh248 {
82*4882a593Smuzhiyun		compatible = "hall-mh248";
83*4882a593Smuzhiyun		pinctrl-names = "default";
84*4882a593Smuzhiyun		pinctrl-0 = <&mh248_irq_gpio>;
85*4882a593Smuzhiyun		irq-gpio = <&gpio0 RK_PD2 IRQ_TYPE_EDGE_BOTH>;
86*4882a593Smuzhiyun		hall-active = <1>;
87*4882a593Smuzhiyun		status = "okay";
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun	pcie20_avdd0v85: pcie20-avdd0v85 {
91*4882a593Smuzhiyun		compatible = "regulator-fixed";
92*4882a593Smuzhiyun		regulator-name = "pcie20_avdd0v85";
93*4882a593Smuzhiyun		regulator-boot-on;
94*4882a593Smuzhiyun		regulator-always-on;
95*4882a593Smuzhiyun		regulator-min-microvolt = <850000>;
96*4882a593Smuzhiyun		regulator-max-microvolt = <850000>;
97*4882a593Smuzhiyun		vin-supply = <&avdd_0v85_s0>;
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	pcie20_avdd1v8: pcie20-avdd1v8 {
101*4882a593Smuzhiyun		compatible = "regulator-fixed";
102*4882a593Smuzhiyun		regulator-name = "pcie20_avdd1v8";
103*4882a593Smuzhiyun		regulator-boot-on;
104*4882a593Smuzhiyun		regulator-always-on;
105*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
106*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
107*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
108*4882a593Smuzhiyun	};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun	pcie30_avdd0v75: pcie30-avdd0v75 {
111*4882a593Smuzhiyun		compatible = "regulator-fixed";
112*4882a593Smuzhiyun		regulator-name = "pcie30_avdd0v75";
113*4882a593Smuzhiyun		regulator-boot-on;
114*4882a593Smuzhiyun		regulator-always-on;
115*4882a593Smuzhiyun		regulator-min-microvolt = <750000>;
116*4882a593Smuzhiyun		regulator-max-microvolt = <750000>;
117*4882a593Smuzhiyun		vin-supply = <&avdd_0v75_s0>;
118*4882a593Smuzhiyun	};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun	pcie30_avdd1v8: pcie30-avdd1v8 {
121*4882a593Smuzhiyun		compatible = "regulator-fixed";
122*4882a593Smuzhiyun		regulator-name = "pcie30_avdd1v8";
123*4882a593Smuzhiyun		regulator-boot-on;
124*4882a593Smuzhiyun		regulator-always-on;
125*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
126*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
127*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
128*4882a593Smuzhiyun	};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun	vbus5v0_typec: vbus5v0-typec {
131*4882a593Smuzhiyun		compatible = "regulator-fixed";
132*4882a593Smuzhiyun		regulator-name = "vbus5v0_typec";
133*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
134*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
135*4882a593Smuzhiyun		enable-active-high;
136*4882a593Smuzhiyun		gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
137*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
138*4882a593Smuzhiyun		pinctrl-names = "default";
139*4882a593Smuzhiyun		pinctrl-0 = <&typec5v_pwren>;
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	vcc3v3_lcd_n: vcc3v3-lcd0-n {
143*4882a593Smuzhiyun		compatible = "regulator-fixed";
144*4882a593Smuzhiyun		regulator-name = "vcc3v3_lcd0_n";
145*4882a593Smuzhiyun		regulator-boot-on;
146*4882a593Smuzhiyun		enable-active-high;
147*4882a593Smuzhiyun		gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
148*4882a593Smuzhiyun		vin-supply = <&vcc_1v8_s0>;
149*4882a593Smuzhiyun	};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun	vcc3v3_pcie30: vcc3v3-pcie30 {
152*4882a593Smuzhiyun		compatible = "regulator-fixed";
153*4882a593Smuzhiyun		regulator-name = "vcc3v3_pcie30";
154*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
155*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
156*4882a593Smuzhiyun		enable-active-high;
157*4882a593Smuzhiyun		gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
158*4882a593Smuzhiyun		startup-delay-us = <5000>;
159*4882a593Smuzhiyun		vin-supply = <&vcc12v_dcin>;
160*4882a593Smuzhiyun	};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host {
163*4882a593Smuzhiyun		compatible = "regulator-fixed";
164*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
165*4882a593Smuzhiyun		regulator-boot-on;
166*4882a593Smuzhiyun		regulator-always-on;
167*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
168*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
169*4882a593Smuzhiyun		enable-active-high;
170*4882a593Smuzhiyun		gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
171*4882a593Smuzhiyun		vin-supply = <&vcc5v0_usb>;
172*4882a593Smuzhiyun		pinctrl-names = "default";
173*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en>;
174*4882a593Smuzhiyun	};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun	wireless_bluetooth: wireless-bluetooth {
177*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
178*4882a593Smuzhiyun		clocks = <&hym8563>;
179*4882a593Smuzhiyun		clock-names = "ext_clock";
180*4882a593Smuzhiyun		uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
181*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
182*4882a593Smuzhiyun		pinctrl-0 = <&uart8m1_rtsn>;
183*4882a593Smuzhiyun		pinctrl-1 = <&uart8_gpios>;
184*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
185*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
186*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
187*4882a593Smuzhiyun		status = "okay";
188*4882a593Smuzhiyun	};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun	wireless_wlan: wireless-wlan {
191*4882a593Smuzhiyun		compatible = "wlan-platdata";
192*4882a593Smuzhiyun		wifi_chip_type = "ap6275p";
193*4882a593Smuzhiyun		pinctrl-names = "default";
194*4882a593Smuzhiyun		pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>;
195*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
196*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
197*4882a593Smuzhiyun		status = "okay";
198*4882a593Smuzhiyun	};
199*4882a593Smuzhiyun};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun&combphy0_ps {
202*4882a593Smuzhiyun	status = "okay";
203*4882a593Smuzhiyun};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun&combphy1_ps {
206*4882a593Smuzhiyun	status = "okay";
207*4882a593Smuzhiyun};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun&combphy2_psu {
210*4882a593Smuzhiyun	status = "okay";
211*4882a593Smuzhiyun};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun&backlight {
214*4882a593Smuzhiyun	pwms = <&pwm15 0 25000 0>;
215*4882a593Smuzhiyun	status = "okay";
216*4882a593Smuzhiyun};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun&dp0 {
219*4882a593Smuzhiyun	status = "okay";
220*4882a593Smuzhiyun};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun&dp0_in_vp2 {
223*4882a593Smuzhiyun	status = "okay";
224*4882a593Smuzhiyun};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun&dp1_sound {
227*4882a593Smuzhiyun	status = "okay";
228*4882a593Smuzhiyun};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun&dp1 {
231*4882a593Smuzhiyun	pinctrl-0 = <&dp1m2_pins>;
232*4882a593Smuzhiyun	pinctrl-names = "default";
233*4882a593Smuzhiyun	status = "okay";
234*4882a593Smuzhiyun};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun&dp1_in_vp2 {
237*4882a593Smuzhiyun	status = "okay";
238*4882a593Smuzhiyun};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun/*
241*4882a593Smuzhiyun * mipi_dcphy0 needs to be enabled
242*4882a593Smuzhiyun * when dsi0 is enabled
243*4882a593Smuzhiyun */
244*4882a593Smuzhiyun&dsi0 {
245*4882a593Smuzhiyun	status = "okay";
246*4882a593Smuzhiyun};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun&dsi0_in_vp2 {
249*4882a593Smuzhiyun	status = "disabled";
250*4882a593Smuzhiyun};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun&dsi0_in_vp3 {
253*4882a593Smuzhiyun	status = "okay";
254*4882a593Smuzhiyun};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun&dsi0_panel {
257*4882a593Smuzhiyun	power-supply = <&vcc3v3_lcd_n>;
258*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
259*4882a593Smuzhiyun	pinctrl-names = "default";
260*4882a593Smuzhiyun	pinctrl-0 = <&lcd_rst_gpio>;
261*4882a593Smuzhiyun};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun/*
264*4882a593Smuzhiyun * mipi_dcphy1 needs to be enabled
265*4882a593Smuzhiyun * when dsi1 is enabled
266*4882a593Smuzhiyun */
267*4882a593Smuzhiyun&dsi1 {
268*4882a593Smuzhiyun	status = "disabled";
269*4882a593Smuzhiyun};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun&dsi1_in_vp2 {
272*4882a593Smuzhiyun	status = "disabled";
273*4882a593Smuzhiyun};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun&dsi1_in_vp3 {
276*4882a593Smuzhiyun	status = "disabled";
277*4882a593Smuzhiyun};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun&dsi1_panel {
280*4882a593Smuzhiyun	power-supply = <&vcc3v3_lcd_n>;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun	/*
283*4882a593Smuzhiyun	 * because in hardware, the two screens share the reset pin,
284*4882a593Smuzhiyun	 * so reset-gpios need only in dsi1 enable and dsi0 disabled
285*4882a593Smuzhiyun	 * case.
286*4882a593Smuzhiyun	 */
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun	//reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
289*4882a593Smuzhiyun	//pinctrl-names = "default";
290*4882a593Smuzhiyun	//pinctrl-0 = <&lcd_rst_gpio>;
291*4882a593Smuzhiyun	phy-c-option;
292*4882a593Smuzhiyun	dsi,lanes  = <3>;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun	panel-init-sequence = [
295*4882a593Smuzhiyun		23 00 02 FF 20
296*4882a593Smuzhiyun		23 00 02 FB 01
297*4882a593Smuzhiyun		23 00 02 05 D9
298*4882a593Smuzhiyun		/* VGH=17V */
299*4882a593Smuzhiyun		23 00 02 07 78
300*4882a593Smuzhiyun		/* VGL=-14V */
301*4882a593Smuzhiyun		23 00 02 08 5A
302*4882a593Smuzhiyun		/* EN_VMODGATE2=1 */
303*4882a593Smuzhiyun		23 00 02 0D 63
304*4882a593Smuzhiyun		/* VGH=16V */
305*4882a593Smuzhiyun		23 00 02 0E 91
306*4882a593Smuzhiyun		/* VGL=-13V */
307*4882a593Smuzhiyun		23 00 02 0F 73
308*4882a593Smuzhiyun		/* GVDD=5.2V */
309*4882a593Smuzhiyun		23 00 02 95 EB
310*4882a593Smuzhiyun		23 00 02 96 EB
311*4882a593Smuzhiyun		/* Disable VDDI LV */
312*4882a593Smuzhiyun		23 00 02 30 11
313*4882a593Smuzhiyun		/* ISOP */
314*4882a593Smuzhiyun		23 00 02 6D 66
315*4882a593Smuzhiyun		/* EN_GMACP */
316*4882a593Smuzhiyun		23 00 02 75 A2
317*4882a593Smuzhiyun		/* V128 */
318*4882a593Smuzhiyun		23 00 02 77 3B
319*4882a593Smuzhiyun		/* R(+) */
320*4882a593Smuzhiyun		29 00 11 B0  00  08  00  23  00  4D  00  6D  00  89  00  A1  00  B6  00  C9
321*4882a593Smuzhiyun		29 00 11 B1  00  DA  01  13  01  3C  01  7E  01  AB  01  F7  02  2F  02  31
322*4882a593Smuzhiyun		29 00 11 B2  02  67  02  A6  02  D1  03  08  03  2E  03  5B  03  6B  03  7B
323*4882a593Smuzhiyun		29 00 0D B3  03  8E  03  A2  03  B7  03  E7  03  FD  03  FF
324*4882a593Smuzhiyun		/* G(+) */
325*4882a593Smuzhiyun		29 00 11 B4  00  08  00  23  00  4D  00  6D  00  89  00  A1  00  B6  00  C9
326*4882a593Smuzhiyun		29 00 11 B5  00  DA  01  13  01  3C  01  7E  01  AB  01  F7  02  2F  02  31
327*4882a593Smuzhiyun		29 00 11 B6  02  67  02  A6  02  D1  03  08  03  2E  03  5B  03  6B  03  7B
328*4882a593Smuzhiyun		29 00 0D B7  03  8E  03  A2  03  B7  03  E7  03  FD  03  FF
329*4882a593Smuzhiyun		/* B(+) */
330*4882a593Smuzhiyun		29 00 11 B8  00  08  00  23  00  4D  00  6D  00  89  00  A1  00  B6  00  C9
331*4882a593Smuzhiyun		29 00 11 B9  00  DA  01  13  01  3C  01  7E  01  AB  01  F7  02  2F  02  31
332*4882a593Smuzhiyun		29 00 11 BA  02  67  02  A6  02  D1  03  08  03  2E  03  5B  03  6B  03  7B
333*4882a593Smuzhiyun		29 00 0D BB  03  8E  03  A2  03  B7  03  E7  03  FD  03  FF
334*4882a593Smuzhiyun		/* CMD2_Page1 */
335*4882a593Smuzhiyun		23 00 02 FF 21
336*4882a593Smuzhiyun		23 00 02 FB 01
337*4882a593Smuzhiyun		/* R(-) */
338*4882a593Smuzhiyun		29 00 11 B0  00  00  00  1B  00  45  00  65  00  81  00  99  00  AE  00  C1
339*4882a593Smuzhiyun		29 00 11 B1  00  D2  01  0B  01  34  01  76  01  A3  01  EF  02  27  02  29
340*4882a593Smuzhiyun		29 00 11 B2  02  5F  02  9E  02  C9  03  00  03  26  03  53  03  63  03  73
341*4882a593Smuzhiyun		29 00 0D B3  03  86  03  9A  03  AF  03  DF  03  F5  03  F7
342*4882a593Smuzhiyun		/* G(-) */
343*4882a593Smuzhiyun		29 00 11 B4  00  00  00  1B  00  45  00  65  00  81  00  99  00  AE  00  C1
344*4882a593Smuzhiyun		29 00 11 B5  00  D2  01  0B  01  34  01  76  01  A3  01  EF  02  27  02  29
345*4882a593Smuzhiyun		29 00 11 B6  02  5F  02  9E  02  C9  03  00  03  26  03  53  03  63  03  73
346*4882a593Smuzhiyun		29 00 0D B7  03  86  03  9A  03  AF  03  DF  03  F5  03  F7
347*4882a593Smuzhiyun		/* B(-) */
348*4882a593Smuzhiyun		29 00 11 B8  00  00  00  1B  00  45  00  65  00  81  00  99  00  AE  00  C1
349*4882a593Smuzhiyun		29 00 11 B9  00  D2  01  0B  01  34  01  76  01  A3  01  EF  02  27  02  29
350*4882a593Smuzhiyun		29 00 11 BA  02  5F  02  9E  02  C9  03  00  03  26  03  53  03  63  03  73
351*4882a593Smuzhiyun		29 00 0D BB  03  86  03  9A  03  AF  03  DF  03  F5  03  F7
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun		29 00 02  FF 24
354*4882a593Smuzhiyun		29 00 02  FB 01
355*4882a593Smuzhiyun		/* VGL */
356*4882a593Smuzhiyun		29 00 02 00 00
357*4882a593Smuzhiyun		29 00 02 01 00
358*4882a593Smuzhiyun		/* VDDO */
359*4882a593Smuzhiyun		29 00 02 02 1C
360*4882a593Smuzhiyun		29 00 02 03 1C
361*4882a593Smuzhiyun		/* VDDE */
362*4882a593Smuzhiyun		29 00 02 04 1D
363*4882a593Smuzhiyun		29 00 02 05 1D
364*4882a593Smuzhiyun		/* STV0 */
365*4882a593Smuzhiyun		29 00 02 06 04
366*4882a593Smuzhiyun		29 00 02 07 04
367*4882a593Smuzhiyun		/* CLK8 */
368*4882a593Smuzhiyun		29 00 02 08 0F
369*4882a593Smuzhiyun		29 00 02 09 0F
370*4882a593Smuzhiyun		/* CLK6 */
371*4882a593Smuzhiyun		29 00 02 0A 0E
372*4882a593Smuzhiyun		29 00 02 0B 0E
373*4882a593Smuzhiyun		/* CLK4 */
374*4882a593Smuzhiyun		29 00 02 0C 0D
375*4882a593Smuzhiyun		29 00 02 0D 0D
376*4882a593Smuzhiyun		/* CLK2 */
377*4882a593Smuzhiyun		29 00 02 0E 0C
378*4882a593Smuzhiyun		29 00 02 0F 0C
379*4882a593Smuzhiyun		/* STV2 */
380*4882a593Smuzhiyun		29 00 02 10 08
381*4882a593Smuzhiyun		29 00 02 11 08
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun		29 00 02 12 00
384*4882a593Smuzhiyun		29 00 02 13 00
385*4882a593Smuzhiyun		29 00 02 14 00
386*4882a593Smuzhiyun		29 00 02 15 00
387*4882a593Smuzhiyun		/* VGL */
388*4882a593Smuzhiyun		29 00 02 16 00
389*4882a593Smuzhiyun		29 00 02 17 00
390*4882a593Smuzhiyun		/* VDDO */
391*4882a593Smuzhiyun		29 00 02 18 1C
392*4882a593Smuzhiyun		29 00 02 19 1C
393*4882a593Smuzhiyun		/* VDDE */
394*4882a593Smuzhiyun		29 00 02 1A 1D
395*4882a593Smuzhiyun		29 00 02 1B 1D
396*4882a593Smuzhiyun		/* STV0 */
397*4882a593Smuzhiyun		29 00 02 1C 04
398*4882a593Smuzhiyun		29 00 02 1D 04
399*4882a593Smuzhiyun		/* CLK7 */
400*4882a593Smuzhiyun		29 00 02 1E 0F
401*4882a593Smuzhiyun		29 00 02 1F 0F
402*4882a593Smuzhiyun		/* CLK5 */
403*4882a593Smuzhiyun		29 00 02 20 0E
404*4882a593Smuzhiyun		29 00 02 21 0E
405*4882a593Smuzhiyun		/* CLK3 */
406*4882a593Smuzhiyun		29 00 02 22 0D
407*4882a593Smuzhiyun		29 00 02 23 0D
408*4882a593Smuzhiyun		/* CLK1 */
409*4882a593Smuzhiyun		29 00 02 24 0C
410*4882a593Smuzhiyun		29 00 02 25 0C
411*4882a593Smuzhiyun		/* STV1 */
412*4882a593Smuzhiyun		29 00 02 26 08
413*4882a593Smuzhiyun		29 00 02 27 08
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun		29 00 02 28 00
416*4882a593Smuzhiyun		29 00 02 29 00
417*4882a593Smuzhiyun		29 00 02 2A 00
418*4882a593Smuzhiyun		29 00 02 2B 00
419*4882a593Smuzhiyun		/* STV0 */
420*4882a593Smuzhiyun		29 00 02 2D 20
421*4882a593Smuzhiyun		29 00 02 2F 0A
422*4882a593Smuzhiyun		29 00 02 30 44
423*4882a593Smuzhiyun		29 00 02 33 0C
424*4882a593Smuzhiyun		29 00 02 34 32
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun		29 00 02 37 44
427*4882a593Smuzhiyun		29 00 02 38 40
428*4882a593Smuzhiyun		29 00 02 39 00
429*4882a593Smuzhiyun		29 00 02 3A 50
430*4882a593Smuzhiyun		29 00 02 3B 50
431*4882a593Smuzhiyun		29 00 02 3D 42
432*4882a593Smuzhiyun		/* STV */
433*4882a593Smuzhiyun		29 00 02 3F 06
434*4882a593Smuzhiyun		29 00 02 43 06
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun		29 00 02 47 66
437*4882a593Smuzhiyun		29 00 02 4A 50
438*4882a593Smuzhiyun		29 00 02 4B 50
439*4882a593Smuzhiyun		29 00 02 4C 91
440*4882a593Smuzhiyun		/* GCK */
441*4882a593Smuzhiyun		29 00 02 4D 21
442*4882a593Smuzhiyun		29 00 02 4E 43
443*4882a593Smuzhiyun		29 00 02 51 12
444*4882a593Smuzhiyun		29 00 02 52 34
445*4882a593Smuzhiyun		29 00 03 55 82 02
446*4882a593Smuzhiyun		29 00 02 56 04
447*4882a593Smuzhiyun		29 00 02 58 21
448*4882a593Smuzhiyun		29 00 02 59 30
449*4882a593Smuzhiyun		29 00 02 5A 50
450*4882a593Smuzhiyun		29 00 02 5B 50
451*4882a593Smuzhiyun		29 00 03 5E 00 06
452*4882a593Smuzhiyun		29 00 02 5F 00
453*4882a593Smuzhiyun		/* EN_LFD_SOURCE=0 */
454*4882a593Smuzhiyun		29 00 02 65 82
455*4882a593Smuzhiyun		/* VDDO, VDDE */
456*4882a593Smuzhiyun		29 00 02 7E 20
457*4882a593Smuzhiyun		29 00 02 7F 3C
458*4882a593Smuzhiyun		29 00 02 82 04
459*4882a593Smuzhiyun		29 00 02 97 C0
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun		29 00 0D B6 05 00 05 00 00 00 00 00 05 05 00 00
462*4882a593Smuzhiyun		/* qclk=96/5 Mhz */
463*4882a593Smuzhiyun		29 00 02 91 44
464*4882a593Smuzhiyun		29 00 02 92 55
465*4882a593Smuzhiyun		29 00 02 93 1A
466*4882a593Smuzhiyun		29 00 02 94 5F
467*4882a593Smuzhiyun		/* SOG_HBP */
468*4882a593Smuzhiyun		29 00 02 D7 55
469*4882a593Smuzhiyun		29 00 02 DA 0A
470*4882a593Smuzhiyun		29 00 02 DE 08
471*4882a593Smuzhiyun		/* Normal */
472*4882a593Smuzhiyun		29 00 02 DB 05
473*4882a593Smuzhiyun		29 00 02 DC 55
474*4882a593Smuzhiyun		29 00 02 DD 22
475*4882a593Smuzhiyun		/* Line N */
476*4882a593Smuzhiyun		29 00 02 DF 05
477*4882a593Smuzhiyun		29 00 02 E0 55
478*4882a593Smuzhiyun		/* Line N+1 */
479*4882a593Smuzhiyun		29 00 02 E1 05
480*4882a593Smuzhiyun		29 00 02 E2 55
481*4882a593Smuzhiyun		/* TP0 */
482*4882a593Smuzhiyun		29 00 02 E3 05
483*4882a593Smuzhiyun		29 00 02 E4 55
484*4882a593Smuzhiyun		/* TP3 */
485*4882a593Smuzhiyun		29 00 02 E5 05
486*4882a593Smuzhiyun		29 00 02 E6 55
487*4882a593Smuzhiyun		/* Gate EQ */
488*4882a593Smuzhiyun		29 00 02 5C 00
489*4882a593Smuzhiyun		29 00 02 5D 00
490*4882a593Smuzhiyun		/* TP3 */
491*4882a593Smuzhiyun		29 00 02 8D 00
492*4882a593Smuzhiyun		29 00 02 8E 00
493*4882a593Smuzhiyun		/* No Sync @ TP */
494*4882a593Smuzhiyun		29 00 02 B5 90
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun		29 00 02 FF 25
497*4882a593Smuzhiyun		29 00 02 FB 01
498*4882a593Smuzhiyun		/* disable auto_vbp_vfp */
499*4882a593Smuzhiyun		29 00 02 05 00
500*4882a593Smuzhiyun		/* ESD_DET_ERR_SEL */
501*4882a593Smuzhiyun		29 00 02 19 07
502*4882a593Smuzhiyun		/* DP_N_GCK */
503*4882a593Smuzhiyun		29 00 02 1F 50
504*4882a593Smuzhiyun		29 00 02 20 50
505*4882a593Smuzhiyun		/* DP_N_1_GCK */
506*4882a593Smuzhiyun		29 00 02 26 50
507*4882a593Smuzhiyun		29 00 02 27 50
508*4882a593Smuzhiyun		/* TP0_GCK */
509*4882a593Smuzhiyun		29 00 02 33 50
510*4882a593Smuzhiyun		29 00 02 34 50
511*4882a593Smuzhiyun		/* TP3 GCK/MUX=1 */
512*4882a593Smuzhiyun		29 00 02 3F E0
513*4882a593Smuzhiyun		/* TP3_GCK_START_LINE */
514*4882a593Smuzhiyun		29 00 02 40 00
515*4882a593Smuzhiyun		/* TP3_STV */
516*4882a593Smuzhiyun		29 00 02 44 00
517*4882a593Smuzhiyun		29 00 02 45 40
518*4882a593Smuzhiyun		/* TP3_GCK */
519*4882a593Smuzhiyun		29 00 02 48 50
520*4882a593Smuzhiyun		29 00 02 49 50
521*4882a593Smuzhiyun		/* LSTP0 */
522*4882a593Smuzhiyun		29 00 02 5B 00
523*4882a593Smuzhiyun		29 00 02 5C 00
524*4882a593Smuzhiyun		29 00 02 5D 00
525*4882a593Smuzhiyun		29 00 02 5E D0
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun		29 00 02 61 50
528*4882a593Smuzhiyun		29 00 02 62 50
529*4882a593Smuzhiyun		/* en_vfp_addvsync */
530*4882a593Smuzhiyun		29 00 02 F1 10
531*4882a593Smuzhiyun		/* CMD2,Page10 */
532*4882a593Smuzhiyun		29 00 02 FF 2A
533*4882a593Smuzhiyun		29 00 02 FB 01
534*4882a593Smuzhiyun		/* PWRONOFF */
535*4882a593Smuzhiyun		/* STV */
536*4882a593Smuzhiyun		29 00 02 64 16
537*4882a593Smuzhiyun		/* CLR */
538*4882a593Smuzhiyun		29 00 02 67 16
539*4882a593Smuzhiyun		/* GCK */
540*4882a593Smuzhiyun		29 00 02 6A 16
541*4882a593Smuzhiyun		/* POL */
542*4882a593Smuzhiyun		29 00 02 70 30
543*4882a593Smuzhiyun		/* ABOFF */
544*4882a593Smuzhiyun		29 00 02 A2 F3
545*4882a593Smuzhiyun		29 00 02 A3 FF
546*4882a593Smuzhiyun		29 00 02 A4 FF
547*4882a593Smuzhiyun		29 00 02 A5 FF
548*4882a593Smuzhiyun		/* Long_V_TIMING disable */
549*4882a593Smuzhiyun		29 00 02 D6 08
550*4882a593Smuzhiyun		/* CMD2,Page6 */
551*4882a593Smuzhiyun		29 00 02 FF 26
552*4882a593Smuzhiyun		29 00 02 FB 01
553*4882a593Smuzhiyun		/* TPEN */
554*4882a593Smuzhiyun		29 00 02 00 81
555*4882a593Smuzhiyun		/* 90Hz */
556*4882a593Smuzhiyun		29 00 02 01 30
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun		29 00 02 02 31
559*4882a593Smuzhiyun		29 00 02 0A F2
560*4882a593Smuzhiyun		//Table A (90Hz)
561*4882a593Smuzhiyun		29 00 02 04 28
562*4882a593Smuzhiyun		29 00 02 06 3C
563*4882a593Smuzhiyun		29 00 02 0C 0B
564*4882a593Smuzhiyun		29 00 02 0D 0C
565*4882a593Smuzhiyun		29 00 02 0F 00
566*4882a593Smuzhiyun		29 00 02 11 00
567*4882a593Smuzhiyun		29 00 02 12 50
568*4882a593Smuzhiyun		29 00 02 13 AE
569*4882a593Smuzhiyun		29 00 02 14 A6
570*4882a593Smuzhiyun		29 00 02 16 10
571*4882a593Smuzhiyun		29 00 02 19 08
572*4882a593Smuzhiyun		29 00 02 1A FF
573*4882a593Smuzhiyun		29 00 02 1B 08
574*4882a593Smuzhiyun		29 00 02 1C 80
575*4882a593Smuzhiyun		29 00 02 22 00
576*4882a593Smuzhiyun		29 00 02 23 00
577*4882a593Smuzhiyun		29 00 02 2A 08
578*4882a593Smuzhiyun		29 00 02 2B FF
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun		29 00 02 1D 00
581*4882a593Smuzhiyun		29 00 02 1E 55
582*4882a593Smuzhiyun		29 00 02 1F 55
583*4882a593Smuzhiyun		29 00 02 24 00
584*4882a593Smuzhiyun		29 00 02 25 55
585*4882a593Smuzhiyun		29 00 02 2F 05
586*4882a593Smuzhiyun		29 00 02 30 55
587*4882a593Smuzhiyun		29 00 02 31 05
588*4882a593Smuzhiyun		29 00 02 32 6D
589*4882a593Smuzhiyun		29 00 02 39 00
590*4882a593Smuzhiyun		29 00 02 3A 55
591*4882a593Smuzhiyun		/* Table B (60Hz,81*1+101*19=2000, Extra=20) */
592*4882a593Smuzhiyun		29 00 02 8B 28
593*4882a593Smuzhiyun		29 00 02 8C 13
594*4882a593Smuzhiyun		29 00 02 8D 0A
595*4882a593Smuzhiyun		29 00 02 8F 0A
596*4882a593Smuzhiyun		29 00 02 91 00
597*4882a593Smuzhiyun		29 00 02 92 50
598*4882a593Smuzhiyun		29 00 02 93 51
599*4882a593Smuzhiyun		29 00 02 94 65
600*4882a593Smuzhiyun		29 00 02 96 10
601*4882a593Smuzhiyun		29 00 02 99 0A
602*4882a593Smuzhiyun		29 00 02 9A 7F
603*4882a593Smuzhiyun		29 00 02 9B 0A
604*4882a593Smuzhiyun		29 00 02 9C 0C
605*4882a593Smuzhiyun		29 00 02 9D 0A
606*4882a593Smuzhiyun		29 00 02 9E 7F
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun		29 00 02 3F 00
609*4882a593Smuzhiyun		29 00 02 40 75
610*4882a593Smuzhiyun		29 00 02 41 75
611*4882a593Smuzhiyun		29 00 02 42 75
612*4882a593Smuzhiyun		29 00 02 43 00
613*4882a593Smuzhiyun		29 00 02 44 75
614*4882a593Smuzhiyun		29 00 02 45 05
615*4882a593Smuzhiyun		29 00 02 46 75
616*4882a593Smuzhiyun		29 00 02 47 05
617*4882a593Smuzhiyun		29 00 02 48 8D
618*4882a593Smuzhiyun		29 00 02 49 00
619*4882a593Smuzhiyun		29 00 02 4A 75
620*4882a593Smuzhiyun		/* STV0 */
621*4882a593Smuzhiyun		29 00 02 4D 5D
622*4882a593Smuzhiyun		29 00 02 4E 60
623*4882a593Smuzhiyun		/* STV */
624*4882a593Smuzhiyun		29 00 02 4F 5D
625*4882a593Smuzhiyun		29 00 02 50 60
626*4882a593Smuzhiyun		/* GCK */
627*4882a593Smuzhiyun		29 00 02 51 70
628*4882a593Smuzhiyun		29 00 02 52 60
629*4882a593Smuzhiyun		/* DP_N_GCK */
630*4882a593Smuzhiyun		29 00 02 56 70
631*4882a593Smuzhiyun		29 00 02 58 60
632*4882a593Smuzhiyun		/* DP_N_1_GCK */
633*4882a593Smuzhiyun		29 00 02 5B 70
634*4882a593Smuzhiyun		29 00 02 5C 60
635*4882a593Smuzhiyun		/* TP0_GCK */
636*4882a593Smuzhiyun		29 00 02 60 70
637*4882a593Smuzhiyun		29 00 02 61 60
638*4882a593Smuzhiyun		/* TP3_GCK */
639*4882a593Smuzhiyun		29 00 02 64 70
640*4882a593Smuzhiyun		29 00 02 65 60
641*4882a593Smuzhiyun		/* LSTP0 */
642*4882a593Smuzhiyun		29 00 02 72 70
643*4882a593Smuzhiyun		29 00 02 73 60
644*4882a593Smuzhiyun		/* PRZ1 */
645*4882a593Smuzhiyun		29 00 02 20 01
646*4882a593Smuzhiyun		/* PRZ3 */
647*4882a593Smuzhiyun		/* Rescan=3 */
648*4882a593Smuzhiyun		29 00 02 33 11
649*4882a593Smuzhiyun		29 00 02 34 78
650*4882a593Smuzhiyun		29 00 02 35 16
651*4882a593Smuzhiyun		/* DLH */
652*4882a593Smuzhiyun		29 00 02 C8 04
653*4882a593Smuzhiyun		29 00 02 C9 80
654*4882a593Smuzhiyun		29 00 02 CA 4E
655*4882a593Smuzhiyun		29 00 02 CB 00
656*4882a593Smuzhiyun		29 00 02 A9 4C
657*4882a593Smuzhiyun		29 00 02 AA 47
658*4882a593Smuzhiyun		/* CMD2,Page7 */
659*4882a593Smuzhiyun		29 00 02 FF 27
660*4882a593Smuzhiyun		29 00 02 FB 01
661*4882a593Smuzhiyun		/* VPOR_DYNH_EN=1, VPOR_CNT_REV=1 */
662*4882a593Smuzhiyun		29 00 02 56 06
663*4882a593Smuzhiyun		/* FR0(60Hz) */
664*4882a593Smuzhiyun		29 00 02 58 80
665*4882a593Smuzhiyun		29 00 02 59 53
666*4882a593Smuzhiyun		29 00 02 5A 00
667*4882a593Smuzhiyun		29 00 02 5B 14
668*4882a593Smuzhiyun		29 00 02 5C 00
669*4882a593Smuzhiyun		29 00 02 5D 01
670*4882a593Smuzhiyun		29 00 02 5E 20
671*4882a593Smuzhiyun		29 00 02 5F 10
672*4882a593Smuzhiyun		29 00 02 60 00
673*4882a593Smuzhiyun		29 00 02 61 1D
674*4882a593Smuzhiyun		29 00 02 62 00
675*4882a593Smuzhiyun		29 00 02 63 01
676*4882a593Smuzhiyun		29 00 02 64 24
677*4882a593Smuzhiyun		29 00 02 65 1C
678*4882a593Smuzhiyun		29 00 02 66 00
679*4882a593Smuzhiyun		29 00 02 67 01
680*4882a593Smuzhiyun		29 00 02 68 25
681*4882a593Smuzhiyun		/* FR1(90Hz) */
682*4882a593Smuzhiyun		29 00 02 78 80
683*4882a593Smuzhiyun		29 00 02 79 73
684*4882a593Smuzhiyun		29 00 02 7A 00
685*4882a593Smuzhiyun		29 00 02 7B 14
686*4882a593Smuzhiyun		29 00 02 7C 00
687*4882a593Smuzhiyun		29 00 02 7D 02
688*4882a593Smuzhiyun		29 00 02 7E 20
689*4882a593Smuzhiyun		29 00 02 7F 21
690*4882a593Smuzhiyun		29 00 02 80 00
691*4882a593Smuzhiyun		29 00 02 81 2A
692*4882a593Smuzhiyun		29 00 02 82 00
693*4882a593Smuzhiyun		29 00 02 83 01
694*4882a593Smuzhiyun		29 00 02 84 1C
695*4882a593Smuzhiyun		29 00 02 85 28
696*4882a593Smuzhiyun		29 00 02 86 00
697*4882a593Smuzhiyun		29 00 02 87 01
698*4882a593Smuzhiyun		29 00 02 88 1D
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun		29 00 02 00 00
701*4882a593Smuzhiyun		29 00 02 C3 00
702*4882a593Smuzhiyun		/* FTE output TE, FTE1 output TSVD, LEDPWM output TSHD */
703*4882a593Smuzhiyun		29 00 02 D1 24
704*4882a593Smuzhiyun		29 00 02 D2 53
705*4882a593Smuzhiyun		/* CMD2,Page10 */
706*4882a593Smuzhiyun		29 00 02 FF 2A
707*4882a593Smuzhiyun		29 00 02 FB 01
708*4882a593Smuzhiyun		29 00 02 01 05
709*4882a593Smuzhiyun		29 00 02 02 55
710*4882a593Smuzhiyun		/* TP0 */
711*4882a593Smuzhiyun		29 00 02 03 05
712*4882a593Smuzhiyun		29 00 02 04 75
713*4882a593Smuzhiyun		/* TP3 */
714*4882a593Smuzhiyun		29 00 02 05 05
715*4882a593Smuzhiyun		29 00 02 06 75
716*4882a593Smuzhiyun		/* PEN_EN=1, UL_FREQ=0 */
717*4882a593Smuzhiyun		29 00 02 22 2F
718*4882a593Smuzhiyun		/* 90Hz */
719*4882a593Smuzhiyun		29 00 02 23 11
720*4882a593Smuzhiyun		/* FR0 (60Hz) */
721*4882a593Smuzhiyun		29 00 02 24 00
722*4882a593Smuzhiyun		29 00 02 25 75
723*4882a593Smuzhiyun		29 00 02 27 00
724*4882a593Smuzhiyun		29 00 02 28 1A
725*4882a593Smuzhiyun		29 00 02 29 00
726*4882a593Smuzhiyun		29 00 02 2A 1A
727*4882a593Smuzhiyun		29 00 02 2B 00
728*4882a593Smuzhiyun		29 00 02 2D 1A
729*4882a593Smuzhiyun		/* FR1 (90Hz) */
730*4882a593Smuzhiyun		29 00 02 2F 00
731*4882a593Smuzhiyun		29 00 02 30 55
732*4882a593Smuzhiyun		29 00 02 32 00
733*4882a593Smuzhiyun		29 00 02 33 1A
734*4882a593Smuzhiyun		29 00 02 34 00
735*4882a593Smuzhiyun		29 00 02 35 1A
736*4882a593Smuzhiyun		29 00 02 36 00
737*4882a593Smuzhiyun		29 00 02 37 1A
738*4882a593Smuzhiyun		/* CMD2,Page3 */
739*4882a593Smuzhiyun		29 00 02 FF 23
740*4882a593Smuzhiyun		29 00 02 FB 01
741*4882a593Smuzhiyun		/* DBV=12 bit */
742*4882a593Smuzhiyun		29 00 02 00 80
743*4882a593Smuzhiyun		/* PWM frequency */
744*4882a593Smuzhiyun		29 00 02 07 00
745*4882a593Smuzhiyun		/* CMD3,PageA */
746*4882a593Smuzhiyun		29 00 02 FF E0
747*4882a593Smuzhiyun		29 00 02 FB 01
748*4882a593Smuzhiyun		/* VCOM Driving Ability */
749*4882a593Smuzhiyun		29 00 02 14 60
750*4882a593Smuzhiyun		29 00 02 16 C0
751*4882a593Smuzhiyun		/* CMD3,PageB */
752*4882a593Smuzhiyun		29 00 02 FF F0
753*4882a593Smuzhiyun		29 00 02 FB 01
754*4882a593Smuzhiyun		/* slave osc workaround */
755*4882a593Smuzhiyun		29 00 02 3A 08
756*4882a593Smuzhiyun		/* CMD3,PageC */
757*4882a593Smuzhiyun		29 00 02 FF D0
758*4882a593Smuzhiyun		29 00 02 FB 01
759*4882a593Smuzhiyun		29 00 02 1C 88
760*4882a593Smuzhiyun		29 00 02 1D 08
761*4882a593Smuzhiyun		/* CMD1 */
762*4882a593Smuzhiyun		29 00 02 FF 10
763*4882a593Smuzhiyun		29 00 02 FB 01
764*4882a593Smuzhiyun		/* Only Write Slave */
765*4882a593Smuzhiyun		29 00 02 B9 01
766*4882a593Smuzhiyun		/* CMD2,Page0 */
767*4882a593Smuzhiyun		29 00 02 FF 20
768*4882a593Smuzhiyun		29 00 02 FB 01
769*4882a593Smuzhiyun		29 00 02 18 40
770*4882a593Smuzhiyun		/* CMD1 */
771*4882a593Smuzhiyun		29 00 02 FF 10
772*4882a593Smuzhiyun		29 00 02 FB 01
773*4882a593Smuzhiyun		/* Write Master & Slave */
774*4882a593Smuzhiyun		29 00 02 B9 02
775*4882a593Smuzhiyun		29 00 02 35 00
776*4882a593Smuzhiyun		29 00 03 51 00 FF
777*4882a593Smuzhiyun		29 00 02 53 24
778*4882a593Smuzhiyun		29 00 02 55 00
779*4882a593Smuzhiyun		29 00 02 BB 13
780*4882a593Smuzhiyun		/* VBP+VFP=121 */
781*4882a593Smuzhiyun		29 00 06 3B 03 5F 1A 04 04
782*4882a593Smuzhiyun		/* CMD2,Page5 */
783*4882a593Smuzhiyun		29 00 02 FF 25
784*4882a593Smuzhiyun		/* FRM */
785*4882a593Smuzhiyun		29 00 02 EC 00
786*4882a593Smuzhiyun		/* CMD1 */
787*4882a593Smuzhiyun		29 00 02 FF 10
788*4882a593Smuzhiyun		29 00 02 FB 01
789*4882a593Smuzhiyun		05 FF 01 11
790*4882a593Smuzhiyun		05 FF 01 29
791*4882a593Smuzhiyun	];
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun	panel-exit-sequence = [
794*4882a593Smuzhiyun		05 00 01 28
795*4882a593Smuzhiyun		05 00 01 10
796*4882a593Smuzhiyun	];
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun	disp_timings1: display-timings {
799*4882a593Smuzhiyun		native-mode = <&dsi1_timing0>;
800*4882a593Smuzhiyun		dsi1_timing0: timing0 {
801*4882a593Smuzhiyun			clock-frequency = <241300000>;
802*4882a593Smuzhiyun			hactive = <1200>;
803*4882a593Smuzhiyun			vactive = <2000>;
804*4882a593Smuzhiyun			hfront-porch = <31>;
805*4882a593Smuzhiyun			hsync-len = <4>;
806*4882a593Smuzhiyun			hback-porch = <32>;
807*4882a593Smuzhiyun			vfront-porch = <26>;
808*4882a593Smuzhiyun			vsync-len = <2>;
809*4882a593Smuzhiyun			vback-porch = <93>;
810*4882a593Smuzhiyun			hsync-active = <0>;
811*4882a593Smuzhiyun			vsync-active = <0>;
812*4882a593Smuzhiyun			de-active = <0>;
813*4882a593Smuzhiyun			pixelclk-active = <0>;
814*4882a593Smuzhiyun		};
815*4882a593Smuzhiyun	};
816*4882a593Smuzhiyun};
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun&hdmi1 {
819*4882a593Smuzhiyun	enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
820*4882a593Smuzhiyun	status = "okay";
821*4882a593Smuzhiyun};
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun&hdmi1_in_vp0 {
824*4882a593Smuzhiyun	status = "okay";
825*4882a593Smuzhiyun};
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun&hdmi1_sound {
828*4882a593Smuzhiyun	status = "okay";
829*4882a593Smuzhiyun};
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun&hdptxphy_hdmi1 {
832*4882a593Smuzhiyun	status = "okay";
833*4882a593Smuzhiyun};
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun&i2c0 {
836*4882a593Smuzhiyun	status = "okay";
837*4882a593Smuzhiyun	pinctrl-0 = <&i2c0m1_xfer>;
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun	ls_stk3332: light@47 {
840*4882a593Smuzhiyun		compatible = "ls_stk3332";
841*4882a593Smuzhiyun		status = "okay";
842*4882a593Smuzhiyun		reg = <0x47>;
843*4882a593Smuzhiyun		type = <SENSOR_TYPE_LIGHT>;
844*4882a593Smuzhiyun		irq_enable = <0>;
845*4882a593Smuzhiyun		als_threshold_high = <100>;
846*4882a593Smuzhiyun		als_threshold_low = <10>;
847*4882a593Smuzhiyun		als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */
848*4882a593Smuzhiyun		poll_delay_ms = <100>;
849*4882a593Smuzhiyun	};
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun	ps_stk3332: proximity@47 {
852*4882a593Smuzhiyun		compatible = "ps_stk3332";
853*4882a593Smuzhiyun		status = "okay";
854*4882a593Smuzhiyun		reg = <0x47>;
855*4882a593Smuzhiyun		type = <SENSOR_TYPE_PROXIMITY>;
856*4882a593Smuzhiyun		//pinctrl-names = "default";
857*4882a593Smuzhiyun		//pinctrl-0 = <&gpio2_b2>;
858*4882a593Smuzhiyun		//irq-gpio = <&gpio2 RK_PB2 IRQ_TYPE_LEVEL_LOW>;
859*4882a593Smuzhiyun		//irq_enable = <1>;
860*4882a593Smuzhiyun		ps_threshold_high = <0x200>;
861*4882a593Smuzhiyun		ps_threshold_low = <0x100>;
862*4882a593Smuzhiyun		ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */
863*4882a593Smuzhiyun		ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/
864*4882a593Smuzhiyun		poll_delay_ms = <100>;
865*4882a593Smuzhiyun	};
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun	mpu6500_acc: mpu_acc@68 {
868*4882a593Smuzhiyun		compatible = "mpu6500_acc";
869*4882a593Smuzhiyun		status = "okay";
870*4882a593Smuzhiyun		reg = <0x68>;
871*4882a593Smuzhiyun		irq-gpio = <&gpio2 RK_PB5 IRQ_TYPE_EDGE_RISING>;
872*4882a593Smuzhiyun		irq_enable = <0>;
873*4882a593Smuzhiyun		poll_delay_ms = <30>;
874*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
875*4882a593Smuzhiyun		layout = <9>;
876*4882a593Smuzhiyun	};
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun	mpu6500_gyro: mpu_gyro@68 {
879*4882a593Smuzhiyun		compatible = "mpu6500_gyro";
880*4882a593Smuzhiyun		status = "okay";
881*4882a593Smuzhiyun		reg = <0x68>;
882*4882a593Smuzhiyun		irq_enable = <0>;
883*4882a593Smuzhiyun		poll_delay_ms = <30>;
884*4882a593Smuzhiyun		type = <SENSOR_TYPE_GYROSCOPE>;
885*4882a593Smuzhiyun		layout = <9>;
886*4882a593Smuzhiyun	};
887*4882a593Smuzhiyun};
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun&i2c2 {
890*4882a593Smuzhiyun	status = "okay";
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun	usbc0: fusb302@22 {
893*4882a593Smuzhiyun		compatible = "fcs,fusb302";
894*4882a593Smuzhiyun		reg = <0x22>;
895*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
896*4882a593Smuzhiyun		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
897*4882a593Smuzhiyun		pinctrl-names = "default";
898*4882a593Smuzhiyun		pinctrl-0 = <&usbc0_int>;
899*4882a593Smuzhiyun		vbus-supply = <&vbus5v0_typec>;
900*4882a593Smuzhiyun		status = "okay";
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun		ports {
903*4882a593Smuzhiyun			#address-cells = <1>;
904*4882a593Smuzhiyun			#size-cells = <0>;
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun			port@0 {
907*4882a593Smuzhiyun				reg = <0>;
908*4882a593Smuzhiyun				usbc0_role_sw: endpoint@0 {
909*4882a593Smuzhiyun					remote-endpoint = <&dwc3_0_role_switch>;
910*4882a593Smuzhiyun				};
911*4882a593Smuzhiyun			};
912*4882a593Smuzhiyun		};
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun		usb_con: connector {
915*4882a593Smuzhiyun			compatible = "usb-c-connector";
916*4882a593Smuzhiyun			label = "USB-C";
917*4882a593Smuzhiyun			data-role = "dual";
918*4882a593Smuzhiyun			power-role = "dual";
919*4882a593Smuzhiyun			try-power-role = "sink";
920*4882a593Smuzhiyun			op-sink-microwatt = <1000000>;
921*4882a593Smuzhiyun			sink-pdos =
922*4882a593Smuzhiyun				<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
923*4882a593Smuzhiyun			source-pdos =
924*4882a593Smuzhiyun				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun			altmodes {
927*4882a593Smuzhiyun				#address-cells = <1>;
928*4882a593Smuzhiyun				#size-cells = <0>;
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun				altmode@0 {
931*4882a593Smuzhiyun					reg = <0>;
932*4882a593Smuzhiyun					svid = <0xff01>;
933*4882a593Smuzhiyun					vdo = <0xffffffff>;
934*4882a593Smuzhiyun				};
935*4882a593Smuzhiyun			};
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun			ports {
938*4882a593Smuzhiyun				#address-cells = <1>;
939*4882a593Smuzhiyun				#size-cells = <0>;
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun				port@0 {
942*4882a593Smuzhiyun					reg = <0>;
943*4882a593Smuzhiyun					usbc0_orien_sw: endpoint {
944*4882a593Smuzhiyun						remote-endpoint = <&usbdp_phy0_orientation_switch>;
945*4882a593Smuzhiyun					};
946*4882a593Smuzhiyun				};
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun				port@1 {
949*4882a593Smuzhiyun					reg = <1>;
950*4882a593Smuzhiyun					dp_altmode_mux: endpoint {
951*4882a593Smuzhiyun						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
952*4882a593Smuzhiyun					};
953*4882a593Smuzhiyun				};
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun			};
956*4882a593Smuzhiyun		};
957*4882a593Smuzhiyun	};
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun	hym8563: hym8563@51 {
960*4882a593Smuzhiyun		compatible = "haoyu,hym8563";
961*4882a593Smuzhiyun		reg = <0x51>;
962*4882a593Smuzhiyun		#clock-cells = <0>;
963*4882a593Smuzhiyun		clock-frequency = <32768>;
964*4882a593Smuzhiyun		clock-output-names = "hym8563";
965*4882a593Smuzhiyun		pinctrl-names = "default";
966*4882a593Smuzhiyun		pinctrl-0 = <&hym8563_int>;
967*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
968*4882a593Smuzhiyun		interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
969*4882a593Smuzhiyun		wakeup-source;
970*4882a593Smuzhiyun	};
971*4882a593Smuzhiyun};
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun&i2c5 {
974*4882a593Smuzhiyun	status = "okay";
975*4882a593Smuzhiyun	pinctrl-names = "default";
976*4882a593Smuzhiyun	pinctrl-0 = <&i2c5m4_xfer>;
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun	gt1x: gt1x@14 {
979*4882a593Smuzhiyun		compatible = "goodix,gt1x";
980*4882a593Smuzhiyun		reg = <0x14>;
981*4882a593Smuzhiyun		pinctrl-names = "default";
982*4882a593Smuzhiyun		pinctrl-0 = <&touch_gpio>;
983*4882a593Smuzhiyun		goodix,rst-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
984*4882a593Smuzhiyun		goodix,irq-gpio = <&gpio4 RK_PB1 IRQ_TYPE_LEVEL_LOW>;
985*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd_n>;
986*4882a593Smuzhiyun	};
987*4882a593Smuzhiyun};
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun&i2c7 {
990*4882a593Smuzhiyun	status = "okay";
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun	es8388: es8388@11 {
993*4882a593Smuzhiyun		status = "okay";
994*4882a593Smuzhiyun		#sound-dai-cells = <0>;
995*4882a593Smuzhiyun		compatible = "everest,es8388", "everest,es8323";
996*4882a593Smuzhiyun		reg = <0x11>;
997*4882a593Smuzhiyun		clocks = <&mclkout_i2s0>;
998*4882a593Smuzhiyun		clock-names = "mclk";
999*4882a593Smuzhiyun		assigned-clocks = <&mclkout_i2s0>;
1000*4882a593Smuzhiyun		assigned-clock-rates = <12288000>;
1001*4882a593Smuzhiyun		pinctrl-names = "default";
1002*4882a593Smuzhiyun		pinctrl-0 = <&i2s0_mclk>;
1003*4882a593Smuzhiyun	};
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun	es7202: es7202@32 {
1006*4882a593Smuzhiyun		status = "okay";
1007*4882a593Smuzhiyun		#sound-dai-cells = <0>;
1008*4882a593Smuzhiyun		compatible = "ES7202_PDM_ADC_1";
1009*4882a593Smuzhiyun		power-supply = <&vcc_1v8_s0>;	/* only 1v8 or 3v3, default is 3v3 */
1010*4882a593Smuzhiyun		reg = <0x32>;
1011*4882a593Smuzhiyun	};
1012*4882a593Smuzhiyun};
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun&i2s6_8ch {
1015*4882a593Smuzhiyun	status = "okay";
1016*4882a593Smuzhiyun};
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun&mipi_dcphy0 {
1019*4882a593Smuzhiyun	status = "okay";
1020*4882a593Smuzhiyun};
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun&mipi_dcphy1 {
1024*4882a593Smuzhiyun	status = "disabled";
1025*4882a593Smuzhiyun};
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun&pcie2x1l1 {
1028*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
1029*4882a593Smuzhiyun	pinctrl-names = "default";
1030*4882a593Smuzhiyun	pinctrl-0 = <&rtl8111_isolate>;
1031*4882a593Smuzhiyun	status = "okay";
1032*4882a593Smuzhiyun};
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun&pcie2x1l2 {
1035*4882a593Smuzhiyun	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
1036*4882a593Smuzhiyun	rockchip,skip-scan-in-resume;
1037*4882a593Smuzhiyun	status = "okay";
1038*4882a593Smuzhiyun};
1039*4882a593Smuzhiyun
1040*4882a593Smuzhiyun&pcie30phy {
1041*4882a593Smuzhiyun	status = "okay";
1042*4882a593Smuzhiyun};
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun&pcie3x4 {
1045*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
1046*4882a593Smuzhiyun	vpcie3v3-supply = <&vcc3v3_pcie30>;
1047*4882a593Smuzhiyun	pinctrl-names = "default";
1048*4882a593Smuzhiyun	pinctrl-0 = <&pcie30x4_clkreqn_m1>;
1049*4882a593Smuzhiyun	status = "okay";
1050*4882a593Smuzhiyun};
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun&pdm0 {
1053*4882a593Smuzhiyun	status = "okay";
1054*4882a593Smuzhiyun	pinctrl-names = "default";
1055*4882a593Smuzhiyun	pinctrl-0 = <&pdm0m0_clk
1056*4882a593Smuzhiyun		     &pdm0m0_sdi0>;
1057*4882a593Smuzhiyun};
1058*4882a593Smuzhiyun
1059*4882a593Smuzhiyun&pinctrl {
1060*4882a593Smuzhiyun	headphone {
1061*4882a593Smuzhiyun		hp_det: hp-det {
1062*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
1063*4882a593Smuzhiyun		};
1064*4882a593Smuzhiyun	};
1065*4882a593Smuzhiyun
1066*4882a593Smuzhiyun	hym8563 {
1067*4882a593Smuzhiyun		hym8563_int: hym8563-int {
1068*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
1069*4882a593Smuzhiyun		};
1070*4882a593Smuzhiyun	};
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun	lcd {
1073*4882a593Smuzhiyun		lcd_rst_gpio: lcd-rst-gpio {
1074*4882a593Smuzhiyun			rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1075*4882a593Smuzhiyun		};
1076*4882a593Smuzhiyun	};
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun	pcie30x4 {
1079*4882a593Smuzhiyun		pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
1080*4882a593Smuzhiyun			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
1081*4882a593Smuzhiyun		};
1082*4882a593Smuzhiyun	};
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun	rtl8111 {
1085*4882a593Smuzhiyun		rtl8111_isolate: rtl8111-isolate {
1086*4882a593Smuzhiyun			rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
1087*4882a593Smuzhiyun		};
1088*4882a593Smuzhiyun	};
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun	sensor {
1091*4882a593Smuzhiyun		mh248_irq_gpio: mh248-irq-gpio {
1092*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
1093*4882a593Smuzhiyun		};
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun		mpu6500_irq_gpio: mpu6500_irq_gpio {
1096*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
1097*4882a593Smuzhiyun		};
1098*4882a593Smuzhiyun	};
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun	touch {
1101*4882a593Smuzhiyun		touch_gpio: touch-gpio {
1102*4882a593Smuzhiyun			rockchip,pins =
1103*4882a593Smuzhiyun				<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
1104*4882a593Smuzhiyun				<4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
1105*4882a593Smuzhiyun		};
1106*4882a593Smuzhiyun	};
1107*4882a593Smuzhiyun
1108*4882a593Smuzhiyun	usb {
1109*4882a593Smuzhiyun		vcc5v0_host_en: vcc5v0-host-en {
1110*4882a593Smuzhiyun			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1111*4882a593Smuzhiyun		};
1112*4882a593Smuzhiyun	};
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun	usb-typec {
1115*4882a593Smuzhiyun		usbc0_int: usbc0-int {
1116*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
1117*4882a593Smuzhiyun		};
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun		typec5v_pwren: typec5v-pwren {
1120*4882a593Smuzhiyun			rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
1121*4882a593Smuzhiyun		};
1122*4882a593Smuzhiyun	};
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun	wireless-bluetooth {
1125*4882a593Smuzhiyun		uart8_gpios: uart8-gpios {
1126*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
1127*4882a593Smuzhiyun		};
1128*4882a593Smuzhiyun	};
1129*4882a593Smuzhiyun
1130*4882a593Smuzhiyun	wireless-wlan {
1131*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
1132*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
1133*4882a593Smuzhiyun		};
1134*4882a593Smuzhiyun
1135*4882a593Smuzhiyun		wifi_poweren_gpio: wifi-poweren-gpio {
1136*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
1137*4882a593Smuzhiyun		};
1138*4882a593Smuzhiyun	};
1139*4882a593Smuzhiyun};
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun&pwm6 {
1142*4882a593Smuzhiyun	pinctrl-0 = <&pwm6m1_pins>;
1143*4882a593Smuzhiyun	status = "okay";
1144*4882a593Smuzhiyun};
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun&pwm15 {
1147*4882a593Smuzhiyun	pinctrl-0 = <&pwm15m1_pins>;
1148*4882a593Smuzhiyun	status = "okay";
1149*4882a593Smuzhiyun};
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun&route_dsi0 {
1152*4882a593Smuzhiyun	status = "okay";
1153*4882a593Smuzhiyun	connect = <&vp3_out_dsi0>;
1154*4882a593Smuzhiyun};
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun&route_dsi1 {
1157*4882a593Smuzhiyun	status = "disabled";
1158*4882a593Smuzhiyun	connect = <&vp3_out_dsi1>;
1159*4882a593Smuzhiyun};
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun&sata1 {
1162*4882a593Smuzhiyun	status = "okay";
1163*4882a593Smuzhiyun};
1164*4882a593Smuzhiyun
1165*4882a593Smuzhiyun&sdmmc {
1166*4882a593Smuzhiyun	status = "okay";
1167*4882a593Smuzhiyun	vmmc-supply = <&vcc_3v3_sd_s0>;
1168*4882a593Smuzhiyun};
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun&spdif_tx5 {
1171*4882a593Smuzhiyun	status = "okay";
1172*4882a593Smuzhiyun};
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun&u2phy0_otg {
1175*4882a593Smuzhiyun	rockchip,typec-vbus-det;
1176*4882a593Smuzhiyun};
1177*4882a593Smuzhiyun
1178*4882a593Smuzhiyun&u2phy1_otg {
1179*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
1180*4882a593Smuzhiyun};
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun&u2phy2_host {
1183*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
1184*4882a593Smuzhiyun};
1185*4882a593Smuzhiyun
1186*4882a593Smuzhiyun&u2phy3_host {
1187*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
1188*4882a593Smuzhiyun};
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun&uart8 {
1191*4882a593Smuzhiyun	status = "okay";
1192*4882a593Smuzhiyun	pinctrl-names = "default";
1193*4882a593Smuzhiyun	pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>;
1194*4882a593Smuzhiyun};
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun&usbdp_phy0 {
1197*4882a593Smuzhiyun	orientation-switch;
1198*4882a593Smuzhiyun	svid = <0xff01>;
1199*4882a593Smuzhiyun	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
1200*4882a593Smuzhiyun	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun	port {
1203*4882a593Smuzhiyun		#address-cells = <1>;
1204*4882a593Smuzhiyun		#size-cells = <0>;
1205*4882a593Smuzhiyun		usbdp_phy0_orientation_switch: endpoint@0 {
1206*4882a593Smuzhiyun			reg = <0>;
1207*4882a593Smuzhiyun			remote-endpoint = <&usbc0_orien_sw>;
1208*4882a593Smuzhiyun		};
1209*4882a593Smuzhiyun
1210*4882a593Smuzhiyun		usbdp_phy0_dp_altmode_mux: endpoint@1 {
1211*4882a593Smuzhiyun			reg = <1>;
1212*4882a593Smuzhiyun			remote-endpoint = <&dp_altmode_mux>;
1213*4882a593Smuzhiyun		};
1214*4882a593Smuzhiyun	};
1215*4882a593Smuzhiyun};
1216*4882a593Smuzhiyun
1217*4882a593Smuzhiyun&usbdp_phy1 {
1218*4882a593Smuzhiyun	rockchip,dp-lane-mux = <2 3>;
1219*4882a593Smuzhiyun};
1220*4882a593Smuzhiyun
1221*4882a593Smuzhiyun&usbdrd_dwc3_0 {
1222*4882a593Smuzhiyun	dr_mode = "otg";
1223*4882a593Smuzhiyun	usb-role-switch;
1224*4882a593Smuzhiyun	port {
1225*4882a593Smuzhiyun		#address-cells = <1>;
1226*4882a593Smuzhiyun		#size-cells = <0>;
1227*4882a593Smuzhiyun		dwc3_0_role_switch: endpoint@0 {
1228*4882a593Smuzhiyun			reg = <0>;
1229*4882a593Smuzhiyun			remote-endpoint = <&usbc0_role_sw>;
1230*4882a593Smuzhiyun		};
1231*4882a593Smuzhiyun	};
1232*4882a593Smuzhiyun};
1233*4882a593Smuzhiyun
1234*4882a593Smuzhiyun&usbhost3_0 {
1235*4882a593Smuzhiyun	status = "disabled";
1236*4882a593Smuzhiyun};
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun&usbhost_dwc3_0 {
1239*4882a593Smuzhiyun	status = "disabled";
1240*4882a593Smuzhiyun};
1241