1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2021 Rockchip Electronics Co., Ltd. 3 4/dts-v1/; 5 6#include "rk3588-evb3-lp5.dtsi" 7#include "rk3588-linux.dtsi" 8 9/ { 10 model = "Rockchip RK3588 EVB3 LP5 V10 EDP Board"; 11 compatible = "rockchip,rk3588-evb3-lp5-v10-edp-linux", "rockchip,rk3588"; 12 13 panel-edp0 { 14 compatible = "simple-panel"; 15 backlight = <&backlight>; 16 power-supply = <&vcc3v3_lcd>; 17 prepare-delay-ms = <120>; 18 enable-delay-ms = <120>; 19 unprepare-delay-ms = <120>; 20 disable-delay-ms = <120>; 21 width-mm = <129>; 22 height-mm = <171>; 23 24 panel-timing { 25 clock-frequency = <200000000>; 26 hactive = <1536>; 27 vactive = <2048>; 28 hfront-porch = <12>; 29 hsync-len = <16>; 30 hback-porch = <48>; 31 vfront-porch = <8>; 32 vsync-len = <4>; 33 vback-porch = <8>; 34 hsync-active = <0>; 35 vsync-active = <0>; 36 de-active = <0>; 37 pixelclk-active = <0>; 38 }; 39 40 port { 41 panel_in_edp0: endpoint { 42 remote-endpoint = <&edp0_out_panel>; 43 }; 44 }; 45 }; 46 47 vcc3v3_lcd: vcc3v3-lcd { 48 compatible = "regulator-fixed"; 49 regulator-name = "vcc3v3_lcd"; 50 vin-supply = <&vcc_3v3_s0>; 51 }; 52}; 53 54&backlight { 55 enable-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; 56}; 57 58&dsi0 { 59 status = "disabled"; 60}; 61 62&edp0 { 63 force-hpd; 64 status = "okay"; 65 66 ports { 67 port@1 { 68 reg = <1>; 69 70 edp0_out_panel: endpoint { 71 remote-endpoint = <&panel_in_edp0>; 72 }; 73 }; 74 }; 75}; 76 77&edp0_in_vp2 { 78 status = "okay"; 79}; 80 81>1x { 82 status = "disabled"; 83}; 84 85&hdptxphy0 { 86 lane-polarity-invert = <0 1 0 0>; 87 status = "okay"; 88}; 89 90&i2c5 { 91 clock-frequency = <400000>; 92 status = "okay"; 93 94 gsl3673@40 { 95 compatible = "GSL,GSL3673"; 96 reg = <0x40>; 97 screen_max_x = <1536>; 98 screen_max_y = <2048>; 99 irq_gpio_number = <&gpio4 RK_PB1 IRQ_TYPE_LEVEL_LOW>; 100 rst_gpio_number = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 101 }; 102}; 103 104&pwm15 { 105 pinctrl-0 = <&pwm15m1_pins>; 106}; 107 108&vcc3v3_lcd_n { 109 /delete-property/ gpio; 110}; 111