1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include "dt-bindings/usb/pd.h" 8#include "rk3588.dtsi" 9#include "rk3588-evb.dtsi" 10#include "rk3588-rk806-dual.dtsi" 11 12/ { 13 /* If hdmirx node is disabled, delete the reserved-memory node here. */ 14 reserved-memory { 15 #address-cells = <2>; 16 #size-cells = <2>; 17 ranges; 18 19 /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ 20 cma { 21 compatible = "shared-dma-pool"; 22 reusable; 23 reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; 24 linux,cma-default; 25 }; 26 }; 27 28 es8388_sound: es8388-sound { 29 status = "okay"; 30 compatible = "rockchip,multicodecs-card"; 31 rockchip,card-name = "rockchip-es8388"; 32 hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 33 io-channels = <&saradc 3>; 34 io-channel-names = "adc-detect"; 35 keyup-threshold-microvolt = <1800000>; 36 poll-interval = <100>; 37 spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 38 hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; 39 rockchip,format = "i2s"; 40 rockchip,mclk-fs = <256>; 41 rockchip,cpu = <&i2s0_8ch>; 42 rockchip,codec = <&es8388>; 43 rockchip,audio-routing = 44 "Headphone", "LOUT1", 45 "Headphone", "ROUT1", 46 "Speaker", "LOUT2", 47 "Speaker", "ROUT2", 48 "Headphone", "Headphone Power", 49 "Headphone", "Headphone Power", 50 "Speaker", "Speaker Power", 51 "Speaker", "Speaker Power", 52 "LINPUT1", "Main Mic", 53 "LINPUT2", "Main Mic", 54 "RINPUT1", "Headset Mic", 55 "RINPUT2", "Headset Mic"; 56 pinctrl-names = "default"; 57 pinctrl-0 = <&hp_det>; 58 play-pause-key { 59 label = "playpause"; 60 linux,code = <KEY_PLAYPAUSE>; 61 press-threshold-microvolt = <2000>; 62 }; 63 }; 64 65 fan: pwm-fan { 66 compatible = "pwm-fan"; 67 #cooling-cells = <2>; 68 pwms = <&pwm9 0 50000 0>; 69 cooling-levels = <0 50 100 150 200 255>; 70 rockchip,temp-trips = < 71 50000 1 72 55000 2 73 60000 3 74 65000 4 75 70000 5 76 >; 77 }; 78 79 hdmiin-sound { 80 compatible = "rockchip,hdmi"; 81 rockchip,mclk-fs = <128>; 82 rockchip,format = "i2s"; 83 rockchip,bitclock-master = <&hdmirx_ctrler>; 84 rockchip,frame-master = <&hdmirx_ctrler>; 85 rockchip,card-name = "rockchip,hdmiin"; 86 rockchip,cpu = <&i2s7_8ch>; 87 rockchip,codec = <&hdmirx_ctrler 0>; 88 rockchip,jack-det; 89 }; 90 91 pcie20_avdd0v85: pcie20-avdd0v85 { 92 compatible = "regulator-fixed"; 93 regulator-name = "pcie20_avdd0v85"; 94 regulator-boot-on; 95 regulator-always-on; 96 regulator-min-microvolt = <850000>; 97 regulator-max-microvolt = <850000>; 98 vin-supply = <&avdd_0v85_s0>; 99 }; 100 101 pcie20_avdd1v8: pcie20-avdd1v8 { 102 compatible = "regulator-fixed"; 103 regulator-name = "pcie20_avdd1v8"; 104 regulator-boot-on; 105 regulator-always-on; 106 regulator-min-microvolt = <1800000>; 107 regulator-max-microvolt = <1800000>; 108 vin-supply = <&avcc_1v8_s0>; 109 }; 110 111 pcie30_avdd0v75: pcie30-avdd0v75 { 112 compatible = "regulator-fixed"; 113 regulator-name = "pcie30_avdd0v75"; 114 regulator-boot-on; 115 regulator-always-on; 116 regulator-min-microvolt = <750000>; 117 regulator-max-microvolt = <750000>; 118 vin-supply = <&avdd_0v75_s0>; 119 }; 120 121 pcie30_avdd1v8: pcie30-avdd1v8 { 122 compatible = "regulator-fixed"; 123 regulator-name = "pcie30_avdd1v8"; 124 regulator-boot-on; 125 regulator-always-on; 126 regulator-min-microvolt = <1800000>; 127 regulator-max-microvolt = <1800000>; 128 vin-supply = <&avcc_1v8_s0>; 129 }; 130 131 rk_headset: rk-headset { 132 status = "disabled"; 133 compatible = "rockchip_headset"; 134 headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&hp_det>; 137 io-channels = <&saradc 3>; 138 }; 139 140 vbus5v0_typec: vbus5v0-typec { 141 compatible = "regulator-fixed"; 142 regulator-name = "vbus5v0_typec"; 143 regulator-min-microvolt = <5000000>; 144 regulator-max-microvolt = <5000000>; 145 enable-active-high; 146 gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; 147 vin-supply = <&vcc5v0_usb>; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&typec5v_pwren>; 150 }; 151 152 vcc3v3_lcd_n: vcc3v3-lcd0-n { 153 compatible = "regulator-fixed"; 154 regulator-name = "vcc3v3_lcd0_n"; 155 regulator-boot-on; 156 enable-active-high; 157 gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; 158 vin-supply = <&vcc_1v8_s0>; 159 }; 160 161 vcc3v3_pcie30: vcc3v3-pcie30 { 162 compatible = "regulator-fixed"; 163 regulator-name = "vcc3v3_pcie30"; 164 regulator-min-microvolt = <3300000>; 165 regulator-max-microvolt = <3300000>; 166 enable-active-high; 167 gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; 168 startup-delay-us = <5000>; 169 vin-supply = <&vcc12v_dcin>; 170 }; 171 172 vcc5v0_host: vcc5v0-host { 173 compatible = "regulator-fixed"; 174 regulator-name = "vcc5v0_host"; 175 regulator-boot-on; 176 regulator-always-on; 177 regulator-min-microvolt = <5000000>; 178 regulator-max-microvolt = <5000000>; 179 enable-active-high; 180 gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 181 vin-supply = <&vcc5v0_usb>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&vcc5v0_host_en>; 184 }; 185 186 vcc_mipicsi0: vcc-mipicsi0-regulator { 187 compatible = "regulator-fixed"; 188 gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; 189 pinctrl-names = "default"; 190 pinctrl-0 = <&mipicsi0_pwr>; 191 regulator-name = "vcc_mipicsi0"; 192 enable-active-high; 193 }; 194 195 vcc_mipicsi1: vcc-mipicsi1-regulator { 196 compatible = "regulator-fixed"; 197 gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&mipicsi1_pwr>; 200 regulator-name = "vcc_mipicsi1"; 201 enable-active-high; 202 }; 203 204 vcc_mipidcphy0: vcc-mipidcphy0-regulator { 205 compatible = "regulator-fixed"; 206 gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; 207 pinctrl-names = "default"; 208 pinctrl-0 = <&mipidcphy0_pwr>; 209 regulator-name = "vcc_mipidcphy0"; 210 enable-active-high; 211 }; 212 213 wireless_bluetooth: wireless-bluetooth { 214 compatible = "bluetooth-platdata"; 215 clocks = <&hym8563>; 216 clock-names = "ext_clock"; 217 uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; 218 pinctrl-names = "default", "rts_gpio"; 219 pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; 220 pinctrl-1 = <&uart8_gpios>; 221 BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; 222 BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 223 BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; 224 status = "okay"; 225 }; 226 227 wireless_wlan: wireless-wlan { 228 compatible = "wlan-platdata"; 229 wifi_chip_type = "ap6255"; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; 232 WIFI,host_wake_irq = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; 233 WIFI,poweren_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; 234 status = "okay"; 235 }; 236}; 237 238&backlight { 239 pwms = <&pwm2 0 25000 0>; 240 status = "okay"; 241}; 242 243&combphy0_ps { 244 status = "okay"; 245}; 246 247&combphy1_ps { 248 status = "okay"; 249}; 250 251&combphy2_psu { 252 status = "okay"; 253}; 254 255&dp0 { 256 status = "okay"; 257}; 258 259&dp0_in_vp2 { 260 status = "okay"; 261}; 262 263&dp0_sound{ 264 status = "okay"; 265}; 266 267&dp1 { 268 pinctrl-names = "default"; 269 pinctrl-0 = <&dp1_hpd>; 270 hpd-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; 271 status = "okay"; 272}; 273 274&dp1_in_vp2 { 275 status = "okay"; 276}; 277 278/* 279 * mipi_dcphy0 needs to be enabled 280 * when dsi0 is enabled 281 */ 282&dsi0 { 283 status = "okay"; 284}; 285 286&dsi0_in_vp2 { 287 status = "disabled"; 288}; 289 290&dsi0_in_vp3 { 291 status = "okay"; 292}; 293 294&dsi0_panel { 295 power-supply = <&vcc3v3_lcd_n>; 296 reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&lcd_rst_gpio>; 299}; 300 301/* 302 * mipi_dcphy1 needs to be enabled 303 * when dsi1 is enabled 304 */ 305&dsi1 { 306 status = "disabled"; 307}; 308 309&dsi1_in_vp2 { 310 status = "disabled"; 311}; 312 313&dsi1_in_vp3 { 314 status = "disabled"; 315}; 316 317&dsi1_panel { 318 power-supply = <&vcc3v3_lcd_n>; 319 320 /* 321 * because in hardware, the two screens share the reset pin, 322 * so reset-gpios need only in dsi1 enable and dsi0 disabled 323 * case. 324 */ 325 326 //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; 327 //pinctrl-names = "default"; 328 //pinctrl-0 = <&lcd_rst_gpio>; 329}; 330 331&gmac0 { 332 /* Use rgmii-rxid mode to disable rx delay inside Soc */ 333 phy-mode = "rgmii-rxid"; 334 clock_in_out = "output"; 335 336 snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; 337 snps,reset-active-low; 338 /* Reset time is 20ms, 100ms for rtl8211f */ 339 snps,reset-delays-us = <0 20000 100000>; 340 341 pinctrl-names = "default"; 342 pinctrl-0 = <&gmac0_miim 343 &gmac0_tx_bus2 344 &gmac0_rx_bus2 345 &gmac0_rgmii_clk 346 &gmac0_rgmii_bus>; 347 348 tx_delay = <0x43>; 349 /* rx_delay = <0x3f>; */ 350 351 phy-handle = <&rgmii_phy>; 352 status = "okay"; 353}; 354 355&hdmi0 { 356 enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 357 status = "okay"; 358}; 359 360&hdmi0_in_vp0 { 361 status = "okay"; 362}; 363 364&hdmi0_sound { 365 status = "okay"; 366}; 367 368&hdmi1 { 369 enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 370 status = "okay"; 371}; 372 373&hdmi1_in_vp1 { 374 status = "okay"; 375}; 376 377&hdmi1_sound { 378 status = "okay"; 379}; 380 381/* Should work with at least 128MB cma reserved above. */ 382&hdmirx_ctrler { 383 status = "okay"; 384 385 #sound-dai-cells = <1>; 386 /* Effective level used to trigger HPD: 0-low, 1-high */ 387 hpd-trigger-level = <1>; 388 hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&hdmim1_rx &hdmirx_det>; 391}; 392 393&hdptxphy_hdmi0 { 394 status = "okay"; 395}; 396 397&hdptxphy_hdmi1 { 398 status = "okay"; 399}; 400 401&i2c2 { 402 status = "okay"; 403 404 usbc0: fusb302@22 { 405 compatible = "fcs,fusb302"; 406 reg = <0x22>; 407 interrupt-parent = <&gpio3>; 408 interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&usbc0_int>; 411 vbus-supply = <&vbus5v0_typec>; 412 status = "okay"; 413 414 ports { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 418 port@0 { 419 reg = <0>; 420 usbc0_role_sw: endpoint@0 { 421 remote-endpoint = <&dwc3_0_role_switch>; 422 }; 423 }; 424 }; 425 426 usb_con: connector { 427 compatible = "usb-c-connector"; 428 label = "USB-C"; 429 data-role = "dual"; 430 power-role = "dual"; 431 try-power-role = "sink"; 432 op-sink-microwatt = <1000000>; 433 sink-pdos = 434 <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; 435 source-pdos = 436 <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 437 438 altmodes { 439 #address-cells = <1>; 440 #size-cells = <0>; 441 442 altmode@0 { 443 reg = <0>; 444 svid = <0xff01>; 445 vdo = <0xffffffff>; 446 }; 447 }; 448 449 ports { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 453 port@0 { 454 reg = <0>; 455 usbc0_orien_sw: endpoint { 456 remote-endpoint = <&usbdp_phy0_orientation_switch>; 457 }; 458 }; 459 460 port@1 { 461 reg = <1>; 462 dp_altmode_mux: endpoint { 463 remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; 464 }; 465 }; 466 }; 467 }; 468 }; 469 470 hym8563: hym8563@51 { 471 compatible = "haoyu,hym8563"; 472 reg = <0x51>; 473 #clock-cells = <0>; 474 clock-frequency = <32768>; 475 clock-output-names = "hym8563"; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&hym8563_int>; 478 interrupt-parent = <&gpio0>; 479 interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; 480 wakeup-source; 481 }; 482}; 483 484&i2c6 { 485 status = "okay"; 486 gt1x: gt1x@14 { 487 compatible = "goodix,gt1x"; 488 reg = <0x14>; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&touch_gpio>; 491 goodix,rst-gpio = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; 492 goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; 493 power-supply = <&vcc3v3_lcd_n>; 494 }; 495}; 496 497&i2c7 { 498 status = "okay"; 499 es8388: es8388@11 { 500 status = "okay"; 501 #sound-dai-cells = <0>; 502 compatible = "everest,es8388", "everest,es8323"; 503 reg = <0x11>; 504 clocks = <&mclkout_i2s0>; 505 clock-names = "mclk"; 506 assigned-clocks = <&mclkout_i2s0>; 507 assigned-clock-rates = <12288000>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&i2s0_mclk>; 510 }; 511}; 512 513&i2s5_8ch { 514 status = "okay"; 515}; 516 517&i2s6_8ch { 518 status = "okay"; 519}; 520 521&i2s7_8ch { 522 status = "okay"; 523}; 524 525&mdio0 { 526 rgmii_phy: phy@1 { 527 compatible = "ethernet-phy-ieee802.3-c22"; 528 reg = <0x1>; 529 }; 530}; 531 532&mipi_dcphy0 { 533 status = "okay"; 534}; 535 536&mipi_dcphy1 { 537 status = "disabled"; 538}; 539 540&pcie2x1l0 { 541 reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; 542 rockchip,skip-scan-in-resume; 543 status = "okay"; 544}; 545 546&pcie2x1l1 { 547 reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&rtl8111_isolate>; 550 status = "okay"; 551}; 552 553&pcie30phy { 554 rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>; 555 status = "okay"; 556}; 557 558&pcie3x4 { 559 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 560 vpcie3v3-supply = <&vcc3v3_pcie30>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pcie30x4_clkreqn_m1>; 563 status = "okay"; 564}; 565 566&pinctrl { 567 cam { 568 mipicsi0_pwr: mipicsi0-pwr { 569 rockchip,pins = 570 /* camera power en */ 571 <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 572 }; 573 mipicsi1_pwr: mipicsi1-pwr { 574 rockchip,pins = 575 /* camera power en */ 576 <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 577 }; 578 mipidcphy0_pwr: mipidcphy0-pwr { 579 rockchip,pins = 580 /* camera power en */ 581 <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 582 }; 583 }; 584 585 dp { 586 dp1_hpd: dp1-hpd { 587 rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 588 }; 589 }; 590 591 hdmi { 592 hdmirx_det: hdmirx-det { 593 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; 594 }; 595 }; 596 597 headphone { 598 hp_det: hp-det { 599 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 600 }; 601 }; 602 603 hym8563 { 604 hym8563_int: hym8563-int { 605 rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 606 }; 607 }; 608 609 lcd { 610 lcd_rst_gpio: lcd-rst-gpio { 611 rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 612 }; 613 }; 614 615 pcie30x4 { 616 pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { 617 rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; 618 }; 619 }; 620 621 rtl8111 { 622 rtl8111_isolate: rtl8111-isolate { 623 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 624 }; 625 }; 626 627 touch { 628 touch_gpio: touch-gpio { 629 rockchip,pins = 630 <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, 631 <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; 632 }; 633 }; 634 635 usb { 636 vcc5v0_host_en: vcc5v0-host-en { 637 rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 638 }; 639 }; 640 641 usb-typec { 642 usbc0_int: usbc0-int { 643 rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; 644 }; 645 646 typec5v_pwren: typec5v-pwren { 647 rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 648 }; 649 }; 650 651 wireless-bluetooth { 652 uart8_gpios: uart8-gpios { 653 rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 654 }; 655 656 bt_reset_gpio: bt-reset-gpio { 657 rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 658 }; 659 660 bt_wake_gpio: bt-wake-gpio { 661 rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; 662 }; 663 664 bt_irq_gpio: bt-irq-gpio { 665 rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; 666 }; 667 }; 668 669 wireless-wlan { 670 wifi_host_wake_irq: wifi-host-wake-irq { 671 rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; 672 }; 673 674 wifi_poweren_gpio: wifi-poweren-gpio { 675 rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 676 }; 677 }; 678}; 679 680&pwm2 { 681 status = "okay"; 682}; 683 684&pwm9 { 685 pinctrl-0 = <&pwm9m1_pins>; 686 status = "okay"; 687}; 688 689&route_dsi0 { 690 status = "okay"; 691 connect = <&vp3_out_dsi0>; 692}; 693 694&route_dsi1 { 695 status = "disabled"; 696 connect = <&vp3_out_dsi1>; 697}; 698 699&route_hdmi0 { 700 status = "okay"; 701 connect = <&vp0_out_hdmi0>; 702}; 703 704&route_hdmi1 { 705 status = "okay"; 706 connect = <&vp1_out_hdmi1>; 707}; 708 709&sata0 { 710 status = "okay"; 711}; 712 713&spdif_tx2 { 714 status = "okay"; 715}; 716 717&u2phy0_otg { 718 rockchip,typec-vbus-det; 719}; 720 721&u2phy1_otg { 722 phy-supply = <&vcc5v0_host>; 723}; 724 725&u2phy2_host { 726 phy-supply = <&vcc5v0_host>; 727}; 728 729&u2phy3_host { 730 phy-supply = <&vcc5v0_host>; 731}; 732 733&uart8 { 734 status = "okay"; 735 pinctrl-names = "default"; 736 pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; 737}; 738 739&usbdp_phy0 { 740 orientation-switch; 741 svid = <0xff01>; 742 sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 743 sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 744 745 port { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 usbdp_phy0_orientation_switch: endpoint@0 { 749 reg = <0>; 750 remote-endpoint = <&usbc0_orien_sw>; 751 }; 752 753 usbdp_phy0_dp_altmode_mux: endpoint@1 { 754 reg = <1>; 755 remote-endpoint = <&dp_altmode_mux>; 756 }; 757 }; 758}; 759 760&usbdp_phy1 { 761 rockchip,dp-lane-mux = <2 3>; 762}; 763 764&usbdrd_dwc3_0 { 765 dr_mode = "otg"; 766 usb-role-switch; 767 port { 768 #address-cells = <1>; 769 #size-cells = <0>; 770 dwc3_0_role_switch: endpoint@0 { 771 reg = <0>; 772 remote-endpoint = <&usbc0_role_sw>; 773 }; 774 }; 775}; 776 777&usbhost3_0 { 778 status = "disabled"; 779}; 780 781&usbhost_dwc3_0 { 782 status = "disabled"; 783}; 784