xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3588-evb1-imx415.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/ {
8*4882a593Smuzhiyun	cam_ircut0: cam_ircut {
9*4882a593Smuzhiyun		status = "okay";
10*4882a593Smuzhiyun		compatible = "rockchip,ircut";
11*4882a593Smuzhiyun		ircut-open-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
12*4882a593Smuzhiyun		ircut-close-gpios  = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
13*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
14*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
15*4882a593Smuzhiyun	};
16*4882a593Smuzhiyun};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun&csi2_dcphy0 {
19*4882a593Smuzhiyun	status = "okay";
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	ports {
22*4882a593Smuzhiyun		#address-cells = <1>;
23*4882a593Smuzhiyun		#size-cells = <0>;
24*4882a593Smuzhiyun		port@0 {
25*4882a593Smuzhiyun			reg = <0>;
26*4882a593Smuzhiyun			#address-cells = <1>;
27*4882a593Smuzhiyun			#size-cells = <0>;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
30*4882a593Smuzhiyun				reg = <1>;
31*4882a593Smuzhiyun				remote-endpoint = <&imx415_out0>;
32*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
33*4882a593Smuzhiyun			};
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun		port@1 {
36*4882a593Smuzhiyun			reg = <1>;
37*4882a593Smuzhiyun			#address-cells = <1>;
38*4882a593Smuzhiyun			#size-cells = <0>;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun			csidcphy0_out: endpoint@0 {
41*4882a593Smuzhiyun				reg = <0>;
42*4882a593Smuzhiyun				remote-endpoint = <&mipi0_csi2_input>;
43*4882a593Smuzhiyun			};
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun&i2c5 {
49*4882a593Smuzhiyun	status = "okay";
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	imx415: imx415@1a {
52*4882a593Smuzhiyun		compatible = "sony,imx415";
53*4882a593Smuzhiyun		reg = <0x1a>;
54*4882a593Smuzhiyun		clocks = <&cru CLK_MIPI_CAMARAOUT_M1>;
55*4882a593Smuzhiyun		clock-names = "xvclk";
56*4882a593Smuzhiyun		pinctrl-names = "default";
57*4882a593Smuzhiyun		pinctrl-0 = <&mipim0_camera1_clk>;
58*4882a593Smuzhiyun		power-domains = <&power RK3588_PD_VI>;
59*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
60*4882a593Smuzhiyun		avdd-supply = <&vcc_mipidcphy0>;
61*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
62*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
63*4882a593Smuzhiyun		rockchip,camera-module-name = "CMK-OT2022-PX1";
64*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
65*4882a593Smuzhiyun		lens-focus = <&cam_ircut0>;
66*4882a593Smuzhiyun		port {
67*4882a593Smuzhiyun			imx415_out0: endpoint {
68*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
69*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
70*4882a593Smuzhiyun			};
71*4882a593Smuzhiyun		};
72*4882a593Smuzhiyun	};
73*4882a593Smuzhiyun};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun&mipi_dcphy0 {
76*4882a593Smuzhiyun	status = "okay";
77*4882a593Smuzhiyun};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun&mipi0_csi2 {
80*4882a593Smuzhiyun	status = "okay";
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	ports {
83*4882a593Smuzhiyun		#address-cells = <1>;
84*4882a593Smuzhiyun		#size-cells = <0>;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun		port@0 {
87*4882a593Smuzhiyun			reg = <0>;
88*4882a593Smuzhiyun			#address-cells = <1>;
89*4882a593Smuzhiyun			#size-cells = <0>;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun			mipi0_csi2_input: endpoint@1 {
92*4882a593Smuzhiyun				reg = <1>;
93*4882a593Smuzhiyun				remote-endpoint = <&csidcphy0_out>;
94*4882a593Smuzhiyun			};
95*4882a593Smuzhiyun		};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		port@1 {
98*4882a593Smuzhiyun			reg = <1>;
99*4882a593Smuzhiyun			#address-cells = <1>;
100*4882a593Smuzhiyun			#size-cells = <0>;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun			mipi0_csi2_output: endpoint@0 {
103*4882a593Smuzhiyun				reg = <0>;
104*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in0>;
105*4882a593Smuzhiyun			};
106*4882a593Smuzhiyun		};
107*4882a593Smuzhiyun	};
108*4882a593Smuzhiyun};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun&rkcif {
111*4882a593Smuzhiyun	status = "okay";
112*4882a593Smuzhiyun};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun&rkcif_mipi_lvds {
115*4882a593Smuzhiyun	status = "okay";
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun	port {
118*4882a593Smuzhiyun		cif_mipi_in0: endpoint {
119*4882a593Smuzhiyun			remote-endpoint = <&mipi0_csi2_output>;
120*4882a593Smuzhiyun		};
121*4882a593Smuzhiyun	};
122*4882a593Smuzhiyun};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf {
125*4882a593Smuzhiyun	status = "okay";
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun	port {
128*4882a593Smuzhiyun		mipi_lvds_sditf: endpoint {
129*4882a593Smuzhiyun			remote-endpoint = <&isp0_vir0>;
130*4882a593Smuzhiyun		};
131*4882a593Smuzhiyun	};
132*4882a593Smuzhiyun};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun&rkcif_mmu {
135*4882a593Smuzhiyun	status = "okay";
136*4882a593Smuzhiyun};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun&rkisp0 {
139*4882a593Smuzhiyun	status = "okay";
140*4882a593Smuzhiyun};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun&isp0_mmu {
143*4882a593Smuzhiyun	status = "okay";
144*4882a593Smuzhiyun};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun&rkisp0_vir0 {
147*4882a593Smuzhiyun	status = "okay";
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun	port {
150*4882a593Smuzhiyun		#address-cells = <1>;
151*4882a593Smuzhiyun		#size-cells = <0>;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun		isp0_vir0: endpoint@0 {
154*4882a593Smuzhiyun			reg = <0>;
155*4882a593Smuzhiyun			remote-endpoint = <&mipi_lvds_sditf>;
156*4882a593Smuzhiyun		};
157*4882a593Smuzhiyun	};
158*4882a593Smuzhiyun};
159