1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/delete-node/ &cpu_l0; 7*4882a593Smuzhiyun/delete-node/ &cpu_l1; 8*4882a593Smuzhiyun/delete-node/ &cpu_l2; 9*4882a593Smuzhiyun/delete-node/ &cpu_l3; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun cpus { 13*4882a593Smuzhiyun cpu_l0: cpu@0000 { 14*4882a593Smuzhiyun device_type = "cpu"; 15*4882a593Smuzhiyun compatible = "arm,cortex-a55"; 16*4882a593Smuzhiyun reg = <0x0>; 17*4882a593Smuzhiyun enable-method = "psci"; 18*4882a593Smuzhiyun capacity-dmips-mhz = <530>; 19*4882a593Smuzhiyun clocks = <&scmi_clk SCMI_CLK_CPUL>; 20*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp_table>; 21*4882a593Smuzhiyun cpu-idle-states = <&CPU_SLEEP>; 22*4882a593Smuzhiyun i-cache-size = <32768>; 23*4882a593Smuzhiyun i-cache-line-size = <64>; 24*4882a593Smuzhiyun i-cache-sets = <128>; 25*4882a593Smuzhiyun d-cache-size = <32768>; 26*4882a593Smuzhiyun d-cache-line-size = <64>; 27*4882a593Smuzhiyun d-cache-sets = <128>; 28*4882a593Smuzhiyun next-level-cache = <&l2_cache_l0>; 29*4882a593Smuzhiyun #cooling-cells = <2>; 30*4882a593Smuzhiyun dynamic-power-coefficient = <100>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun cpu_l1: cpu@0100 { 34*4882a593Smuzhiyun device_type = "cpu"; 35*4882a593Smuzhiyun compatible = "arm,cortex-a55"; 36*4882a593Smuzhiyun reg = <0x100>; 37*4882a593Smuzhiyun enable-method = "psci"; 38*4882a593Smuzhiyun capacity-dmips-mhz = <530>; 39*4882a593Smuzhiyun clocks = <&scmi_clk SCMI_CLK_CPUL>; 40*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp_table>; 41*4882a593Smuzhiyun cpu-idle-states = <&CPU_SLEEP>; 42*4882a593Smuzhiyun i-cache-size = <32768>; 43*4882a593Smuzhiyun i-cache-line-size = <64>; 44*4882a593Smuzhiyun i-cache-sets = <128>; 45*4882a593Smuzhiyun d-cache-size = <32768>; 46*4882a593Smuzhiyun d-cache-line-size = <64>; 47*4882a593Smuzhiyun d-cache-sets = <128>; 48*4882a593Smuzhiyun next-level-cache = <&l2_cache_l1>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun cpu_l2: cpu@0200 { 52*4882a593Smuzhiyun device_type = "cpu"; 53*4882a593Smuzhiyun compatible = "arm,cortex-a55"; 54*4882a593Smuzhiyun reg = <0x200>; 55*4882a593Smuzhiyun enable-method = "psci"; 56*4882a593Smuzhiyun capacity-dmips-mhz = <530>; 57*4882a593Smuzhiyun clocks = <&scmi_clk SCMI_CLK_CPUL>; 58*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp_table>; 59*4882a593Smuzhiyun cpu-idle-states = <&CPU_SLEEP>; 60*4882a593Smuzhiyun i-cache-size = <32768>; 61*4882a593Smuzhiyun i-cache-line-size = <64>; 62*4882a593Smuzhiyun i-cache-sets = <128>; 63*4882a593Smuzhiyun d-cache-size = <32768>; 64*4882a593Smuzhiyun d-cache-line-size = <64>; 65*4882a593Smuzhiyun d-cache-sets = <128>; 66*4882a593Smuzhiyun next-level-cache = <&l2_cache_l2>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun cpu_l3: cpu@0300 { 70*4882a593Smuzhiyun device_type = "cpu"; 71*4882a593Smuzhiyun compatible = "arm,cortex-a55"; 72*4882a593Smuzhiyun reg = <0x300>; 73*4882a593Smuzhiyun enable-method = "psci"; 74*4882a593Smuzhiyun capacity-dmips-mhz = <530>; 75*4882a593Smuzhiyun clocks = <&scmi_clk SCMI_CLK_CPUL>; 76*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp_table>; 77*4882a593Smuzhiyun cpu-idle-states = <&CPU_SLEEP>; 78*4882a593Smuzhiyun i-cache-size = <32768>; 79*4882a593Smuzhiyun i-cache-line-size = <64>; 80*4882a593Smuzhiyun i-cache-sets = <128>; 81*4882a593Smuzhiyun d-cache-size = <32768>; 82*4882a593Smuzhiyun d-cache-line-size = <64>; 83*4882a593Smuzhiyun d-cache-sets = <128>; 84*4882a593Smuzhiyun next-level-cache = <&l2_cache_l3>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun}; 88