1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6/delete-node/ &cpu_l0; 7/delete-node/ &cpu_l1; 8/delete-node/ &cpu_l2; 9/delete-node/ &cpu_l3; 10 11/ { 12 cpus { 13 cpu_l0: cpu@0000 { 14 device_type = "cpu"; 15 compatible = "arm,cortex-a55"; 16 reg = <0x0>; 17 enable-method = "psci"; 18 capacity-dmips-mhz = <530>; 19 clocks = <&scmi_clk SCMI_CLK_CPUL>; 20 operating-points-v2 = <&cluster0_opp_table>; 21 cpu-idle-states = <&CPU_SLEEP>; 22 i-cache-size = <32768>; 23 i-cache-line-size = <64>; 24 i-cache-sets = <128>; 25 d-cache-size = <32768>; 26 d-cache-line-size = <64>; 27 d-cache-sets = <128>; 28 next-level-cache = <&l2_cache_l0>; 29 #cooling-cells = <2>; 30 dynamic-power-coefficient = <100>; 31 }; 32 33 cpu_l1: cpu@0100 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a55"; 36 reg = <0x100>; 37 enable-method = "psci"; 38 capacity-dmips-mhz = <530>; 39 clocks = <&scmi_clk SCMI_CLK_CPUL>; 40 operating-points-v2 = <&cluster0_opp_table>; 41 cpu-idle-states = <&CPU_SLEEP>; 42 i-cache-size = <32768>; 43 i-cache-line-size = <64>; 44 i-cache-sets = <128>; 45 d-cache-size = <32768>; 46 d-cache-line-size = <64>; 47 d-cache-sets = <128>; 48 next-level-cache = <&l2_cache_l1>; 49 }; 50 51 cpu_l2: cpu@0200 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a55"; 54 reg = <0x200>; 55 enable-method = "psci"; 56 capacity-dmips-mhz = <530>; 57 clocks = <&scmi_clk SCMI_CLK_CPUL>; 58 operating-points-v2 = <&cluster0_opp_table>; 59 cpu-idle-states = <&CPU_SLEEP>; 60 i-cache-size = <32768>; 61 i-cache-line-size = <64>; 62 i-cache-sets = <128>; 63 d-cache-size = <32768>; 64 d-cache-line-size = <64>; 65 d-cache-sets = <128>; 66 next-level-cache = <&l2_cache_l2>; 67 }; 68 69 cpu_l3: cpu@0300 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a55"; 72 reg = <0x300>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <530>; 75 clocks = <&scmi_clk SCMI_CLK_CPUL>; 76 operating-points-v2 = <&cluster0_opp_table>; 77 cpu-idle-states = <&CPU_SLEEP>; 78 i-cache-size = <32768>; 79 i-cache-line-size = <64>; 80 i-cache-sets = <128>; 81 d-cache-size = <32768>; 82 d-cache-line-size = <64>; 83 d-cache-sets = <128>; 84 next-level-cache = <&l2_cache_l3>; 85 }; 86 }; 87}; 88