1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun rockchip_amp: rockchip-amp { 8*4882a593Smuzhiyun compatible = "rockchip,mcu-amp"; 9*4882a593Smuzhiyun clocks = <&cru HCLK_PMU_CM0_ROOT>, <&cru FCLK_PMU_CM0_CORE>, 10*4882a593Smuzhiyun <&cru CLK_PMU_CM0_RTC>, <&cru PCLK_PMUCM0_INTMUX>, 11*4882a593Smuzhiyun <&cru SCLK_UART5>, <&cru PCLK_UART5>, 12*4882a593Smuzhiyun <&cru PCLK_BUSTIMER1>, <&cru CLK_BUSTIMER10>, <&cru CLK_BUSTIMER11>; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun pinctrl-names = "default"; 15*4882a593Smuzhiyun pinctrl-0 = <&uart5m0_xfer>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun status = "okay"; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reserved-memory { 21*4882a593Smuzhiyun #address-cells = <2>; 22*4882a593Smuzhiyun #size-cells = <2>; 23*4882a593Smuzhiyun ranges; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* mcu address */ 26*4882a593Smuzhiyun mcu_reserved: mcu@8200000 { 27*4882a593Smuzhiyun reg = <0x0 0x8200000 0x0 0x100000>; 28*4882a593Smuzhiyun no-map; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun}; 32