1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun aliases { 9*4882a593Smuzhiyun mmc0 = &sdhci; 10*4882a593Smuzhiyun mmc1 = &sdmmc0; 11*4882a593Smuzhiyun mmc2 = &sdmmc1; 12*4882a593Smuzhiyun mmc3 = &sdmmc2; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun chosen: chosen { 16*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun fiq-debugger { 20*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 21*4882a593Smuzhiyun rockchip,serial-id = <2>; 22*4882a593Smuzhiyun rockchip,wake-irq = <0>; 23*4882a593Smuzhiyun /* If enable uart uses irq instead of fiq */ 24*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 25*4882a593Smuzhiyun rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 26*4882a593Smuzhiyun interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>; 27*4882a593Smuzhiyun pinctrl-names = "default"; 28*4882a593Smuzhiyun pinctrl-0 = <&uart2m0_xfer>; 29*4882a593Smuzhiyun status = "okay"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun debug: debug@fd904000 { 33*4882a593Smuzhiyun compatible = "rockchip,debug"; 34*4882a593Smuzhiyun reg = <0x0 0xfd904000 0x0 0x1000>, 35*4882a593Smuzhiyun <0x0 0xfd905000 0x0 0x1000>, 36*4882a593Smuzhiyun <0x0 0xfd906000 0x0 0x1000>, 37*4882a593Smuzhiyun <0x0 0xfd907000 0x0 0x1000>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun cspmu: cspmu@fd90c000 { 41*4882a593Smuzhiyun compatible = "rockchip,cspmu"; 42*4882a593Smuzhiyun reg = <0x0 0xfd90c000 0x0 0x1000>, 43*4882a593Smuzhiyun <0x0 0xfd90d000 0x0 0x1000>, 44*4882a593Smuzhiyun <0x0 0xfd90e000 0x0 0x1000>, 45*4882a593Smuzhiyun <0x0 0xfd90f000 0x0 0x1000>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&reserved_memory { 50*4882a593Smuzhiyun ramoops: ramoops@110000 { 51*4882a593Smuzhiyun compatible = "ramoops"; 52*4882a593Smuzhiyun reg = <0x0 0x110000 0x0 0xf0000>; 53*4882a593Smuzhiyun record-size = <0x20000>; 54*4882a593Smuzhiyun console-size = <0x80000>; 55*4882a593Smuzhiyun ftrace-size = <0x00000>; 56*4882a593Smuzhiyun pmsg-size = <0x50000>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun}; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun&rng { 61*4882a593Smuzhiyun status = "okay"; 62*4882a593Smuzhiyun}; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun&rockchip_suspend { 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun&vop { 69*4882a593Smuzhiyun disable-win-move; 70*4882a593Smuzhiyun}; 71