xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2lvds.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h>
7*4882a593Smuzhiyun#include "rk3568-evb6-ddr3-v10.dtsi"
8*4882a593Smuzhiyun#include "rk3568-android.dtsi"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	vcc33_lcd: vcc33-lcd {
12*4882a593Smuzhiyun		compatible = "regulator-fixed";
13*4882a593Smuzhiyun		regulator-name = "vcc33_lcd";
14*4882a593Smuzhiyun		regulator-boot-on;
15*4882a593Smuzhiyun		regulator-always-on;
16*4882a593Smuzhiyun		gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
17*4882a593Smuzhiyun		enable-active-high;
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	panel {
21*4882a593Smuzhiyun		compatible = "simple-panel";
22*4882a593Smuzhiyun		power-supply = <&vcc33_lcd>;
23*4882a593Smuzhiyun		backlight = <&backlight>;
24*4882a593Smuzhiyun		enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
25*4882a593Smuzhiyun		prepare-delay-ms = <20>;
26*4882a593Smuzhiyun		enable-delay-ms = <20>;
27*4882a593Smuzhiyun		disable-delay-ms = <20>;
28*4882a593Smuzhiyun		unprepare-delay-ms = <20>;
29*4882a593Smuzhiyun		bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA>;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun		display-timings {
32*4882a593Smuzhiyun			native-mode = <&timing0>;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun			timing0: timing0 {
35*4882a593Smuzhiyun				clock-frequency = <66600000>;
36*4882a593Smuzhiyun				hactive = <800>;
37*4882a593Smuzhiyun				vactive = <1280>;
38*4882a593Smuzhiyun				hback-porch = <30>;
39*4882a593Smuzhiyun				hfront-porch = <30>;
40*4882a593Smuzhiyun				vback-porch = <3>;
41*4882a593Smuzhiyun				vfront-porch = <3>;
42*4882a593Smuzhiyun				hsync-len = <4>;
43*4882a593Smuzhiyun				vsync-len = <2>;
44*4882a593Smuzhiyun				hsync-active = <0>;
45*4882a593Smuzhiyun				vsync-active = <0>;
46*4882a593Smuzhiyun				de-active = <0>;
47*4882a593Smuzhiyun				pixelclk-active = <0>;
48*4882a593Smuzhiyun			};
49*4882a593Smuzhiyun		};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun		port {
52*4882a593Smuzhiyun			panel_in_lvds: endpoint {
53*4882a593Smuzhiyun				remote-endpoint = <&lvds_out_panel>;
54*4882a593Smuzhiyun			};
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun&dsi0 {
60*4882a593Smuzhiyun	status = "disabled";
61*4882a593Smuzhiyun};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun&video_phy0 {
64*4882a593Smuzhiyun	status = "disabled";
65*4882a593Smuzhiyun};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun&i2c3 {
68*4882a593Smuzhiyun	clock-frequency = <400000>;
69*4882a593Smuzhiyun	status = "okay";
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	rk628: rk628@50 {
72*4882a593Smuzhiyun		reg = <0x50>;
73*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
74*4882a593Smuzhiyun		interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
75*4882a593Smuzhiyun		enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
76*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
77*4882a593Smuzhiyun		status = "okay";
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun#include <arm/rk628.dtsi>
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun&backlight {
84*4882a593Smuzhiyun	pwms = <&pwm14 0 25000 0>;
85*4882a593Smuzhiyun};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun&pwm14 {
88*4882a593Smuzhiyun	status = "okay";
89*4882a593Smuzhiyun};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun&rk628_lvds {
92*4882a593Smuzhiyun	status = "okay";
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun	ports {
95*4882a593Smuzhiyun		#address-cells = <1>;
96*4882a593Smuzhiyun		#size-cells = <0>;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun		port@0 {
99*4882a593Smuzhiyun			reg = <0>;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun			lvds_in_post_process: endpoint {
102*4882a593Smuzhiyun				remote-endpoint = <&post_process_out_lvds>;
103*4882a593Smuzhiyun			};
104*4882a593Smuzhiyun		};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun		port@1 {
107*4882a593Smuzhiyun			reg = <1>;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun			lvds_out_panel: endpoint {
110*4882a593Smuzhiyun				remote-endpoint = <&panel_in_lvds>;
111*4882a593Smuzhiyun			};
112*4882a593Smuzhiyun		};
113*4882a593Smuzhiyun	};
114*4882a593Smuzhiyun};
115*4882a593Smuzhiyun&rk628_combtxphy {
116*4882a593Smuzhiyun	status = "okay";
117*4882a593Smuzhiyun};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun&rk628_post_process {
120*4882a593Smuzhiyun	pinctrl-names = "default";
121*4882a593Smuzhiyun	pinctrl-0 = <&rk628_vop_pins>;
122*4882a593Smuzhiyun	status = "okay";
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	mode-sync-pol = <0>;
125*4882a593Smuzhiyun	ports {
126*4882a593Smuzhiyun		#address-cells = <1>;
127*4882a593Smuzhiyun		#size-cells = <0>;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun		port@0 {
130*4882a593Smuzhiyun			reg = <0>;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun			post_process_in_rgb: endpoint {
133*4882a593Smuzhiyun				remote-endpoint = <&rgb_out_post_process>;
134*4882a593Smuzhiyun			};
135*4882a593Smuzhiyun		};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun		port@1 {
138*4882a593Smuzhiyun			reg = <1>;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun			post_process_out_lvds: endpoint {
141*4882a593Smuzhiyun				remote-endpoint = <&lvds_in_post_process>;
142*4882a593Smuzhiyun			};
143*4882a593Smuzhiyun		};
144*4882a593Smuzhiyun	};
145*4882a593Smuzhiyun};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun&rgb {
148*4882a593Smuzhiyun	status = "okay";
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	ports {
151*4882a593Smuzhiyun		port@1 {
152*4882a593Smuzhiyun			reg = <1>;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun			rgb_out_post_process: endpoint {
155*4882a593Smuzhiyun				remote-endpoint = <&post_process_in_rgb>;
156*4882a593Smuzhiyun			};
157*4882a593Smuzhiyun		};
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun&rgb_in_vp2 {
162*4882a593Smuzhiyun	status = "okay";
163*4882a593Smuzhiyun};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun&vcc3v3_lcd1_n {
166*4882a593Smuzhiyun	status = "disabled";
167*4882a593Smuzhiyun	gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
168*4882a593Smuzhiyun	enable-active-high;
169*4882a593Smuzhiyun};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun&gmac1 {
172*4882a593Smuzhiyun	status = "disabled";
173*4882a593Smuzhiyun};
174