1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "rk3568-evb6-ddr3-v10.dtsi" 7*4882a593Smuzhiyun#include "rk3568-android.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun&dsi0 { 10*4882a593Smuzhiyun status = "disabled"; 11*4882a593Smuzhiyun}; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun&i2c3 { 14*4882a593Smuzhiyun clock-frequency = <400000>; 15*4882a593Smuzhiyun status = "okay"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun rk628: rk628@50 { 18*4882a593Smuzhiyun reg = <0x50>; 19*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 20*4882a593Smuzhiyun interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>; 21*4882a593Smuzhiyun enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 22*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; 23*4882a593Smuzhiyun status = "okay"; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun#include <arm/rk628.dtsi> 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun&rk628_hdmi { 30*4882a593Smuzhiyun status = "okay"; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun ports { 33*4882a593Smuzhiyun #address-cells = <1>; 34*4882a593Smuzhiyun #size-cells = <0>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun port@0 { 37*4882a593Smuzhiyun reg = <0>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun hdmi_in_post_process: endpoint { 40*4882a593Smuzhiyun remote-endpoint = <&post_process_out_hdmi>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&rk628_post_process { 47*4882a593Smuzhiyun pinctrl-names = "default"; 48*4882a593Smuzhiyun pinctrl-0 = <&rk628_vop_pins>; 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun mode-sync-pol = <0>; 52*4882a593Smuzhiyun ports { 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <0>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun port@0 { 57*4882a593Smuzhiyun reg = <0>; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun post_process_in_rgb: endpoint { 60*4882a593Smuzhiyun remote-endpoint = <&rgb_out_post_process>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun port@1 { 65*4882a593Smuzhiyun reg = <1>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun post_process_out_hdmi: endpoint { 68*4882a593Smuzhiyun remote-endpoint = <&hdmi_in_post_process>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&rgb { 75*4882a593Smuzhiyun status = "okay"; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun ports { 78*4882a593Smuzhiyun port@1 { 79*4882a593Smuzhiyun reg = <1>; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun rgb_out_post_process: endpoint { 82*4882a593Smuzhiyun remote-endpoint = <&post_process_in_rgb>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun&rgb_in_vp2 { 89*4882a593Smuzhiyun status = "okay"; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&vcc3v3_lcd1_n { 93*4882a593Smuzhiyun status = "disabled"; 94*4882a593Smuzhiyun gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 95*4882a593Smuzhiyun enable-active-high; 96*4882a593Smuzhiyun}; 97