1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include "rk3568.dtsi" 12#include "rk3568-evb.dtsi" 13 14/ { 15 model = "Rockchip RK3568 EVB5 DDR4 V10 Board"; 16 compatible = "rockchip,rk3568-evb5-ddr4-v10", "rockchip,rk3568"; 17 18 rk_headset: rk-headset { 19 compatible = "rockchip_headset"; 20 headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; 21 pinctrl-names = "default"; 22 pinctrl-0 = <&hp_det>; 23 }; 24 25 vcc2v5_sys: vcc2v5-ddr { 26 compatible = "regulator-fixed"; 27 regulator-name = "vcc2v5-sys"; 28 regulator-always-on; 29 regulator-boot-on; 30 regulator-min-microvolt = <2500000>; 31 regulator-max-microvolt = <2500000>; 32 vin-supply = <&vcc3v3_sys>; 33 }; 34 35 pcie30_avdd0v9: pcie30-avdd0v9 { 36 compatible = "regulator-fixed"; 37 regulator-name = "pcie30_avdd0v9"; 38 regulator-always-on; 39 regulator-boot-on; 40 regulator-min-microvolt = <900000>; 41 regulator-max-microvolt = <900000>; 42 vin-supply = <&vcc3v3_sys>; 43 }; 44 45 pcie30_avdd1v8: pcie30-avdd1v8 { 46 compatible = "regulator-fixed"; 47 regulator-name = "pcie30_avdd1v8"; 48 regulator-always-on; 49 regulator-boot-on; 50 regulator-min-microvolt = <1800000>; 51 regulator-max-microvolt = <1800000>; 52 vin-supply = <&vcc3v3_sys>; 53 }; 54 55 vcc3v3_pcie: gpio-regulator { 56 compatible = "regulator-fixed"; 57 regulator-name = "vcc3v3_pcie"; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; 61 startup-delay-us = <5000>; 62 vin-supply = <&dc_12v>; 63 }; 64 65 vcc3v3_bu: vcc3v3-bu { 66 compatible = "regulator-fixed"; 67 regulator-name = "vcc3v3_bu"; 68 regulator-always-on; 69 regulator-boot-on; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 vin-supply = <&vcc5v0_sys>; 73 }; 74 75 vcc_camera: vcc-camera-regulator { 76 compatible = "regulator-fixed"; 77 gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&camera_pwr>; 80 regulator-name = "vcc_camera"; 81 enable-active-high; 82 regulator-always-on; 83 regulator-boot-on; 84 }; 85}; 86 87&bt_sound { 88 status = "disabled"; 89 simple-audio-card,cpu { 90 sound-dai = <&i2s2_2ch>; 91 }; 92}; 93 94&combphy0_us { 95 status = "okay"; 96}; 97 98&combphy1_usq { 99 rockchip,sgmii-mac-sel = <0>; 100 status = "okay"; 101}; 102 103&combphy2_psq { 104 status = "okay"; 105}; 106 107&csi2_dphy_hw { 108 status = "okay"; 109}; 110 111&csi2_dphy0 { 112 status = "okay"; 113 114 ports { 115 #address-cells = <1>; 116 #size-cells = <0>; 117 port@0 { 118 reg = <0>; 119 #address-cells = <1>; 120 #size-cells = <0>; 121 122 mipi_in_ucam0: endpoint@1 { 123 reg = <1>; 124 remote-endpoint = <&ucam_out0>; 125 data-lanes = <1 2 3 4>; 126 }; 127 mipi_in_ucam1: endpoint@2 { 128 reg = <2>; 129 remote-endpoint = <&gc8034_out>; 130 data-lanes = <1 2 3 4>; 131 }; 132 mipi_in_ucam2: endpoint@3 { 133 reg = <3>; 134 remote-endpoint = <&ov5695_out>; 135 data-lanes = <1 2>; 136 }; 137 }; 138 port@1 { 139 reg = <1>; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 143 csidphy_out: endpoint@0 { 144 reg = <0>; 145 remote-endpoint = <&isp0_in>; 146 }; 147 }; 148 }; 149}; 150 151/* 152 * video_phy0 needs to be enabled 153 * when dsi0 is enabled 154 */ 155&dsi0 { 156 status = "okay"; 157}; 158 159&dsi0_in_vp0 { 160 status = "disabled"; 161}; 162 163&dsi0_in_vp1 { 164 status = "okay"; 165}; 166 167&dsi0_panel { 168 power-supply = <&vcc3v3_lcd0_n>; 169}; 170 171/* 172 * video_phy1 needs to be enabled 173 * when dsi1 is enabled 174 */ 175&dsi1 { 176 status = "disabled"; 177}; 178 179&dsi1_in_vp0 { 180 status = "disabled"; 181}; 182 183&dsi1_in_vp1 { 184 status = "disabled"; 185}; 186 187&dsi1_panel { 188 power-supply = <&vcc3v3_lcd1_n>; 189}; 190 191&edp { 192 hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; 193 status = "okay"; 194}; 195 196&edp_phy { 197 status = "okay"; 198}; 199 200&edp_in_vp0 { 201 status = "okay"; 202}; 203 204&edp_in_vp1 { 205 status = "disabled"; 206}; 207 208&gmac0 { 209 phy-mode = "sgmii"; 210 211 rockchip,pipegrf = <&pipegrf>; 212 rockchip,xpcs = <&xpcs>; 213 214 snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; 215 snps,reset-active-low; 216 /* Reset time is 20ms, 100ms for rtl8211f */ 217 snps,reset-delays-us = <0 20000 100000>; 218 219 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>; 220 assigned-clock-parents = <&gmac0_xpcsclk>; 221 222 pinctrl-names = "default"; 223 pinctrl-0 = <&gmac0_miim>; 224 225 power-domains = <&power RK3568_PD_PIPE>; 226 phys = <&combphy1_usq PHY_TYPE_SGMII>; 227 phy-handle = <&sgmii_phy>; 228 229 status = "okay"; 230}; 231 232&gmac1 { 233 phy-mode = "rgmii"; 234 clock_in_out = "output"; 235 236 snps,reset-gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; 237 snps,reset-active-low; 238 /* Reset time is 20ms, 100ms for rtl8211f */ 239 snps,reset-delays-us = <0 20000 100000>; 240 241 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 242 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; 243 assigned-clock-rates = <0>, <125000000>; 244 245 pinctrl-names = "default"; 246 pinctrl-0 = <&gmac1m1_miim 247 &gmac1m1_tx_bus2_level3 248 &gmac1m1_rx_bus2 249 &gmac1m1_rgmii_clk_level2 250 &gmac1m1_rgmii_bus_level3>; 251 252 tx_delay = <0x46>; 253 rx_delay = <0x2f>; 254 255 phy-handle = <&rgmii_phy1>; 256 status = "okay"; 257}; 258 259/* 260 * power-supply should switche to vcc3v3_lcd1_n 261 * when mipi panel is connected to dsi1. 262 */ 263>1x { 264 power-supply = <&vcc3v3_lcd0_n>; 265}; 266 267&i2c3 { 268 clock-frequency = <400000>; 269 status = "okay"; 270 271 sii9022: sii9022@39 { 272 compatible = "sil,sii9022"; 273 reg = <0x39>; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&sii902x_hdmi_int>; 276 interrupt-parent = <&gpio4>; 277 interrupts = <RK_PD2 IRQ_TYPE_LEVEL_HIGH>; 278 reset-gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; 279 enable-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; 280 bus-format = <0>; 281 282 ports { 283 #address-cells = <1>; 284 #size-cells = <0>; 285 286 port@0 { 287 reg = <0>; 288 289 sii9022_in_rgb: endpoint { 290 remote-endpoint = <&rgb_out_sii9022>; 291 }; 292 }; 293 }; 294 }; 295}; 296 297&i2c4 { 298 status = "okay"; 299 gc8034: gc8034@37 { 300 compatible = "galaxycore,gc8034"; 301 status = "okay"; 302 reg = <0x37>; 303 clocks = <&cru CLK_CIF_OUT>; 304 clock-names = "xvclk"; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&cif_clk>; 307 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; 308 pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; 309 rockchip,grf = <&grf>; 310 rockchip,camera-module-index = <0>; 311 rockchip,camera-module-facing = "back"; 312 rockchip,camera-module-name = "RK-CMK-8M-2-v1"; 313 rockchip,camera-module-lens-name = "CK8401"; 314 port { 315 gc8034_out: endpoint { 316 remote-endpoint = <&mipi_in_ucam1>; 317 data-lanes = <1 2 3 4>; 318 }; 319 }; 320 }; 321 os04a10: os04a10@36 { 322 compatible = "ovti,os04a10"; 323 reg = <0x36>; 324 clocks = <&cru CLK_CIF_OUT>; 325 clock-names = "xvclk"; 326 power-domains = <&power RK3568_PD_VI>; 327 pinctrl-names = "default"; 328 pinctrl-0 = <&cif_clk>; 329 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; 330 pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; 331 rockchip,camera-module-index = <0>; 332 rockchip,camera-module-facing = "back"; 333 rockchip,camera-module-name = "CMK-OT1607-FV1"; 334 rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; 335 port { 336 ucam_out0: endpoint { 337 remote-endpoint = <&mipi_in_ucam0>; 338 data-lanes = <1 2 3 4>; 339 }; 340 }; 341 }; 342 ov5695: ov5695@36 { 343 status = "okay"; 344 compatible = "ovti,ov5695"; 345 reg = <0x36>; 346 clocks = <&cru CLK_CIF_OUT>; 347 clock-names = "xvclk"; 348 power-domains = <&power RK3568_PD_VI>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&cif_clk>; 351 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; 352 pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; 353 rockchip,camera-module-index = <0>; 354 rockchip,camera-module-facing = "back"; 355 rockchip,camera-module-name = "TongJu"; 356 rockchip,camera-module-lens-name = "CHT842-MD"; 357 port { 358 ov5695_out: endpoint { 359 remote-endpoint = <&mipi_in_ucam2>; 360 data-lanes = <1 2>; 361 }; 362 }; 363 }; 364}; 365 366&i2c5 { 367 status = "disabled"; 368}; 369 370&i2s2_2ch { 371 pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; 372 rockchip,bclk-fs = <32>; 373 status = "disabled"; 374}; 375 376&mdio0 { 377 sgmii_phy: phy@1 { 378 compatible = "ethernet-phy-ieee802.3-c22"; 379 reg = <0x1>; 380 }; 381}; 382 383&mdio1 { 384 rgmii_phy1: phy@0 { 385 compatible = "ethernet-phy-ieee802.3-c22"; 386 reg = <0x0>; 387 }; 388}; 389 390&video_phy0 { 391 status = "okay"; 392}; 393 394&video_phy1 { 395 status = "disabled"; 396}; 397 398&pcie30phy { 399 status = "okay"; 400}; 401 402&pcie3x2 { 403 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; 404 vpcie3v3-supply = <&vcc3v3_pcie>; 405 status = "okay"; 406}; 407 408&pinctrl { 409 cam { 410 camera_pwr: camera-pwr { 411 rockchip,pins = 412 /* camera power en */ 413 <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 414 }; 415 }; 416 headphone { 417 hp_det: hp-det { 418 rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; 419 }; 420 }; 421 422 sii902x { 423 sii902x_hdmi_int: sii902x-hdmi-int { 424 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; 425 }; 426 }; 427 428 wireless-wlan { 429 wifi_host_wake_irq: wifi-host-wake-irq { 430 rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; 431 }; 432 }; 433 434 wireless-bluetooth { 435 uart8_gpios: uart8-gpios { 436 rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 437 }; 438 }; 439}; 440 441&rgb { 442 status = "okay"; 443 444 ports { 445 port@1 { 446 reg = <1>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 450 rgb_out_sii9022: endpoint@0 { 451 reg = <0>; 452 remote-endpoint = <&sii9022_in_rgb>; 453 }; 454 }; 455 }; 456}; 457 458&rgb_in_vp2 { 459 status = "okay"; 460}; 461 462&rkisp { 463 status = "okay"; 464}; 465 466&rkisp_mmu { 467 status = "okay"; 468}; 469 470&rkisp_vir0 { 471 status = "okay"; 472 473 port { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 477 isp0_in: endpoint@0 { 478 reg = <0>; 479 remote-endpoint = <&csidphy_out>; 480 }; 481 }; 482}; 483 484&route_dsi0 { 485 status = "okay"; 486 connect = <&vp1_out_dsi0>; 487}; 488 489&sata2 { 490 status = "okay"; 491}; 492 493&sdmmc2 { 494 max-frequency = <150000000>; 495 no-sd; 496 no-mmc; 497 bus-width = <4>; 498 disable-wp; 499 cap-sd-highspeed; 500 cap-sdio-irq; 501 keep-power-in-suspend; 502 mmc-pwrseq = <&sdio_pwrseq>; 503 non-removable; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; 506 sd-uhs-sdr104; 507 status = "okay"; 508}; 509 510&spdif_8ch { 511 status = "okay"; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&spdifm1_tx>; 514}; 515 516&uart8 { 517 status = "okay"; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; 520}; 521 522&vcc3v3_lcd0_n { 523 gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 524 enable-active-high; 525}; 526 527&vcc3v3_lcd1_n { 528 gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 529 enable-active-high; 530}; 531 532&wireless_wlan { 533 pinctrl-names = "default"; 534 pinctrl-0 = <&wifi_host_wake_irq>; 535 WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; 536}; 537 538&wireless_bluetooth { 539 compatible = "bluetooth-platdata"; 540 clocks = <&rk809 1>; 541 clock-names = "ext_clock"; 542 //wifi-bt-power-toggle; 543 uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 544 pinctrl-names = "default", "rts_gpio"; 545 pinctrl-0 = <&uart8m0_rtsn>; 546 pinctrl-1 = <&uart8_gpios>; 547 BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; 548 BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; 549 BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 550 status = "okay"; 551}; 552