1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rockchip-ddr.h> 7#include <dt-bindings/memory/rk3568-dram.h> 8 9/ { 10 ddr3_params: ddr3-params { 11 /* version information */ 12 version = <0x100>; 13 expanded_version = <IGNORE_THIS>; 14 reserved = <IGNORE_THIS>; 15 /* freq info, freq_0 is final frequency, unit: MHz */ 16 freq_0 = <1056>; 17 freq_1 = <324>; 18 freq_2 = <528>; 19 freq_3 = <780>; 20 freq_4 = <IGNORE_THIS>; 21 freq_5 = <IGNORE_THIS>; 22 /* power save setting */ 23 pd_idle = <13>; 24 sr_idle = <93>; 25 sr_mc_gate_idle = <0>; 26 srpd_lite_idle = <0>; 27 standby_idle = <0>; 28 pd_dis_freq = <1066>; 29 sr_dis_freq = <800>; 30 dram_dll_dis_freq = <300>; 31 phy_dll_dis_freq = <IGNORE_THIS>; 32 /* drv when odt on */ 33 phy_dq_drv_odten = <33>; 34 phy_ca_drv_odten = <33>; 35 phy_clk_drv_odten = <33>; 36 dram_dq_drv_odten = <34>; 37 /* drv when odt off */ 38 phy_dq_drv_odtoff = <33>; 39 phy_ca_drv_odtoff = <33>; 40 phy_clk_drv_odtoff = <33>; 41 dram_dq_drv_odtoff = <34>; 42 /* odt info */ 43 dram_odt = <120>; 44 phy_odt = <167>; 45 phy_odt_puup_en = <1>; 46 phy_odt_pudn_en = <1>; 47 /* odt enable freq */ 48 dram_dq_odt_en_freq = <333>; 49 phy_odt_en_freq = <333>; 50 /* slew rate when odt enable */ 51 phy_dq_sr_odten = <0xf>; 52 phy_ca_sr_odten = <0x3>; 53 phy_clk_sr_odten = <0x0>; 54 /* slew rate when odt disable */ 55 phy_dq_sr_odtoff = <0xf>; 56 phy_ca_sr_odtoff = <0x3>; 57 phy_clk_sr_odtoff = <0x0>; 58 /* ssmod setting*/ 59 ssmod_downspread = <0>; 60 ssmod_div = <0>; 61 ssmod_spread = <0>; 62 /* 2T mode */ 63 mode_2t = <IGNORE_THIS>; 64 /* speed bin */ 65 speed_bin = <DDR3_DEFAULT>; 66 /* dram extended temperature support */ 67 dram_ext_temp = <0>; 68 /* byte map */ 69 byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; 70 /* dq map */ 71 dq_map_cs0_dq_l = <0>; 72 dq_map_cs0_dq_h = <0>; 73 dq_map_cs1_dq_l = <0>; 74 dq_map_cs1_dq_h = <0>; 75 }; 76 77 ddr4_params: ddr4-params { 78 /* version information */ 79 version = <0x100>; 80 expanded_version = <IGNORE_THIS>; 81 reserved = <IGNORE_THIS>; 82 /* freq info, freq_0 is final frequency, unit: MHz */ 83 freq_0 = <1056>; 84 freq_1 = <324>; 85 freq_2 = <528>; 86 freq_3 = <780>; 87 freq_4 = <IGNORE_THIS>; 88 freq_5 = <IGNORE_THIS>; 89 /* power save setting */ 90 pd_idle = <13>; 91 sr_idle = <93>; 92 sr_mc_gate_idle = <0>; 93 srpd_lite_idle = <0>; 94 standby_idle = <0>; 95 pd_dis_freq = <1066>; 96 sr_dis_freq = <800>; 97 dram_dll_dis_freq = <625>; 98 phy_dll_dis_freq = <IGNORE_THIS>; 99 /* drv when odt on */ 100 phy_dq_drv_odten = <37>; 101 phy_ca_drv_odten = <37>; 102 phy_clk_drv_odten = <37>; 103 dram_dq_drv_odten = <34>; 104 /* drv when odt off */ 105 phy_dq_drv_odtoff = <37>; 106 phy_ca_drv_odtoff = <37>; 107 phy_clk_drv_odtoff = <37>; 108 dram_dq_drv_odtoff = <34>; 109 /* odt info */ 110 dram_odt = <120>; 111 phy_odt = <139>; 112 phy_odt_puup_en = <1>; 113 phy_odt_pudn_en = <1>; 114 /* odt enable freq */ 115 dram_dq_odt_en_freq = <500>; 116 phy_odt_en_freq = <500>; 117 /* slew rate when odt enable */ 118 phy_dq_sr_odten = <0xe>; 119 phy_ca_sr_odten = <0x1>; 120 phy_clk_sr_odten = <0x1>; 121 /* slew rate when odt disable */ 122 phy_dq_sr_odtoff = <0xe>; 123 phy_ca_sr_odtoff = <0x1>; 124 phy_clk_sr_odtoff = <0x1>; 125 /* ssmod setting*/ 126 ssmod_downspread = <0>; 127 ssmod_div = <0>; 128 ssmod_spread = <0>; 129 /* 2T mode */ 130 mode_2t = <IGNORE_THIS>; 131 /* speed bin */ 132 speed_bin = <DDR4_DEFAULT>; 133 /* dram extended temperature support */ 134 dram_ext_temp = <0>; 135 /* byte map */ 136 byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; 137 /* dq map */ 138 dq_map_cs0_dq_l = <(((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 0) | \ 139 ((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 8) | \ 140 ((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 16) | \ 141 ((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 24))>; 142 dq_map_cs0_dq_h = <(((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 0) | \ 143 ((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 8) | \ 144 ((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 16) | \ 145 ((3 << 0 | 1 << 2 | 1 << 4 | 3 << 6) << 24))>; 146 dq_map_cs1_dq_l = <(((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 0) | \ 147 ((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 8) | \ 148 ((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 16) | \ 149 ((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 24))>; 150 dq_map_cs1_dq_h = <(((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 0) | \ 151 ((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 8) | \ 152 ((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 16) | \ 153 ((3 << 0 | 1 << 2 | 1 << 4 | 3 << 6) << 24))>; 154 }; 155 156 lpddr3_params: lpddr3-params { 157 /* version information */ 158 version = <0x100>; 159 expanded_version = <IGNORE_THIS>; 160 reserved = <IGNORE_THIS>; 161 /* freq info, freq_0 is final frequency, unit: MHz */ 162 freq_0 = <1056>; 163 freq_1 = <324>; 164 freq_2 = <528>; 165 freq_3 = <780>; 166 freq_4 = <IGNORE_THIS>; 167 freq_5 = <IGNORE_THIS>; 168 /* power save setting */ 169 pd_idle = <13>; 170 sr_idle = <93>; 171 sr_mc_gate_idle = <0>; 172 srpd_lite_idle = <0>; 173 standby_idle = <0>; 174 pd_dis_freq = <1066>; 175 sr_dis_freq = <800>; 176 dram_dll_dis_freq = <IGNORE_THIS>; 177 phy_dll_dis_freq = <IGNORE_THIS>; 178 /* drv when odt on */ 179 phy_dq_drv_odten = <37>; 180 phy_ca_drv_odten = <37>; 181 phy_clk_drv_odten = <39>; 182 dram_dq_drv_odten = <34>; 183 /* drv when odt off */ 184 phy_dq_drv_odtoff = <37>; 185 phy_ca_drv_odtoff = <37>; 186 phy_clk_drv_odtoff = <39>; 187 dram_dq_drv_odtoff = <34>; 188 /* odt info */ 189 dram_odt = <120>; 190 phy_odt = <148>; 191 phy_odt_puup_en = <1>; 192 phy_odt_pudn_en = <1>; 193 /* odt enable freq */ 194 dram_dq_odt_en_freq = <333>; 195 phy_odt_en_freq = <333>; 196 /* slew rate when odt enable */ 197 phy_dq_sr_odten = <0xf>; 198 phy_ca_sr_odten = <0x1>; 199 phy_clk_sr_odten = <0xf>; 200 /* slew rate when odt disable */ 201 phy_dq_sr_odtoff = <0xf>; 202 phy_ca_sr_odtoff = <0x1>; 203 phy_clk_sr_odtoff = <0xf>; 204 /* ssmod setting*/ 205 ssmod_downspread = <0>; 206 ssmod_div = <0>; 207 ssmod_spread = <0>; 208 /* 2T mode */ 209 mode_2t = <IGNORE_THIS>; 210 /* speed bin */ 211 speed_bin = <IGNORE_THIS>; 212 /* dram extended temperature support */ 213 dram_ext_temp = <0>; 214 /* byte map */ 215 byte_map = <((0x2 << 6) | (0x0 << 4) | (0x3 << 2) | (0x1 << 0))>; 216 /* dq map */ 217 dq_map_cs0_dq_l = <0>; 218 dq_map_cs0_dq_h = <0>; 219 dq_map_cs1_dq_l = <0>; 220 dq_map_cs1_dq_h = <0>; 221 }; 222 223 lpddr4_params: lpddr4-params { 224 /* version information */ 225 version = <0x100>; 226 expanded_version = <IGNORE_THIS>; 227 reserved = <IGNORE_THIS>; 228 /* freq info, freq_0 is final frequency, unit: MHz */ 229 freq_0 = <1560>; 230 freq_1 = <324>; 231 freq_2 = <528>; 232 freq_3 = <780>; 233 freq_4 = <IGNORE_THIS>; 234 freq_5 = <IGNORE_THIS>; 235 /* power save setting */ 236 pd_idle = <13>; 237 sr_idle = <93>; 238 sr_mc_gate_idle = <0>; 239 srpd_lite_idle = <0>; 240 standby_idle = <0>; 241 pd_dis_freq = <1066>; 242 sr_dis_freq = <800>; 243 dram_dll_dis_freq = <IGNORE_THIS>; 244 phy_dll_dis_freq = <IGNORE_THIS>; 245 /* drv when odt on */ 246 phy_dq_drv_odten = <30>; 247 phy_ca_drv_odten = <38>; 248 phy_clk_drv_odten = <38>; 249 dram_dq_drv_odten = <40>; 250 /* drv when odt off */ 251 phy_dq_drv_odtoff = <30>; 252 phy_ca_drv_odtoff = <38>; 253 phy_clk_drv_odtoff = <38>; 254 dram_dq_drv_odtoff = <40>; 255 /* odt info */ 256 dram_odt = <80>; 257 phy_odt = <60>; 258 phy_odt_puup_en = <IGNORE_THIS>; 259 phy_odt_pudn_en = <IGNORE_THIS>; 260 /* odt enable freq */ 261 dram_dq_odt_en_freq = <800>; 262 phy_odt_en_freq = <800>; 263 /* slew rate when odt enable */ 264 phy_dq_sr_odten = <0x0>; 265 phy_ca_sr_odten = <0xf>; 266 phy_clk_sr_odten = <0xf>; 267 /* slew rate when odt disable */ 268 phy_dq_sr_odtoff = <0x0>; 269 phy_ca_sr_odtoff = <0xf>; 270 phy_clk_sr_odtoff = <0xf>; 271 /* ssmod setting*/ 272 ssmod_downspread = <0>; 273 ssmod_div = <0>; 274 ssmod_spread = <0>; 275 /* 2T mode */ 276 mode_2t = <IGNORE_THIS>; 277 /* speed bin */ 278 speed_bin = <IGNORE_THIS>; 279 /* dram extended temperature support */ 280 dram_ext_temp = <0>; 281 /* byte map */ 282 byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; 283 /* dq map */ 284 dq_map_cs0_dq_l = <0>; 285 dq_map_cs0_dq_h = <0>; 286 dq_map_cs1_dq_l = <0>; 287 dq_map_cs1_dq_h = <0>; 288 /* lp4 odt info */ 289 lp4_ca_odt = <120>; 290 lp4_drv_pu_cal_odten = <LP4_VDDQ_3>; 291 lp4_drv_pu_cal_odtoff = <LP4_VDDQ_3>; 292 phy_lp4_drv_pulldown_en_odten = <0>; 293 phy_lp4_drv_pulldown_en_odtoff = <0>; 294 /* lp4 odt enable freq */ 295 lp4_ca_odt_en_freq = <800>; 296 /* lp4 cs drv info and ca odt info */ 297 phy_lp4_cs_drv_odten = <0>; 298 phy_lp4_cs_drv_odtoff = <0>; 299 lp4_odte_ck_en = <1>; 300 lp4_odte_cs_en = <1>; 301 lp4_odtd_ca_en = <0>; 302 /* lp4 vref info when odt enable */ 303 phy_lp4_dq_vref_odten = <166>; 304 lp4_dq_vref_odten = <300>; 305 lp4_ca_vref_odten = <380>; 306 /* lp4 vref info when odt disable */ 307 phy_lp4_dq_vref_odtoff = <420>; 308 lp4_dq_vref_odtoff = <420>; 309 lp4_ca_vref_odtoff = <420>; 310 }; 311 312 lpddr4x_params: lpddr4x-params { 313 /* version information */ 314 version = <0x100>; 315 expanded_version = <IGNORE_THIS>; 316 reserved = <IGNORE_THIS>; 317 /* freq info, freq_0 is final frequency, unit: MHz */ 318 freq_0 = <1560>; 319 freq_1 = <324>; 320 freq_2 = <528>; 321 freq_3 = <780>; 322 freq_4 = <IGNORE_THIS>; 323 freq_5 = <IGNORE_THIS>; 324 /* power save setting */ 325 pd_idle = <13>; 326 sr_idle = <93>; 327 sr_mc_gate_idle = <0>; 328 srpd_lite_idle = <0>; 329 standby_idle = <0>; 330 pd_dis_freq = <1066>; 331 sr_dis_freq = <800>; 332 dram_dll_dis_freq = <IGNORE_THIS>; 333 phy_dll_dis_freq = <IGNORE_THIS>; 334 /* drv when odt on */ 335 phy_dq_drv_odten = <29>; 336 phy_ca_drv_odten = <36>; 337 phy_clk_drv_odten = <36>; 338 dram_dq_drv_odten = <40>; 339 /* drv when odt off */ 340 phy_dq_drv_odtoff = <29>; 341 phy_ca_drv_odtoff = <36>; 342 phy_clk_drv_odtoff = <36>; 343 dram_dq_drv_odtoff = <40>; 344 /* odt info */ 345 dram_odt = <80>; 346 phy_odt = <60>; 347 phy_odt_puup_en = <IGNORE_THIS>; 348 phy_odt_pudn_en = <IGNORE_THIS>; 349 /* odt enable freq */ 350 dram_dq_odt_en_freq = <800>; 351 phy_odt_en_freq = <800>; 352 /* slew rate when odt enable */ 353 phy_dq_sr_odten = <0x0>; 354 phy_ca_sr_odten = <0x0>; 355 phy_clk_sr_odten = <0x0>; 356 /* slew rate when odt disable */ 357 phy_dq_sr_odtoff = <0x0>; 358 phy_ca_sr_odtoff = <0x0>; 359 phy_clk_sr_odtoff = <0x0>; 360 /* ssmod setting*/ 361 ssmod_downspread = <0>; 362 ssmod_div = <0>; 363 ssmod_spread = <0>; 364 /* 2T mode */ 365 mode_2t = <IGNORE_THIS>; 366 /* speed bin */ 367 speed_bin = <IGNORE_THIS>; 368 /* dram extended temperature support */ 369 dram_ext_temp = <0>; 370 /* byte map */ 371 byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; 372 /* dq map */ 373 dq_map_cs0_dq_l = <0>; 374 dq_map_cs0_dq_h = <0>; 375 dq_map_cs1_dq_l = <0>; 376 dq_map_cs1_dq_h = <0>; 377 /* lp4 odt info */ 378 lp4_ca_odt = <120>; 379 lp4_drv_pu_cal_odten = <LP4X_VDDQ_0_6>; 380 lp4_drv_pu_cal_odtoff = <LP4X_VDDQ_0_6>; 381 phy_lp4_drv_pulldown_en_odten = <0>; 382 phy_lp4_drv_pulldown_en_odtoff = <0>; 383 /* odt enable freq */ 384 lp4_ca_odt_en_freq = <800>; 385 /* lp4 cs drv info and ca odt info */ 386 phy_lp4_cs_drv_odten = <0>; 387 phy_lp4_cs_drv_odtoff = <0>; 388 lp4_odte_ck_en = <0>; 389 lp4_odte_cs_en = <0>; 390 lp4_odtd_ca_en = <0>; 391 /* lp4 vref info when odt enable */ 392 phy_lp4_dq_vref_odten = <166>; 393 lp4_dq_vref_odten = <228>; 394 lp4_ca_vref_odten = <343>; 395 /* lp4 vref info when odt disable */ 396 phy_lp4_dq_vref_odtoff = <420>; 397 lp4_dq_vref_odtoff = <420>; 398 lp4_ca_vref_odtoff = <343>; 399 }; 400}; 401