1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun rockchip_amp: rockchip-amp { 8*4882a593Smuzhiyun compatible = "rockchip,amp"; 9*4882a593Smuzhiyun clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>, 10*4882a593Smuzhiyun <&cru PCLK_TIMER>, <&cru CLK_TIMER4>, <&cru CLK_TIMER5>; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun pinctrl-names = "default"; 13*4882a593Smuzhiyun pinctrl-0 = <&uart4m1_xfer>; 14*4882a593Smuzhiyun status = "okay"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun amp_cpus: amp-cpus { 17*4882a593Smuzhiyun amp-cpu2 { 18*4882a593Smuzhiyun id = <0x0 0x200>; 19*4882a593Smuzhiyun entry = <0x0 0x3800000>; 20*4882a593Smuzhiyun mode = <0>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun amp-cpu3 { 24*4882a593Smuzhiyun id = <0x0 0x300>; 25*4882a593Smuzhiyun entry = <0x0 0x5800000>; 26*4882a593Smuzhiyun mode = <0>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun}; 31