1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 11*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h> 12*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h> 13*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 14*4882a593Smuzhiyun#include "rk3566.dtsi" 15*4882a593Smuzhiyun#include "rk3568-android.dtsi" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/ { 18*4882a593Smuzhiyun model = "Rockchip RK3566 RK817 TABLET RKG11 LP4 Board"; 19*4882a593Smuzhiyun compatible = "rockchip,rk3566-rk817-tablet-rkg11", "rockchip,rk3566"; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun adc_keys: adc-keys { 22*4882a593Smuzhiyun compatible = "adc-keys"; 23*4882a593Smuzhiyun io-channels = <&saradc 0>; 24*4882a593Smuzhiyun io-channel-names = "buttons"; 25*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 26*4882a593Smuzhiyun poll-interval = <100>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun vol-up-key { 29*4882a593Smuzhiyun label = "volume up"; 30*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 31*4882a593Smuzhiyun press-threshold-microvolt = <1750>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun vol-down-key { 35*4882a593Smuzhiyun label = "volume down"; 36*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 37*4882a593Smuzhiyun press-threshold-microvolt = <297500>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun backlight: backlight { 42*4882a593Smuzhiyun compatible = "pwm-backlight"; 43*4882a593Smuzhiyun pwms = <&pwm4 0 25000 0>; 44*4882a593Smuzhiyun brightness-levels = < 45*4882a593Smuzhiyun 0 20 20 21 21 22 22 23 46*4882a593Smuzhiyun 23 24 24 25 25 26 26 27 47*4882a593Smuzhiyun 27 28 28 29 29 30 30 31 48*4882a593Smuzhiyun 31 32 32 33 33 34 34 35 49*4882a593Smuzhiyun 35 36 36 37 37 38 38 39 50*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 51*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 52*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 53*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 54*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 55*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 56*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 57*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 58*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 59*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 60*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 61*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 62*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 63*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 64*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 65*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 66*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 67*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 68*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 69*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 70*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 71*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 72*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 73*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 74*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 75*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 76*4882a593Smuzhiyun 248 249 250 251 252 253 254 255 77*4882a593Smuzhiyun >; 78*4882a593Smuzhiyun default-brightness-level = <200>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun charge-animation { 82*4882a593Smuzhiyun compatible = "rockchip,uboot-charge"; 83*4882a593Smuzhiyun rockchip,uboot-charge-on = <1>; 84*4882a593Smuzhiyun rockchip,android-charge-on = <0>; 85*4882a593Smuzhiyun rockchip,uboot-low-power-voltage = <3350>; 86*4882a593Smuzhiyun rockchip,screen-on-voltage = <3400>; 87*4882a593Smuzhiyun status = "okay"; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun es7210_sound: es7210-sound { 91*4882a593Smuzhiyun status = "okay"; 92*4882a593Smuzhiyun compatible = "simple-audio-card"; 93*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 94*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 95*4882a593Smuzhiyun simple-audio-card,name = "rockchip,es7210"; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun simple-audio-card,cpu { 98*4882a593Smuzhiyun sound-dai = <&i2s1_8ch>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun simple-audio-card,codec { 101*4882a593Smuzhiyun sound-dai = <&es7210>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun vccsys: vccsys { 106*4882a593Smuzhiyun compatible = "regulator-fixed"; 107*4882a593Smuzhiyun regulator-name = "vcc3v8_sys"; 108*4882a593Smuzhiyun regulator-always-on; 109*4882a593Smuzhiyun regulator-boot-on; 110*4882a593Smuzhiyun regulator-min-microvolt = <3800000>; 111*4882a593Smuzhiyun regulator-max-microvolt = <3800000>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun vcc3v3_lcd0_n: vcc3v3-lcd0-n { 115*4882a593Smuzhiyun compatible = "regulator-fixed"; 116*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd0_n"; 117*4882a593Smuzhiyun gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 118*4882a593Smuzhiyun enable-active-high; 119*4882a593Smuzhiyun regulator-boot-on; 120*4882a593Smuzhiyun regulator-state-mem { 121*4882a593Smuzhiyun regulator-off-in-suspend; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun rk817-sound { 126*4882a593Smuzhiyun compatible = "simple-audio-card"; 127*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 128*4882a593Smuzhiyun simple-audio-card,name = "rockchip,rk817-codec"; 129*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun simple-audio-card,cpu { 132*4882a593Smuzhiyun sound-dai = <&i2s3_2ch>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun simple-audio-card,codec { 135*4882a593Smuzhiyun sound-dai = <&rk817_codec>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun rk_headset: rk-headset { 140*4882a593Smuzhiyun compatible = "rockchip_headset"; 141*4882a593Smuzhiyun headset_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; 142*4882a593Smuzhiyun pinctrl-names = "default"; 143*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 144*4882a593Smuzhiyun io-channels = <&saradc 2>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 148*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 149*4882a593Smuzhiyun clocks = <&rk817 1>; 150*4882a593Smuzhiyun clock-names = "ext_clock"; 151*4882a593Smuzhiyun pinctrl-names = "default"; 152*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* 155*4882a593Smuzhiyun * On the module itself this is one of these (depending 156*4882a593Smuzhiyun * on the actual card populated): 157*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 158*4882a593Smuzhiyun * - PDN (power down when low) 159*4882a593Smuzhiyun */ 160*4882a593Smuzhiyun post-power-on-delay-ms = <200>; 161*4882a593Smuzhiyun reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>, 162*4882a593Smuzhiyun <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun wireless-wlan { 166*4882a593Smuzhiyun compatible = "wlan-platdata"; 167*4882a593Smuzhiyun rockchip,grf = <&grf>; 168*4882a593Smuzhiyun wifi_chip_type = "rtl8821cs"; 169*4882a593Smuzhiyun pinctrl-names = "default"; 170*4882a593Smuzhiyun pinctrl-0 = <&wifi_host_wake_irq>; 171*4882a593Smuzhiyun WIFI,vbat_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 172*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; 173*4882a593Smuzhiyun WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; 174*4882a593Smuzhiyun status = "okay"; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun wireless-bluetooth { 178*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 179*4882a593Smuzhiyun clocks = <&rk817 1>; 180*4882a593Smuzhiyun clock-names = "ext_clock"; 181*4882a593Smuzhiyun //wifi-bt-power-toggle; 182*4882a593Smuzhiyun uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; 183*4882a593Smuzhiyun pinctrl-names = "default", "rts_gpio"; 184*4882a593Smuzhiyun pinctrl-0 = <&uart1m0_rtsn>; 185*4882a593Smuzhiyun pinctrl-1 = <&uart1_gpios>; 186*4882a593Smuzhiyun BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; 187*4882a593Smuzhiyun BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; 188*4882a593Smuzhiyun BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; 189*4882a593Smuzhiyun status = "okay"; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun hall_sensor: hall-mh248 { 193*4882a593Smuzhiyun compatible = "hall-mh248"; 194*4882a593Smuzhiyun pinctrl-names = "default"; 195*4882a593Smuzhiyun pinctrl-0 = <&mh248_irq_gpio>; 196*4882a593Smuzhiyun irq-gpio = <&gpio0 RK_PC6 IRQ_TYPE_EDGE_BOTH>; 197*4882a593Smuzhiyun hall-active = <1>; 198*4882a593Smuzhiyun status = "okay"; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun vibrator { 202*4882a593Smuzhiyun compatible = "rk-vibrator-gpio"; 203*4882a593Smuzhiyun vibrator-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; 204*4882a593Smuzhiyun status = "okay"; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun reserved-memory { 208*4882a593Smuzhiyun #address-cells = <2>; 209*4882a593Smuzhiyun #size-cells = <2>; 210*4882a593Smuzhiyun ranges; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun rknpu_reserved: rknpu { 213*4882a593Smuzhiyun compatible = "shared-dma-pool"; 214*4882a593Smuzhiyun inactive; 215*4882a593Smuzhiyun reusable; 216*4882a593Smuzhiyun size = <0x0 0x20000000>; 217*4882a593Smuzhiyun alignment = <0x0 0x1000>; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun}; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun&cpu0 { 223*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 224*4882a593Smuzhiyun}; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun&csi2_dphy_hw { 227*4882a593Smuzhiyun status = "okay"; 228*4882a593Smuzhiyun}; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun&csi2_dphy0 { 231*4882a593Smuzhiyun status = "okay"; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun ports { 234*4882a593Smuzhiyun #address-cells = <1>; 235*4882a593Smuzhiyun #size-cells = <0>; 236*4882a593Smuzhiyun port@0 { 237*4882a593Smuzhiyun reg = <0>; 238*4882a593Smuzhiyun #address-cells = <1>; 239*4882a593Smuzhiyun #size-cells = <0>; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun mipi_in_ucam0: endpoint@0 { 242*4882a593Smuzhiyun reg = <0>; 243*4882a593Smuzhiyun remote-endpoint = <&gc5035_out>; 244*4882a593Smuzhiyun data-lanes = <1 2>; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun mipi_in_ucam1: endpoint@1 { 247*4882a593Smuzhiyun reg = <1>; 248*4882a593Smuzhiyun remote-endpoint = <&ov8858_out>; 249*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun port@1 { 253*4882a593Smuzhiyun reg = <1>; 254*4882a593Smuzhiyun #address-cells = <1>; 255*4882a593Smuzhiyun #size-cells = <0>; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun csidphy0_out: endpoint@0 { 258*4882a593Smuzhiyun reg = <0>; 259*4882a593Smuzhiyun remote-endpoint = <&isp0_in>; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun}; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun&dfi { 266*4882a593Smuzhiyun status = "okay"; 267*4882a593Smuzhiyun}; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun&dmc { 270*4882a593Smuzhiyun center-supply = <&vdd_logic>; 271*4882a593Smuzhiyun status = "okay"; 272*4882a593Smuzhiyun}; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun&dsi0 { 275*4882a593Smuzhiyun status = "okay"; 276*4882a593Smuzhiyun rockchip,dual-channel = <&dsi1>; 277*4882a593Smuzhiyun panel@0 { 278*4882a593Smuzhiyun status = "okay"; 279*4882a593Smuzhiyun compatible = "simple-panel-dsi"; 280*4882a593Smuzhiyun reg = <0>; 281*4882a593Smuzhiyun backlight = <&backlight>; 282*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd0_n>; 283*4882a593Smuzhiyun //vsp-supply = <&outp>; 284*4882a593Smuzhiyun //vsn-supply = <&outn>; 285*4882a593Smuzhiyun //enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 286*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; 287*4882a593Smuzhiyun pinctrl-names = "default"; 288*4882a593Smuzhiyun pinctrl-0 = <&lcd_enable_gpio>, <&lcd_rst_gpio>, <&lcd_panel_vsp>, <&lcd_panel_vsn>; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun prepare-delay-ms = <60>; 291*4882a593Smuzhiyun unprepare-delay-ms = <60>; 292*4882a593Smuzhiyun enable-delay-ms = <60>; 293*4882a593Smuzhiyun disable-delay-ms = <60>; 294*4882a593Smuzhiyun init-delay-ms = <60>; 295*4882a593Smuzhiyun reset-delay-ms = <60>; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 298*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 299*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 300*4882a593Smuzhiyun dsi,lanes = <8>; 301*4882a593Smuzhiyun panel-init-sequence = [ 302*4882a593Smuzhiyun 05 20 01 11 303*4882a593Smuzhiyun 05 96 01 29 304*4882a593Smuzhiyun ]; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun panel-exit-sequence = [ 307*4882a593Smuzhiyun 05 05 01 28 308*4882a593Smuzhiyun 05 78 01 10 309*4882a593Smuzhiyun ]; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun display-timings { 312*4882a593Smuzhiyun native-mode = <&timing0>; 313*4882a593Smuzhiyun timing0: timing0 { 314*4882a593Smuzhiyun clock-frequency = <255000000>; 315*4882a593Smuzhiyun hactive = <1600>; 316*4882a593Smuzhiyun vactive = <2176>; 317*4882a593Smuzhiyun hsync-len = <14>; //20, 50 318*4882a593Smuzhiyun hback-porch = <25>; //50, 56 319*4882a593Smuzhiyun hfront-porch = <25>;//50, 30 320*4882a593Smuzhiyun vsync-len = <8>; 321*4882a593Smuzhiyun vback-porch = <73>; 322*4882a593Smuzhiyun vfront-porch = <250>; 323*4882a593Smuzhiyun hsync-active = <0>; 324*4882a593Smuzhiyun vsync-active = <0>; 325*4882a593Smuzhiyun de-active = <0>; 326*4882a593Smuzhiyun pixelclk-active = <1>; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun ports { 331*4882a593Smuzhiyun #address-cells = <1>; 332*4882a593Smuzhiyun #size-cells = <0>; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun port@0 { 335*4882a593Smuzhiyun reg = <0>; 336*4882a593Smuzhiyun panel_in_dsi: endpoint { 337*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun ports { 344*4882a593Smuzhiyun #address-cells = <1>; 345*4882a593Smuzhiyun #size-cells = <0>; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun port@1 { 348*4882a593Smuzhiyun reg = <1>; 349*4882a593Smuzhiyun dsi_out_panel: endpoint { 350*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun}; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun&dsi1 { 358*4882a593Smuzhiyun status = "okay"; 359*4882a593Smuzhiyun}; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun&dsi0_in_vp0 { 362*4882a593Smuzhiyun status = "okay"; 363*4882a593Smuzhiyun}; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun&dsi0_in_vp1 { 366*4882a593Smuzhiyun status = "disabled"; 367*4882a593Smuzhiyun}; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun&gpu { 370*4882a593Smuzhiyun mali-supply = <&vdd_gpu>; 371*4882a593Smuzhiyun status = "okay"; 372*4882a593Smuzhiyun}; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun&i2c0 { 376*4882a593Smuzhiyun status = "okay"; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun vdd_cpu: tcs4525@1c { 379*4882a593Smuzhiyun compatible = "tcs,tcs4525"; 380*4882a593Smuzhiyun reg = <0x1c>; 381*4882a593Smuzhiyun vin-supply = <&vccsys>; 382*4882a593Smuzhiyun regulator-compatible = "fan53555-reg"; 383*4882a593Smuzhiyun regulator-name = "vdd_cpu"; 384*4882a593Smuzhiyun regulator-min-microvolt = <712500>; 385*4882a593Smuzhiyun regulator-max-microvolt = <1390000>; 386*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 387*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 388*4882a593Smuzhiyun fcs,suspend-voltage-selector = <1>; 389*4882a593Smuzhiyun regulator-boot-on; 390*4882a593Smuzhiyun regulator-always-on; 391*4882a593Smuzhiyun regulator-state-mem { 392*4882a593Smuzhiyun regulator-off-in-suspend; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun rk817: pmic@20 { 397*4882a593Smuzhiyun compatible = "rockchip,rk817"; 398*4882a593Smuzhiyun reg = <0x20>; 399*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 400*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 403*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 404*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 405*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 406*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 407*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; 408*4882a593Smuzhiyun rockchip,system-power-controller; 409*4882a593Smuzhiyun wakeup-source; 410*4882a593Smuzhiyun #clock-cells = <1>; 411*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 412*4882a593Smuzhiyun //fb-inner-reg-idxs = <2>; 413*4882a593Smuzhiyun /* 1: rst regs (default in codes), 0: rst the pmic */ 414*4882a593Smuzhiyun pmic-reset-func = <0>; 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun vcc1-supply = <&vccsys>; 417*4882a593Smuzhiyun vcc2-supply = <&vccsys>; 418*4882a593Smuzhiyun vcc3-supply = <&vccsys>; 419*4882a593Smuzhiyun vcc4-supply = <&vccsys>; 420*4882a593Smuzhiyun vcc5-supply = <&vccsys>; 421*4882a593Smuzhiyun vcc6-supply = <&vccsys>; 422*4882a593Smuzhiyun vcc7-supply = <&vccsys>; 423*4882a593Smuzhiyun vcc8-supply = <&vccsys>; 424*4882a593Smuzhiyun vcc9-supply = <&dcdc_boost>; 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun pwrkey { 427*4882a593Smuzhiyun status = "okay"; 428*4882a593Smuzhiyun }; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 431*4882a593Smuzhiyun gpio-controller; 432*4882a593Smuzhiyun #gpio-cells = <2>; 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 435*4882a593Smuzhiyun pins = "gpio_slp"; 436*4882a593Smuzhiyun function = "pin_fun0"; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 440*4882a593Smuzhiyun pins = "gpio_slp"; 441*4882a593Smuzhiyun function = "pin_fun1"; 442*4882a593Smuzhiyun }; 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 445*4882a593Smuzhiyun pins = "gpio_slp"; 446*4882a593Smuzhiyun function = "pin_fun2"; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 450*4882a593Smuzhiyun pins = "gpio_slp"; 451*4882a593Smuzhiyun function = "pin_fun3"; 452*4882a593Smuzhiyun }; 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun regulators { 456*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 457*4882a593Smuzhiyun regulator-always-on; 458*4882a593Smuzhiyun regulator-boot-on; 459*4882a593Smuzhiyun regulator-min-microvolt = <500000>; 460*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 461*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 462*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 463*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 464*4882a593Smuzhiyun regulator-name = "vdd_logic"; 465*4882a593Smuzhiyun regulator-state-mem { 466*4882a593Smuzhiyun regulator-off-in-suspend; 467*4882a593Smuzhiyun regulator-suspend-microvolt = <900000>; 468*4882a593Smuzhiyun }; 469*4882a593Smuzhiyun }; 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun vdd_gpu: DCDC_REG2 { 472*4882a593Smuzhiyun regulator-always-on; 473*4882a593Smuzhiyun regulator-boot-on; 474*4882a593Smuzhiyun regulator-min-microvolt = <500000>; 475*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 476*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 477*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 478*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 479*4882a593Smuzhiyun regulator-name = "vdd_gpu"; 480*4882a593Smuzhiyun regulator-state-mem { 481*4882a593Smuzhiyun regulator-off-in-suspend; 482*4882a593Smuzhiyun }; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun 485*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 486*4882a593Smuzhiyun regulator-always-on; 487*4882a593Smuzhiyun regulator-boot-on; 488*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 489*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 490*4882a593Smuzhiyun regulator-state-mem { 491*4882a593Smuzhiyun regulator-on-in-suspend; 492*4882a593Smuzhiyun }; 493*4882a593Smuzhiyun }; 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun vcc_3v3: DCDC_REG4 { 496*4882a593Smuzhiyun regulator-always-on; 497*4882a593Smuzhiyun regulator-boot-on; 498*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 499*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 500*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 501*4882a593Smuzhiyun regulator-name = "vcc_3v3"; 502*4882a593Smuzhiyun regulator-state-mem { 503*4882a593Smuzhiyun regulator-off-in-suspend; 504*4882a593Smuzhiyun }; 505*4882a593Smuzhiyun }; 506*4882a593Smuzhiyun 507*4882a593Smuzhiyun vcca1v8_pmu: LDO_REG1 { 508*4882a593Smuzhiyun regulator-always-on; 509*4882a593Smuzhiyun regulator-boot-on; 510*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 511*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 512*4882a593Smuzhiyun regulator-name = "vcca1v8_pmu"; 513*4882a593Smuzhiyun regulator-state-mem { 514*4882a593Smuzhiyun regulator-on-in-suspend; 515*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 516*4882a593Smuzhiyun }; 517*4882a593Smuzhiyun }; 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun vdda_0v9: LDO_REG2 { 520*4882a593Smuzhiyun regulator-always-on; 521*4882a593Smuzhiyun regulator-boot-on; 522*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 523*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 524*4882a593Smuzhiyun regulator-name = "vdda_0v9"; 525*4882a593Smuzhiyun regulator-state-mem { 526*4882a593Smuzhiyun regulator-off-in-suspend; 527*4882a593Smuzhiyun }; 528*4882a593Smuzhiyun }; 529*4882a593Smuzhiyun 530*4882a593Smuzhiyun vdda0v9_pmu: LDO_REG3 { 531*4882a593Smuzhiyun regulator-always-on; 532*4882a593Smuzhiyun regulator-boot-on; 533*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 534*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 535*4882a593Smuzhiyun regulator-name = "vdda0v9_pmu"; 536*4882a593Smuzhiyun regulator-state-mem { 537*4882a593Smuzhiyun regulator-on-in-suspend; 538*4882a593Smuzhiyun regulator-suspend-microvolt = <900000>; 539*4882a593Smuzhiyun }; 540*4882a593Smuzhiyun }; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun vccio_acodec: LDO_REG4 { 543*4882a593Smuzhiyun regulator-always-on; 544*4882a593Smuzhiyun regulator-boot-on; 545*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 546*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 547*4882a593Smuzhiyun regulator-name = "vccio_acodec"; 548*4882a593Smuzhiyun regulator-state-mem { 549*4882a593Smuzhiyun regulator-off-in-suspend; 550*4882a593Smuzhiyun }; 551*4882a593Smuzhiyun }; 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 554*4882a593Smuzhiyun regulator-always-on; 555*4882a593Smuzhiyun regulator-boot-on; 556*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 557*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 558*4882a593Smuzhiyun regulator-name = "vccio_sd"; 559*4882a593Smuzhiyun regulator-state-mem { 560*4882a593Smuzhiyun regulator-off-in-suspend; 561*4882a593Smuzhiyun }; 562*4882a593Smuzhiyun }; 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun vcc3v3_pmu: LDO_REG6 { 565*4882a593Smuzhiyun regulator-always-on; 566*4882a593Smuzhiyun regulator-boot-on; 567*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 568*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 569*4882a593Smuzhiyun regulator-name = "vcc3v3_pmu"; 570*4882a593Smuzhiyun regulator-state-mem { 571*4882a593Smuzhiyun regulator-on-in-suspend; 572*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 573*4882a593Smuzhiyun }; 574*4882a593Smuzhiyun }; 575*4882a593Smuzhiyun 576*4882a593Smuzhiyun vcc_1v8: LDO_REG7 { 577*4882a593Smuzhiyun regulator-always-on; 578*4882a593Smuzhiyun regulator-boot-on; 579*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 580*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 581*4882a593Smuzhiyun regulator-name = "vcc_1v8"; 582*4882a593Smuzhiyun regulator-state-mem { 583*4882a593Smuzhiyun regulator-off-in-suspend; 584*4882a593Smuzhiyun }; 585*4882a593Smuzhiyun }; 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun vcc1v8_dvp: LDO_REG8 { 588*4882a593Smuzhiyun regulator-always-on; 589*4882a593Smuzhiyun regulator-boot-on; 590*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 591*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 592*4882a593Smuzhiyun regulator-name = "vcc1v8_dvp"; 593*4882a593Smuzhiyun regulator-state-mem { 594*4882a593Smuzhiyun regulator-off-in-suspend; 595*4882a593Smuzhiyun }; 596*4882a593Smuzhiyun }; 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun vcc2v8_dvp: LDO_REG9 { 599*4882a593Smuzhiyun regulator-always-on; 600*4882a593Smuzhiyun regulator-boot-on; 601*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 602*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 603*4882a593Smuzhiyun regulator-name = "vcc2v8_dvp"; 604*4882a593Smuzhiyun regulator-state-mem { 605*4882a593Smuzhiyun regulator-off-in-suspend; 606*4882a593Smuzhiyun }; 607*4882a593Smuzhiyun }; 608*4882a593Smuzhiyun 609*4882a593Smuzhiyun dcdc_boost: BOOST { 610*4882a593Smuzhiyun regulator-always-on; 611*4882a593Smuzhiyun regulator-boot-on; 612*4882a593Smuzhiyun regulator-min-microvolt = <4700000>; 613*4882a593Smuzhiyun regulator-max-microvolt = <5400000>; 614*4882a593Smuzhiyun regulator-name = "boost"; 615*4882a593Smuzhiyun regulator-state-mem { 616*4882a593Smuzhiyun regulator-off-in-suspend; 617*4882a593Smuzhiyun }; 618*4882a593Smuzhiyun }; 619*4882a593Smuzhiyun 620*4882a593Smuzhiyun otg_switch: OTG_SWITCH { 621*4882a593Smuzhiyun regulator-name = "otg_switch"; 622*4882a593Smuzhiyun regulator-state-mem { 623*4882a593Smuzhiyun regulator-off-in-suspend; 624*4882a593Smuzhiyun }; 625*4882a593Smuzhiyun }; 626*4882a593Smuzhiyun }; 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun battery { 629*4882a593Smuzhiyun compatible = "rk817,battery"; 630*4882a593Smuzhiyun ocv_table = <3510 3679 3691 3714 3738 3759 3776 631*4882a593Smuzhiyun 3795 3811 3834 3852 3881 3942 3976 632*4882a593Smuzhiyun 4012 4075 4114 4177 4232 4277 4351>; 633*4882a593Smuzhiyun design_capacity = <7916>; 634*4882a593Smuzhiyun design_qmax = <8708>; 635*4882a593Smuzhiyun bat_res = <110>; 636*4882a593Smuzhiyun sleep_enter_current = <150>; 637*4882a593Smuzhiyun sleep_exit_current = <180>; 638*4882a593Smuzhiyun sleep_filter_current = <100>; 639*4882a593Smuzhiyun power_off_thresd = <3450>; 640*4882a593Smuzhiyun zero_algorithm_vol = <3850>; 641*4882a593Smuzhiyun max_soc_offset = <60>; 642*4882a593Smuzhiyun monitor_sec = <5>; 643*4882a593Smuzhiyun sample_res = <10>; 644*4882a593Smuzhiyun virtual_power = <0>; 645*4882a593Smuzhiyun }; 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun charger { 648*4882a593Smuzhiyun compatible = "rk817,charger"; 649*4882a593Smuzhiyun min_input_voltage = <4500>; 650*4882a593Smuzhiyun max_input_current = <1500>; 651*4882a593Smuzhiyun max_chrg_current = <2000>; 652*4882a593Smuzhiyun max_chrg_voltage = <4300>; 653*4882a593Smuzhiyun chrg_term_mode = <0>; 654*4882a593Smuzhiyun chrg_finish_cur = <300>; 655*4882a593Smuzhiyun virtual_power = <0>; 656*4882a593Smuzhiyun dc_det_adc = <0>; 657*4882a593Smuzhiyun extcon = <&usb2phy0>; 658*4882a593Smuzhiyun }; 659*4882a593Smuzhiyun 660*4882a593Smuzhiyun rk817_codec: codec { 661*4882a593Smuzhiyun #sound-dai-cells = <0>; 662*4882a593Smuzhiyun compatible = "rockchip,rk817-codec"; 663*4882a593Smuzhiyun clocks = <&cru I2S3_MCLKOUT>; 664*4882a593Smuzhiyun clock-names = "mclk"; 665*4882a593Smuzhiyun assigned-clocks = <&cru I2S3_MCLKOUT>, <&cru I2S3_MCLK_IOE>; 666*4882a593Smuzhiyun assigned-clock-rates = <12288000>; 667*4882a593Smuzhiyun assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>, <&cru I2S3_MCLKOUT>; 668*4882a593Smuzhiyun pinctrl-names = "default"; 669*4882a593Smuzhiyun pinctrl-0 = <&i2s3m1_mclk>; 670*4882a593Smuzhiyun hp-volume = <20>; 671*4882a593Smuzhiyun spk-volume = <3>; 672*4882a593Smuzhiyun mic-in-differential; 673*4882a593Smuzhiyun use-ext-amplifier; 674*4882a593Smuzhiyun //out-l2spk-r2hp; 675*4882a593Smuzhiyun spk-ctl-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; 676*4882a593Smuzhiyun status = "okay"; 677*4882a593Smuzhiyun }; 678*4882a593Smuzhiyun }; 679*4882a593Smuzhiyun}; 680*4882a593Smuzhiyun 681*4882a593Smuzhiyun&i2c1 { 682*4882a593Smuzhiyun status = "okay"; 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun dio5632@3e { 685*4882a593Smuzhiyun compatible = "DIO5632"; 686*4882a593Smuzhiyun reg = <0x3e>; 687*4882a593Smuzhiyun status = "disabled"; 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun outp: outp@3e { 690*4882a593Smuzhiyun regulator-name = "LCD_VSP"; 691*4882a593Smuzhiyun vin-supply = <&vccsys>; 692*4882a593Smuzhiyun enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 693*4882a593Smuzhiyun }; 694*4882a593Smuzhiyun 695*4882a593Smuzhiyun outn: outn@3e { 696*4882a593Smuzhiyun regulator-name = "LCD_VSN"; 697*4882a593Smuzhiyun vin-supply = <&vccsys>; 698*4882a593Smuzhiyun enable-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; 699*4882a593Smuzhiyun }; 700*4882a593Smuzhiyun }; 701*4882a593Smuzhiyun 702*4882a593Smuzhiyun es7210: es7210@43 { 703*4882a593Smuzhiyun #sound-dai-cells = <0>; 704*4882a593Smuzhiyun compatible = "ES7210_MicArray_0"; 705*4882a593Smuzhiyun reg = <0x43>; 706*4882a593Smuzhiyun clocks = <&cru I2S1_MCLKOUT_RX>; 707*4882a593Smuzhiyun clock-names = "mclk"; 708*4882a593Smuzhiyun assigned-clocks = <&cru I2S1_MCLKOUT_RX>; 709*4882a593Smuzhiyun assigned-clock-parents = <&cru CLK_I2S1_8CH_RX>; 710*4882a593Smuzhiyun pinctrl-names = "default"; 711*4882a593Smuzhiyun pinctrl-0 = <&i2s1m0_mclk>; 712*4882a593Smuzhiyun }; 713*4882a593Smuzhiyun}; 714*4882a593Smuzhiyun 715*4882a593Smuzhiyun&i2c2 { 716*4882a593Smuzhiyun status = "okay"; 717*4882a593Smuzhiyun pinctrl-names = "default"; 718*4882a593Smuzhiyun pinctrl-0 = <&i2c2m1_xfer>; 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun gc5035: gc5035@37 { 721*4882a593Smuzhiyun compatible = "galaxycore,gc5035"; 722*4882a593Smuzhiyun status = "okay"; 723*4882a593Smuzhiyun reg = <0x37>; 724*4882a593Smuzhiyun clocks = <&cru CLK_CIF_OUT>; 725*4882a593Smuzhiyun clock-names = "xvclk"; 726*4882a593Smuzhiyun power-domains = <&power RK3568_PD_VI>; 727*4882a593Smuzhiyun pinctrl-names = "default"; 728*4882a593Smuzhiyun pinctrl-0 = <&cif_clk>; 729*4882a593Smuzhiyun 730*4882a593Smuzhiyun //reset pin control by hardware,used this pin switch to mipi input 731*4882a593Smuzhiyun //0->FRONT camera, 1->REAR camera 732*4882a593Smuzhiyun reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; 733*4882a593Smuzhiyun pwdn-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; 734*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 735*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 736*4882a593Smuzhiyun rockchip,camera-module-name = "XHG-RKX11F-V5"; 737*4882a593Smuzhiyun rockchip,camera-module-lens-name = "HR232H65"; 738*4882a593Smuzhiyun port { 739*4882a593Smuzhiyun gc5035_out: endpoint { 740*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam0>; 741*4882a593Smuzhiyun data-lanes = <1 2>; 742*4882a593Smuzhiyun }; 743*4882a593Smuzhiyun }; 744*4882a593Smuzhiyun }; 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun ov8858: ov8858@36 { 747*4882a593Smuzhiyun status = "okay"; 748*4882a593Smuzhiyun compatible = "ovti,ov8858"; 749*4882a593Smuzhiyun reg = <0x36>; 750*4882a593Smuzhiyun clocks = <&cru CLK_CAM0_OUT>; 751*4882a593Smuzhiyun clock-names = "xvclk"; 752*4882a593Smuzhiyun power-domains = <&power RK3568_PD_VI>; 753*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; 754*4882a593Smuzhiyun pinctrl-0 = <&cam_clkout0>; 755*4882a593Smuzhiyun pinctrl-1 = <&cam_sleep>; 756*4882a593Smuzhiyun //reset pin control by hardware,used this pin switch to mipi input 757*4882a593Smuzhiyun //0->FRONT camera, 1->REAR camera 758*4882a593Smuzhiyun reset-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; 759*4882a593Smuzhiyun pwdn-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; 760*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 761*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 762*4882a593Smuzhiyun rockchip,camera-module-name = "XHG-RKX11B-V10"; 763*4882a593Smuzhiyun rockchip,camera-module-lens-name = "default"; 764*4882a593Smuzhiyun port { 765*4882a593Smuzhiyun ov8858_out: endpoint { 766*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam1>; 767*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 768*4882a593Smuzhiyun }; 769*4882a593Smuzhiyun }; 770*4882a593Smuzhiyun }; 771*4882a593Smuzhiyun}; 772*4882a593Smuzhiyun 773*4882a593Smuzhiyun&i2c3 { 774*4882a593Smuzhiyun status = "okay"; 775*4882a593Smuzhiyun pinctrl-names = "default"; 776*4882a593Smuzhiyun pinctrl-0 = <&i2c3m1_xfer>; 777*4882a593Smuzhiyun 778*4882a593Smuzhiyun focaltech: focaltech@38 { 779*4882a593Smuzhiyun status = "okay"; 780*4882a593Smuzhiyun compatible = "focaltech,fts"; 781*4882a593Smuzhiyun reg = <0x38>; 782*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd0_n>; 783*4882a593Smuzhiyun pinctrl-names = "default"; 784*4882a593Smuzhiyun pinctrl-0 = <&tp_gpio>; 785*4882a593Smuzhiyun focaltech,irq-gpio = <&gpio3 RK_PB0 IRQ_TYPE_LEVEL_LOW>; 786*4882a593Smuzhiyun focaltech,reset-gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; 787*4882a593Smuzhiyun focaltech,have-key = <0>; 788*4882a593Smuzhiyun focaltech,key-number = <3>; 789*4882a593Smuzhiyun focaltech,keys = <256 1068 64 64 128 1068 64 64 192 1068 64 64>; 790*4882a593Smuzhiyun focaltech,key-x-coord = <1600>; 791*4882a593Smuzhiyun focaltech,key-y-coord = <2176>; 792*4882a593Smuzhiyun focaltech,max-touch-number = <5>; 793*4882a593Smuzhiyun }; 794*4882a593Smuzhiyun}; 795*4882a593Smuzhiyun 796*4882a593Smuzhiyun&i2c5 { 797*4882a593Smuzhiyun status = "okay"; 798*4882a593Smuzhiyun 799*4882a593Smuzhiyun sensor@18 { 800*4882a593Smuzhiyun compatible = "gs_sc7a20"; 801*4882a593Smuzhiyun reg = <0x18>; 802*4882a593Smuzhiyun type = <SENSOR_TYPE_ACCEL>; 803*4882a593Smuzhiyun irq_enable = <0>; 804*4882a593Smuzhiyun pinctrl-names = "default"; 805*4882a593Smuzhiyun pinctrl-0 = <&sensor_gpio>; 806*4882a593Smuzhiyun irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_LEVEL_LOW>; 807*4882a593Smuzhiyun poll_delay_ms = <10>; 808*4882a593Smuzhiyun layout = <7>; 809*4882a593Smuzhiyun status = "disabled"; 810*4882a593Smuzhiyun }; 811*4882a593Smuzhiyun 812*4882a593Smuzhiyun ls_em3071x@24 { 813*4882a593Smuzhiyun compatible = "ls_em3071x"; 814*4882a593Smuzhiyun reg = <0x24>; 815*4882a593Smuzhiyun type = <SENSOR_TYPE_LIGHT>; 816*4882a593Smuzhiyun irq_enable = <0>; 817*4882a593Smuzhiyun poll_delay_ms = <100>; 818*4882a593Smuzhiyun status = "okay"; 819*4882a593Smuzhiyun }; 820*4882a593Smuzhiyun 821*4882a593Smuzhiyun ps_em3071x@24 { 822*4882a593Smuzhiyun compatible = "ps_em3071x"; 823*4882a593Smuzhiyun reg = <0x24>; 824*4882a593Smuzhiyun type = <SENSOR_TYPE_PROXIMITY>; 825*4882a593Smuzhiyun pinctrl-names = "default"; 826*4882a593Smuzhiyun pinctrl-0 = <&em3071x_irq_gpio>; 827*4882a593Smuzhiyun irq-gpio = <&gpio3 RK_PA6 IRQ_TYPE_LEVEL_LOW>; 828*4882a593Smuzhiyun irq_enable = <1>; 829*4882a593Smuzhiyun ps_threshold_high = <25>; 830*4882a593Smuzhiyun ps_threshold_low = <15>; 831*4882a593Smuzhiyun poll_delay_ms = <100>; 832*4882a593Smuzhiyun status = "okay"; 833*4882a593Smuzhiyun }; 834*4882a593Smuzhiyun 835*4882a593Smuzhiyun icm20607_acc@68 { 836*4882a593Smuzhiyun compatible = "icm2060x_acc"; 837*4882a593Smuzhiyun reg = <0x68>; 838*4882a593Smuzhiyun irq_enable = <0>; 839*4882a593Smuzhiyun poll_delay_ms = <30>; 840*4882a593Smuzhiyun type = <SENSOR_TYPE_ACCEL>; 841*4882a593Smuzhiyun layout = <1>; 842*4882a593Smuzhiyun status = "okay"; 843*4882a593Smuzhiyun }; 844*4882a593Smuzhiyun 845*4882a593Smuzhiyun icm20607_gyro@68 { 846*4882a593Smuzhiyun compatible = "icm2060x_gyro"; 847*4882a593Smuzhiyun reg = <0x68>; 848*4882a593Smuzhiyun irq_enable = <0>; 849*4882a593Smuzhiyun poll_delay_ms = <30>; 850*4882a593Smuzhiyun type = <SENSOR_TYPE_GYROSCOPE>; 851*4882a593Smuzhiyun layout = <1>; 852*4882a593Smuzhiyun status = "okay"; 853*4882a593Smuzhiyun }; 854*4882a593Smuzhiyun 855*4882a593Smuzhiyun ak09918_compass: ak09918_compass@c { 856*4882a593Smuzhiyun compatible = "ak09918"; 857*4882a593Smuzhiyun reg = <0x0c>; 858*4882a593Smuzhiyun type = <SENSOR_TYPE_COMPASS>; 859*4882a593Smuzhiyun irq_enable = <0>; 860*4882a593Smuzhiyun poll_delay_ms = <30>; 861*4882a593Smuzhiyun layout = <1>; 862*4882a593Smuzhiyun status = "okay"; 863*4882a593Smuzhiyun }; 864*4882a593Smuzhiyun}; 865*4882a593Smuzhiyun 866*4882a593Smuzhiyun&i2s1_8ch { 867*4882a593Smuzhiyun status = "okay"; 868*4882a593Smuzhiyun #sound-dai-cells = <0>; 869*4882a593Smuzhiyun rockchip,clk-trcm = <2>; 870*4882a593Smuzhiyun pinctrl-names = "default"; 871*4882a593Smuzhiyun pinctrl-0 = <&i2s1m0_sclkrx 872*4882a593Smuzhiyun &i2s1m0_lrckrx 873*4882a593Smuzhiyun &i2s1m0_sdi0 874*4882a593Smuzhiyun &i2s1m0_sdi1 875*4882a593Smuzhiyun &i2s1m0_sdi2 876*4882a593Smuzhiyun &i2s1m0_sdi3>; 877*4882a593Smuzhiyun}; 878*4882a593Smuzhiyun 879*4882a593Smuzhiyun&i2s3_2ch { 880*4882a593Smuzhiyun status = "okay"; 881*4882a593Smuzhiyun rockchip,clk-trcm = <1>; 882*4882a593Smuzhiyun pinctrl-names = "default"; 883*4882a593Smuzhiyun pinctrl-0 = <&i2s3m1_sclk 884*4882a593Smuzhiyun &i2s3m1_lrck 885*4882a593Smuzhiyun &i2s3m1_sdi 886*4882a593Smuzhiyun &i2s3m1_sdo>; 887*4882a593Smuzhiyun}; 888*4882a593Smuzhiyun 889*4882a593Smuzhiyun&jpegd { 890*4882a593Smuzhiyun status = "okay"; 891*4882a593Smuzhiyun}; 892*4882a593Smuzhiyun 893*4882a593Smuzhiyun&jpegd_mmu { 894*4882a593Smuzhiyun status = "okay"; 895*4882a593Smuzhiyun}; 896*4882a593Smuzhiyun 897*4882a593Smuzhiyun&video_phy0 { 898*4882a593Smuzhiyun status = "okay"; 899*4882a593Smuzhiyun}; 900*4882a593Smuzhiyun 901*4882a593Smuzhiyun&video_phy1 { 902*4882a593Smuzhiyun status = "okay"; 903*4882a593Smuzhiyun}; 904*4882a593Smuzhiyun 905*4882a593Smuzhiyun&mpp_srv { 906*4882a593Smuzhiyun status = "okay"; 907*4882a593Smuzhiyun}; 908*4882a593Smuzhiyun 909*4882a593Smuzhiyun&nandc0 { 910*4882a593Smuzhiyun status = "okay"; 911*4882a593Smuzhiyun}; 912*4882a593Smuzhiyun 913*4882a593Smuzhiyun&pinctrl { 914*4882a593Smuzhiyun cam { 915*4882a593Smuzhiyun cam_clkout0: cam-clkout0 { 916*4882a593Smuzhiyun rockchip,pins = 917*4882a593Smuzhiyun /* cam_clkout0 */ 918*4882a593Smuzhiyun <4 RK_PA7 1 &pcfg_pull_none>; 919*4882a593Smuzhiyun }; 920*4882a593Smuzhiyun 921*4882a593Smuzhiyun cam_sleep: cam-sleep { 922*4882a593Smuzhiyun rockchip,pins = 923*4882a593Smuzhiyun /* cam_sleep */ 924*4882a593Smuzhiyun <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; 925*4882a593Smuzhiyun }; 926*4882a593Smuzhiyun 927*4882a593Smuzhiyun camera_rst: camera-rst { 928*4882a593Smuzhiyun rockchip,pins = 929*4882a593Smuzhiyun /* front camera reset */ 930*4882a593Smuzhiyun <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, 931*4882a593Smuzhiyun /* back camra reset */ 932*4882a593Smuzhiyun <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 933*4882a593Smuzhiyun }; 934*4882a593Smuzhiyun 935*4882a593Smuzhiyun flash_led_gpios: flash-led { 936*4882a593Smuzhiyun rockchip,pins = 937*4882a593Smuzhiyun /* flash led enable */ 938*4882a593Smuzhiyun <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 939*4882a593Smuzhiyun }; 940*4882a593Smuzhiyun }; 941*4882a593Smuzhiyun 942*4882a593Smuzhiyun tp { 943*4882a593Smuzhiyun tp_gpio: tp-gpio { 944*4882a593Smuzhiyun rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, 945*4882a593Smuzhiyun <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 946*4882a593Smuzhiyun }; 947*4882a593Smuzhiyun }; 948*4882a593Smuzhiyun 949*4882a593Smuzhiyun headphone { 950*4882a593Smuzhiyun hp_det: hp-det { 951*4882a593Smuzhiyun rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; 952*4882a593Smuzhiyun }; 953*4882a593Smuzhiyun }; 954*4882a593Smuzhiyun 955*4882a593Smuzhiyun lcd { 956*4882a593Smuzhiyun lcd_rst_gpio: lcd-rst-gpio { 957*4882a593Smuzhiyun rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; 958*4882a593Smuzhiyun }; 959*4882a593Smuzhiyun 960*4882a593Smuzhiyun lcd_enable_gpio: lcd-enable-gpio { 961*4882a593Smuzhiyun rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; 962*4882a593Smuzhiyun }; 963*4882a593Smuzhiyun 964*4882a593Smuzhiyun lcd_panel_vsp: lcd-panel-vsp { 965*4882a593Smuzhiyun rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; 966*4882a593Smuzhiyun }; 967*4882a593Smuzhiyun 968*4882a593Smuzhiyun lcd_panel_vsn: lcd-panel-vsn { 969*4882a593Smuzhiyun rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; 970*4882a593Smuzhiyun }; 971*4882a593Smuzhiyun }; 972*4882a593Smuzhiyun 973*4882a593Smuzhiyun pmic { 974*4882a593Smuzhiyun pmic_int: pmic_int { 975*4882a593Smuzhiyun rockchip,pins = 976*4882a593Smuzhiyun <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 977*4882a593Smuzhiyun }; 978*4882a593Smuzhiyun 979*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 980*4882a593Smuzhiyun rockchip,pins = 981*4882a593Smuzhiyun <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; 982*4882a593Smuzhiyun }; 983*4882a593Smuzhiyun 984*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 985*4882a593Smuzhiyun rockchip,pins = 986*4882a593Smuzhiyun <0 RK_PA2 1 &pcfg_pull_none>; 987*4882a593Smuzhiyun }; 988*4882a593Smuzhiyun 989*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 990*4882a593Smuzhiyun rockchip,pins = 991*4882a593Smuzhiyun <0 RK_PA2 2 &pcfg_pull_none>; 992*4882a593Smuzhiyun }; 993*4882a593Smuzhiyun }; 994*4882a593Smuzhiyun 995*4882a593Smuzhiyun sensor { 996*4882a593Smuzhiyun sensor_gpio:sensor-gpio { 997*4882a593Smuzhiyun rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 998*4882a593Smuzhiyun }; 999*4882a593Smuzhiyun 1000*4882a593Smuzhiyun em3071x_irq_gpio: em3071x-irq-gpio { 1001*4882a593Smuzhiyun rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1002*4882a593Smuzhiyun }; 1003*4882a593Smuzhiyun 1004*4882a593Smuzhiyun mh248_irq_gpio: mh248-irq-gpio { 1005*4882a593Smuzhiyun rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; 1006*4882a593Smuzhiyun }; 1007*4882a593Smuzhiyun }; 1008*4882a593Smuzhiyun 1009*4882a593Smuzhiyun sdio-pwrseq { 1010*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 1011*4882a593Smuzhiyun rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, 1012*4882a593Smuzhiyun <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 1013*4882a593Smuzhiyun }; 1014*4882a593Smuzhiyun }; 1015*4882a593Smuzhiyun 1016*4882a593Smuzhiyun wireless-wlan { 1017*4882a593Smuzhiyun wifi_host_wake_irq: wifi-host-wake-irq { 1018*4882a593Smuzhiyun rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 1019*4882a593Smuzhiyun }; 1020*4882a593Smuzhiyun }; 1021*4882a593Smuzhiyun 1022*4882a593Smuzhiyun wireless-bluetooth { 1023*4882a593Smuzhiyun uart1_gpios: uart1-gpios { 1024*4882a593Smuzhiyun rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1025*4882a593Smuzhiyun }; 1026*4882a593Smuzhiyun }; 1027*4882a593Smuzhiyun}; 1028*4882a593Smuzhiyun 1029*4882a593Smuzhiyun&pmu_io_domains { 1030*4882a593Smuzhiyun status = "okay"; 1031*4882a593Smuzhiyun pmuio1-supply = <&vcc3v3_pmu>; 1032*4882a593Smuzhiyun pmuio2-supply = <&vcc3v3_pmu>; 1033*4882a593Smuzhiyun vccio1-supply = <&vccio_acodec>; 1034*4882a593Smuzhiyun vccio3-supply = <&vccio_sd>; 1035*4882a593Smuzhiyun vccio4-supply = <&vcca1v8_pmu>; 1036*4882a593Smuzhiyun vccio5-supply = <&vcc_1v8>; 1037*4882a593Smuzhiyun vccio6-supply = <&vcc1v8_dvp>; 1038*4882a593Smuzhiyun vccio7-supply = <&vccio_acodec>; 1039*4882a593Smuzhiyun}; 1040*4882a593Smuzhiyun 1041*4882a593Smuzhiyun&pwm4 { 1042*4882a593Smuzhiyun status = "okay"; 1043*4882a593Smuzhiyun}; 1044*4882a593Smuzhiyun 1045*4882a593Smuzhiyun&rkisp { 1046*4882a593Smuzhiyun status = "okay"; 1047*4882a593Smuzhiyun}; 1048*4882a593Smuzhiyun 1049*4882a593Smuzhiyun&rkisp_mmu { 1050*4882a593Smuzhiyun status = "okay"; 1051*4882a593Smuzhiyun}; 1052*4882a593Smuzhiyun 1053*4882a593Smuzhiyun&rkisp_vir0 { 1054*4882a593Smuzhiyun status = "okay"; 1055*4882a593Smuzhiyun 1056*4882a593Smuzhiyun port { 1057*4882a593Smuzhiyun #address-cells = <1>; 1058*4882a593Smuzhiyun #size-cells = <0>; 1059*4882a593Smuzhiyun 1060*4882a593Smuzhiyun isp0_in: endpoint@0 { 1061*4882a593Smuzhiyun reg = <0>; 1062*4882a593Smuzhiyun remote-endpoint = <&csidphy0_out>; 1063*4882a593Smuzhiyun }; 1064*4882a593Smuzhiyun }; 1065*4882a593Smuzhiyun}; 1066*4882a593Smuzhiyun 1067*4882a593Smuzhiyun&rknpu { 1068*4882a593Smuzhiyun memory-region = <&rknpu_reserved>; 1069*4882a593Smuzhiyun rknpu-supply = <&vdd_gpu>; 1070*4882a593Smuzhiyun status = "okay"; 1071*4882a593Smuzhiyun}; 1072*4882a593Smuzhiyun 1073*4882a593Smuzhiyun&rknpu_mmu { 1074*4882a593Smuzhiyun status = "disabled"; 1075*4882a593Smuzhiyun}; 1076*4882a593Smuzhiyun 1077*4882a593Smuzhiyun&rk_rga { 1078*4882a593Smuzhiyun status = "okay"; 1079*4882a593Smuzhiyun}; 1080*4882a593Smuzhiyun 1081*4882a593Smuzhiyun&rkvdec { 1082*4882a593Smuzhiyun status = "okay"; 1083*4882a593Smuzhiyun}; 1084*4882a593Smuzhiyun 1085*4882a593Smuzhiyun&rkvdec_mmu { 1086*4882a593Smuzhiyun status = "okay"; 1087*4882a593Smuzhiyun}; 1088*4882a593Smuzhiyun 1089*4882a593Smuzhiyun&rkvenc { 1090*4882a593Smuzhiyun status = "okay"; 1091*4882a593Smuzhiyun}; 1092*4882a593Smuzhiyun 1093*4882a593Smuzhiyun&rkvenc_mmu { 1094*4882a593Smuzhiyun status = "okay"; 1095*4882a593Smuzhiyun}; 1096*4882a593Smuzhiyun 1097*4882a593Smuzhiyun&route_dsi0 { 1098*4882a593Smuzhiyun status = "okay"; 1099*4882a593Smuzhiyun}; 1100*4882a593Smuzhiyun 1101*4882a593Smuzhiyun&saradc { 1102*4882a593Smuzhiyun status = "okay"; 1103*4882a593Smuzhiyun vref-supply = <&vcc_1v8>; 1104*4882a593Smuzhiyun}; 1105*4882a593Smuzhiyun 1106*4882a593Smuzhiyun&sdhci { 1107*4882a593Smuzhiyun bus-width = <8>; 1108*4882a593Smuzhiyun no-sdio; 1109*4882a593Smuzhiyun no-sd; 1110*4882a593Smuzhiyun non-removable; 1111*4882a593Smuzhiyun max-frequency = <200000000>; 1112*4882a593Smuzhiyun status = "okay"; 1113*4882a593Smuzhiyun}; 1114*4882a593Smuzhiyun 1115*4882a593Smuzhiyun&sdmmc1 { 1116*4882a593Smuzhiyun max-frequency = <150000000>; 1117*4882a593Smuzhiyun no-sd; 1118*4882a593Smuzhiyun no-mmc; 1119*4882a593Smuzhiyun bus-width = <4>; 1120*4882a593Smuzhiyun disable-wp; 1121*4882a593Smuzhiyun cap-sd-highspeed; 1122*4882a593Smuzhiyun cap-sdio-irq; 1123*4882a593Smuzhiyun keep-power-in-suspend; 1124*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 1125*4882a593Smuzhiyun non-removable; 1126*4882a593Smuzhiyun pinctrl-names = "default"; 1127*4882a593Smuzhiyun pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; 1128*4882a593Smuzhiyun sd-uhs-sdr104; 1129*4882a593Smuzhiyun rockchip,default-sample-phase = <90>; 1130*4882a593Smuzhiyun status = "okay"; 1131*4882a593Smuzhiyun}; 1132*4882a593Smuzhiyun 1133*4882a593Smuzhiyun&tsadc { 1134*4882a593Smuzhiyun status = "okay"; 1135*4882a593Smuzhiyun}; 1136*4882a593Smuzhiyun 1137*4882a593Smuzhiyun&uart1 { 1138*4882a593Smuzhiyun status = "okay"; 1139*4882a593Smuzhiyun pinctrl-names = "default"; 1140*4882a593Smuzhiyun pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; 1141*4882a593Smuzhiyun}; 1142*4882a593Smuzhiyun 1143*4882a593Smuzhiyun&u2phy0_otg { 1144*4882a593Smuzhiyun status = "okay"; 1145*4882a593Smuzhiyun}; 1146*4882a593Smuzhiyun 1147*4882a593Smuzhiyun&usb2phy0 { 1148*4882a593Smuzhiyun status = "okay"; 1149*4882a593Smuzhiyun}; 1150*4882a593Smuzhiyun 1151*4882a593Smuzhiyun&usbdrd_dwc3 { 1152*4882a593Smuzhiyun status = "okay"; 1153*4882a593Smuzhiyun}; 1154*4882a593Smuzhiyun 1155*4882a593Smuzhiyun&usbdrd30 { 1156*4882a593Smuzhiyun status = "okay"; 1157*4882a593Smuzhiyun}; 1158*4882a593Smuzhiyun 1159*4882a593Smuzhiyun&vdpu { 1160*4882a593Smuzhiyun status = "okay"; 1161*4882a593Smuzhiyun}; 1162*4882a593Smuzhiyun 1163*4882a593Smuzhiyun&vdpu_mmu { 1164*4882a593Smuzhiyun status = "okay"; 1165*4882a593Smuzhiyun}; 1166*4882a593Smuzhiyun 1167*4882a593Smuzhiyun&vepu { 1168*4882a593Smuzhiyun status = "okay"; 1169*4882a593Smuzhiyun}; 1170*4882a593Smuzhiyun 1171*4882a593Smuzhiyun&vepu_mmu { 1172*4882a593Smuzhiyun status = "okay"; 1173*4882a593Smuzhiyun}; 1174*4882a593Smuzhiyun 1175*4882a593Smuzhiyun&vop { 1176*4882a593Smuzhiyun status = "okay"; 1177*4882a593Smuzhiyun}; 1178*4882a593Smuzhiyun 1179*4882a593Smuzhiyun&vop_mmu { 1180*4882a593Smuzhiyun status = "okay"; 1181*4882a593Smuzhiyun}; 1182