xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
11*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h>
12*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
13*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
14*4882a593Smuzhiyun#include "rk3566.dtsi"
15*4882a593Smuzhiyun#include "rk3568-android.dtsi"
16*4882a593Smuzhiyun#include "rk3566-eink.dtsi"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun/ {
19*4882a593Smuzhiyun	model = "Rockchip RK3566 RK817 EINK LP4X Board";
20*4882a593Smuzhiyun	compatible = "rockchip,rk3566-rk817-eink", "rockchip,rk3566";
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	charge-animation {
23*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
24*4882a593Smuzhiyun		rockchip,uboot-charge-on = <1>;
25*4882a593Smuzhiyun		rockchip,android-charge-on = <0>;
26*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <3350>;
27*4882a593Smuzhiyun		rockchip,screen-on-voltage = <3400>;
28*4882a593Smuzhiyun		rockchip,auto-wakeup-interval = <60>;
29*4882a593Smuzhiyun		status = "okay";
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	adc_keys: adc-keys {
33*4882a593Smuzhiyun		status = "okay";
34*4882a593Smuzhiyun		compatible = "adc-keys";
35*4882a593Smuzhiyun		io-channels = <&saradc 0>;
36*4882a593Smuzhiyun		io-channel-names = "buttons";
37*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
38*4882a593Smuzhiyun		poll-interval = <100>;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun		vol-up-key {
41*4882a593Smuzhiyun			label = "volume up";
42*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
43*4882a593Smuzhiyun			press-threshold-microvolt = <9000>;
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun		vol-down-key {
47*4882a593Smuzhiyun			label = "volume down";
48*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
49*4882a593Smuzhiyun			press-threshold-microvolt = <235000>;
50*4882a593Smuzhiyun		};
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	backlight: backlight {
54*4882a593Smuzhiyun		compatible = "pwm-backlight";
55*4882a593Smuzhiyun		pwms = <&pwm0 0 25000 0>;
56*4882a593Smuzhiyun		brightness-levels = <
57*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
58*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
59*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
60*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
61*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
62*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
63*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
64*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
65*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
66*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
67*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
68*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
69*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
70*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
71*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
72*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
73*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
74*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
75*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
76*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
77*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
78*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
79*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
80*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
81*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
82*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
83*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
84*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
85*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
86*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
87*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
88*4882a593Smuzhiyun			248 249 250 251 252 253 254 255
89*4882a593Smuzhiyun		>;
90*4882a593Smuzhiyun		default-brightness-level = <200>;
91*4882a593Smuzhiyun	};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun	gpio_keys: gpio-keys {
94*4882a593Smuzhiyun		status = "disabled";
95*4882a593Smuzhiyun		compatible = "gpio-keys";
96*4882a593Smuzhiyun		autorepeat;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun		BACK {
99*4882a593Smuzhiyun			label = "GPIO Key Home";
100*4882a593Smuzhiyun			debounce-interval = <10>;
101*4882a593Smuzhiyun			interrupt-parent = <&gpio0>;
102*4882a593Smuzhiyun			interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
103*4882a593Smuzhiyun			linux,input-type = <EV_KEY>;
104*4882a593Smuzhiyun			linux,code = <KEY_BACK>;
105*4882a593Smuzhiyun		};
106*4882a593Smuzhiyun	};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	hdmi_sound: hdmi-sound {
109*4882a593Smuzhiyun		compatible = "simple-audio-card";
110*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
111*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <128>;
112*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,hdmi";
113*4882a593Smuzhiyun		status = "disabled";
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun		simple-audio-card,cpu {
116*4882a593Smuzhiyun				sound-dai = <&i2s0_8ch>;
117*4882a593Smuzhiyun		};
118*4882a593Smuzhiyun		simple-audio-card,codec {
119*4882a593Smuzhiyun				sound-dai = <&hdmi>;
120*4882a593Smuzhiyun		};
121*4882a593Smuzhiyun	};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun	leds: gpio-leds {
124*4882a593Smuzhiyun		compatible = "gpio-leds";
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun		led@2 {
127*4882a593Smuzhiyun			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
128*4882a593Smuzhiyun			linux,default-trigger = "battery-charging";
129*4882a593Smuzhiyun			label = "battery_charging";
130*4882a593Smuzhiyun			retain-state-suspended;
131*4882a593Smuzhiyun		};
132*4882a593Smuzhiyun	};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun	hall_sensor: hall-mh248 {
135*4882a593Smuzhiyun		compatible = "hall-mh248";
136*4882a593Smuzhiyun		irq-gpio = <&gpio0 RK_PC7 IRQ_TYPE_EDGE_BOTH>;
137*4882a593Smuzhiyun		hall-active = <1>;
138*4882a593Smuzhiyun		status = "okay";
139*4882a593Smuzhiyun	};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun	vccsys: vccsys {
142*4882a593Smuzhiyun		compatible = "regulator-fixed";
143*4882a593Smuzhiyun		regulator-name = "vcc3v8_sys";
144*4882a593Smuzhiyun		regulator-always-on;
145*4882a593Smuzhiyun		regulator-boot-on;
146*4882a593Smuzhiyun		regulator-min-microvolt = <3800000>;
147*4882a593Smuzhiyun		regulator-max-microvolt = <3800000>;
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	vcc_tp: vcc-tp-regulator {
151*4882a593Smuzhiyun		compatible = "regulator-fixed";
152*4882a593Smuzhiyun		enable-active-high;
153*4882a593Smuzhiyun		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
154*4882a593Smuzhiyun		pinctrl-names = "default";
155*4882a593Smuzhiyun		pinctrl-0 = <&vcc_tp_en>;
156*4882a593Smuzhiyun		regulator-name = "vcc_tp";
157*4882a593Smuzhiyun		regulator-boot-on;
158*4882a593Smuzhiyun		startup-delay-us = <10000>;
159*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
160*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
161*4882a593Smuzhiyun	};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun	rk817-sound {
164*4882a593Smuzhiyun		compatible = "simple-audio-card";
165*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
166*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,rk817-codec";
167*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun		simple-audio-card,cpu {
170*4882a593Smuzhiyun			sound-dai = <&i2s1_8ch>;
171*4882a593Smuzhiyun		};
172*4882a593Smuzhiyun		simple-audio-card,codec {
173*4882a593Smuzhiyun			sound-dai = <&rk817_codec>;
174*4882a593Smuzhiyun		};
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
178*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
179*4882a593Smuzhiyun		clocks = <&rk817 1>;
180*4882a593Smuzhiyun		clock-names = "ext_clock";
181*4882a593Smuzhiyun		pinctrl-names = "default";
182*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun		/*
185*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
186*4882a593Smuzhiyun		 * on the actual card populated):
187*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
188*4882a593Smuzhiyun		 * - PDN (power down when low)
189*4882a593Smuzhiyun		 */
190*4882a593Smuzhiyun		post-power-on-delay-ms = <200>;
191*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
192*4882a593Smuzhiyun	};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun	wireless-wlan {
195*4882a593Smuzhiyun		compatible = "wlan-platdata";
196*4882a593Smuzhiyun		rockchip,grf = <&grf>;
197*4882a593Smuzhiyun		wifi_chip_type = "ap6255";
198*4882a593Smuzhiyun		pinctrl-names = "default";
199*4882a593Smuzhiyun		pinctrl-0 = <&wifi_vbat &wifi_host_wake_irq>;
200*4882a593Smuzhiyun		WIFI,vbat_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
201*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
202*4882a593Smuzhiyun		status = "okay";
203*4882a593Smuzhiyun	};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun	wireless-bluetooth {
206*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
207*4882a593Smuzhiyun		clocks = <&rk817 1>;
208*4882a593Smuzhiyun		clock-names = "ext_clock";
209*4882a593Smuzhiyun		wifi-bt-power-toggle;
210*4882a593Smuzhiyun		uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
211*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
212*4882a593Smuzhiyun		pinctrl-0 = <&uart1m0_rtsn>,
213*4882a593Smuzhiyun			    <&bt_reset_gpio>,
214*4882a593Smuzhiyun			    <&bt_wake_gpio>,
215*4882a593Smuzhiyun			    <&bt_irq_gpio>;
216*4882a593Smuzhiyun		pinctrl-1 = <&uart1_gpios>;
217*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
218*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
219*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
220*4882a593Smuzhiyun		status = "okay";
221*4882a593Smuzhiyun	};
222*4882a593Smuzhiyun};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun&ebc {
225*4882a593Smuzhiyun	/* clock rate 1000M/n, (n=1~32) */
226*4882a593Smuzhiyun	assigned-clocks = <&cru CPLL_333M>, <&cru DCLK_EBC>;
227*4882a593Smuzhiyun	//assigned-clock-rates = <340000000>, <340000000>;
228*4882a593Smuzhiyun	assigned-clock-rates = <250000000>, <250000000>;
229*4882a593Smuzhiyun	status = "okay";
230*4882a593Smuzhiyun};
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun&ebc_dev {
233*4882a593Smuzhiyun	pmic = <&tps65185>;
234*4882a593Smuzhiyun	status = "okay";
235*4882a593Smuzhiyun#if 0
236*4882a593Smuzhiyun	/* ED097TC2U1 */
237*4882a593Smuzhiyun	panel,width = <1200>;
238*4882a593Smuzhiyun	panel,height = <825>;
239*4882a593Smuzhiyun	panel,vir_width = <1200>;
240*4882a593Smuzhiyun	panel,vir_height = <825>;
241*4882a593Smuzhiyun	panel,sdck = <25000000>;
242*4882a593Smuzhiyun	panel,lsl = <4>;
243*4882a593Smuzhiyun	panel,lbl = <4>;
244*4882a593Smuzhiyun	panel,ldl = <300>;
245*4882a593Smuzhiyun	panel,lel = <36>;
246*4882a593Smuzhiyun	panel,gdck-sta = <18>;
247*4882a593Smuzhiyun	panel,lgonl = <265>;
248*4882a593Smuzhiyun	panel,fsl = <2>;
249*4882a593Smuzhiyun	panel,fbl = <4>;
250*4882a593Smuzhiyun	panel,fdl = <825>;
251*4882a593Smuzhiyun	panel,fel = <24>;
252*4882a593Smuzhiyun	panel,mirror = <0>;
253*4882a593Smuzhiyun	panel,panel_16bit = <0>;
254*4882a593Smuzhiyun	panel,panel_color = <0>;
255*4882a593Smuzhiyun	panel,width-mm = <203>;
256*4882a593Smuzhiyun	panel,height-mm = <140>;
257*4882a593Smuzhiyun#endif
258*4882a593Smuzhiyun#if 1
259*4882a593Smuzhiyun	/* ES103TC1 */
260*4882a593Smuzhiyun	panel,width = <1872>;
261*4882a593Smuzhiyun	panel,height = <1404>;
262*4882a593Smuzhiyun	panel,vir_width = <1872>;
263*4882a593Smuzhiyun	panel,vir_height = <1404>;
264*4882a593Smuzhiyun	panel,sdck = <33300000>;
265*4882a593Smuzhiyun	panel,lsl = <18>;
266*4882a593Smuzhiyun	panel,lbl = <17>;
267*4882a593Smuzhiyun	panel,ldl = <234>;
268*4882a593Smuzhiyun	panel,lel = <7>;
269*4882a593Smuzhiyun	panel,gdck-sta = <34>;
270*4882a593Smuzhiyun	panel,lgonl = <192>;
271*4882a593Smuzhiyun	panel,fsl = <1>;
272*4882a593Smuzhiyun	panel,fbl = <4>;
273*4882a593Smuzhiyun	panel,fdl = <1404>;
274*4882a593Smuzhiyun	panel,fel = <12>;
275*4882a593Smuzhiyun	panel,mirror = <0>;
276*4882a593Smuzhiyun	panel,panel_16bit = <1>;
277*4882a593Smuzhiyun	panel,panel_color = <0>;
278*4882a593Smuzhiyun	panel,width-mm = <157>;
279*4882a593Smuzhiyun	panel,height-mm = <210>;
280*4882a593Smuzhiyun#endif
281*4882a593Smuzhiyun#if 0
282*4882a593Smuzhiyun	/* ES133TC1 */
283*4882a593Smuzhiyun	panel,width = <2200>;
284*4882a593Smuzhiyun	panel,height = <1650>;
285*4882a593Smuzhiyun	panel,vir_width = <2208>;
286*4882a593Smuzhiyun	panel,vir_height = <1650>;
287*4882a593Smuzhiyun	panel,sdck = <37500000>;
288*4882a593Smuzhiyun	panel,lsl = <4>;
289*4882a593Smuzhiyun	panel,lbl = <8>;
290*4882a593Smuzhiyun	panel,ldl = <275>;
291*4882a593Smuzhiyun	panel,lel = <14>;
292*4882a593Smuzhiyun	panel,gdck-sta = <34>;
293*4882a593Smuzhiyun	panel,lgonl = <217>;
294*4882a593Smuzhiyun	panel,fsl = <1>;
295*4882a593Smuzhiyun	panel,fbl = <4>;
296*4882a593Smuzhiyun	panel,fdl = <1650>;
297*4882a593Smuzhiyun	panel,fel = <6>;
298*4882a593Smuzhiyun	panel,mirror = <0>;
299*4882a593Smuzhiyun	panel,panel_16bit = <1>;
300*4882a593Smuzhiyun	panel,panel_color = <0>;
301*4882a593Smuzhiyun	panel,width-mm = <157>;
302*4882a593Smuzhiyun	panel,height-mm = <210>;
303*4882a593Smuzhiyun#endif
304*4882a593Smuzhiyun};
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun&cpu0 {
307*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
308*4882a593Smuzhiyun};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun&csi2_dphy_hw {
311*4882a593Smuzhiyun	status = "okay";
312*4882a593Smuzhiyun};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun&csi2_dphy0 {
315*4882a593Smuzhiyun	status = "okay";
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun	ports {
318*4882a593Smuzhiyun		#address-cells = <1>;
319*4882a593Smuzhiyun		#size-cells = <0>;
320*4882a593Smuzhiyun		port@0 {
321*4882a593Smuzhiyun			reg = <0>;
322*4882a593Smuzhiyun			#address-cells = <1>;
323*4882a593Smuzhiyun			#size-cells = <0>;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@0 {
326*4882a593Smuzhiyun				reg = <0>;
327*4882a593Smuzhiyun				/*remote-endpoint = <&ov5648_out>;*/
328*4882a593Smuzhiyun				data-lanes = <1 2>;
329*4882a593Smuzhiyun			};
330*4882a593Smuzhiyun		};
331*4882a593Smuzhiyun		port@1 {
332*4882a593Smuzhiyun			reg = <1>;
333*4882a593Smuzhiyun			#address-cells = <1>;
334*4882a593Smuzhiyun			#size-cells = <0>;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun			csidphy0_out: endpoint@0 {
337*4882a593Smuzhiyun				reg = <0>;
338*4882a593Smuzhiyun				remote-endpoint = <&isp0_in>;
339*4882a593Smuzhiyun			};
340*4882a593Smuzhiyun		};
341*4882a593Smuzhiyun	};
342*4882a593Smuzhiyun};
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun&gpu {
345*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
346*4882a593Smuzhiyun	status = "okay";
347*4882a593Smuzhiyun};
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun&hdmi {
350*4882a593Smuzhiyun	status = "disabled";
351*4882a593Smuzhiyun};
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun&hdmi_in_vp0 {
354*4882a593Smuzhiyun	status = "disabled";
355*4882a593Smuzhiyun};
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun&hdmi_in_vp1 {
358*4882a593Smuzhiyun	status = "disabled";
359*4882a593Smuzhiyun};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun&hdmi_sound {
362*4882a593Smuzhiyun	status = "disabled";
363*4882a593Smuzhiyun};
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun&i2c0 {
366*4882a593Smuzhiyun	status = "okay";
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun	vdd_cpu: tcs4525@1c {
369*4882a593Smuzhiyun		compatible = "tcs,tcs4525";
370*4882a593Smuzhiyun		reg = <0x1c>;
371*4882a593Smuzhiyun		vin-supply = <&vccsys>;
372*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
373*4882a593Smuzhiyun		regulator-name = "vdd_cpu";
374*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
375*4882a593Smuzhiyun		regulator-max-microvolt = <1390000>;
376*4882a593Smuzhiyun		regulator-init-microvolt = <900000>;
377*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
378*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <0>;
379*4882a593Smuzhiyun		regulator-initial-mode = <0x2>;
380*4882a593Smuzhiyun		regulator-boot-on;
381*4882a593Smuzhiyun		regulator-always-on;
382*4882a593Smuzhiyun		regulator-state-mem {
383*4882a593Smuzhiyun			regulator-on-in-suspend;
384*4882a593Smuzhiyun			regulator-suspend-microvolt = <1100000>;
385*4882a593Smuzhiyun			regulator-changeable-in-suspend;
386*4882a593Smuzhiyun		};
387*4882a593Smuzhiyun	};
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun	rk817: pmic@20 {
390*4882a593Smuzhiyun		compatible = "rockchip,rk817";
391*4882a593Smuzhiyun		reg = <0x20>;
392*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
393*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun		pinctrl-names = "default";
396*4882a593Smuzhiyun//		pinctrl-names = "default", "pmic-sleep",
397*4882a593Smuzhiyun//				"pmic-power-off", "pmic-reset";
398*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int>;
399*4882a593Smuzhiyun//		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
400*4882a593Smuzhiyun//		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
401*4882a593Smuzhiyun//		pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
402*4882a593Smuzhiyun		rockchip,system-power-controller;
403*4882a593Smuzhiyun		wakeup-source;
404*4882a593Smuzhiyun		#clock-cells = <1>;
405*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
406*4882a593Smuzhiyun		//fb-inner-reg-idxs = <2>;
407*4882a593Smuzhiyun		/* 1: rst regs (default in codes), 0: rst the pmic */
408*4882a593Smuzhiyun		pmic-reset-func = <0>;
409*4882a593Smuzhiyun		/* not save the PMIC_POWER_EN register in uboot */
410*4882a593Smuzhiyun		not-save-power-en = <1>;
411*4882a593Smuzhiyun		vcc1-supply = <&vccsys>;
412*4882a593Smuzhiyun		vcc2-supply = <&vccsys>;
413*4882a593Smuzhiyun		vcc3-supply = <&vccsys>;
414*4882a593Smuzhiyun		vcc4-supply = <&vccsys>;
415*4882a593Smuzhiyun		vcc5-supply = <&vccsys>;
416*4882a593Smuzhiyun		vcc6-supply = <&vccsys>;
417*4882a593Smuzhiyun		vcc7-supply = <&vccsys>;
418*4882a593Smuzhiyun		vcc8-supply = <&vccsys>;
419*4882a593Smuzhiyun		vcc9-supply = <&dcdc_boost>;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun		pwrkey {
422*4882a593Smuzhiyun			status = "okay";
423*4882a593Smuzhiyun		};
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
426*4882a593Smuzhiyun			gpio-controller;
427*4882a593Smuzhiyun			#gpio-cells = <2>;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun			rk817_slppin_null: rk817_slppin_null {
430*4882a593Smuzhiyun				pins = "gpio_slp";
431*4882a593Smuzhiyun				function = "pin_fun0";
432*4882a593Smuzhiyun			};
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun			rk817_slppin_slp: rk817_slppin_slp {
435*4882a593Smuzhiyun				pins = "gpio_slp";
436*4882a593Smuzhiyun				function = "pin_fun1";
437*4882a593Smuzhiyun			};
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
440*4882a593Smuzhiyun				pins = "gpio_slp";
441*4882a593Smuzhiyun				function = "pin_fun2";
442*4882a593Smuzhiyun			};
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun			rk817_slppin_rst: rk817_slppin_rst {
445*4882a593Smuzhiyun				pins = "gpio_slp";
446*4882a593Smuzhiyun				function = "pin_fun3";
447*4882a593Smuzhiyun			};
448*4882a593Smuzhiyun		};
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun		regulators {
451*4882a593Smuzhiyun			vdd_logic: DCDC_REG1 {
452*4882a593Smuzhiyun				regulator-always-on;
453*4882a593Smuzhiyun				regulator-boot-on;
454*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
455*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
456*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
457*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
458*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
459*4882a593Smuzhiyun				regulator-name = "vdd_logic";
460*4882a593Smuzhiyun				regulator-state-mem {
461*4882a593Smuzhiyun					regulator-off-in-suspend;
462*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
463*4882a593Smuzhiyun					regulator-changeable-in-suspend;
464*4882a593Smuzhiyun				};
465*4882a593Smuzhiyun			};
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun			vdd_gpu: DCDC_REG2 {
468*4882a593Smuzhiyun				regulator-always-on;
469*4882a593Smuzhiyun				regulator-boot-on;
470*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
471*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
472*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
473*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
474*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
475*4882a593Smuzhiyun				regulator-name = "vdd_gpu";
476*4882a593Smuzhiyun					regulator-state-mem {
477*4882a593Smuzhiyun					regulator-off-in-suspend;
478*4882a593Smuzhiyun					regulator-changeable-in-suspend;
479*4882a593Smuzhiyun				};
480*4882a593Smuzhiyun			};
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
483*4882a593Smuzhiyun				regulator-always-on;
484*4882a593Smuzhiyun				regulator-boot-on;
485*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
486*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
487*4882a593Smuzhiyun				regulator-state-mem {
488*4882a593Smuzhiyun					regulator-on-in-suspend;
489*4882a593Smuzhiyun				};
490*4882a593Smuzhiyun			};
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun			vcc_3v3: DCDC_REG4 {
493*4882a593Smuzhiyun				regulator-always-on;
494*4882a593Smuzhiyun				regulator-boot-on;
495*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
496*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
497*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
498*4882a593Smuzhiyun				regulator-name = "vcc_3v3";
499*4882a593Smuzhiyun				regulator-state-mem {
500*4882a593Smuzhiyun					regulator-off-in-suspend;
501*4882a593Smuzhiyun					regulator-changeable-in-suspend;
502*4882a593Smuzhiyun				};
503*4882a593Smuzhiyun			};
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun			vcca1v8_pmu: LDO_REG1 {
506*4882a593Smuzhiyun				regulator-always-on;
507*4882a593Smuzhiyun				regulator-boot-on;
508*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
509*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
510*4882a593Smuzhiyun				regulator-name = "vcca1v8_pmu";
511*4882a593Smuzhiyun				regulator-state-mem {
512*4882a593Smuzhiyun					regulator-on-in-suspend;
513*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
514*4882a593Smuzhiyun					regulator-changeable-in-suspend;
515*4882a593Smuzhiyun				};
516*4882a593Smuzhiyun			};
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun			vdda_0v9: LDO_REG2 {
519*4882a593Smuzhiyun				regulator-always-on;
520*4882a593Smuzhiyun				regulator-boot-on;
521*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
522*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
523*4882a593Smuzhiyun				regulator-name = "vdda_0v9";
524*4882a593Smuzhiyun				regulator-state-mem {
525*4882a593Smuzhiyun					regulator-off-in-suspend;
526*4882a593Smuzhiyun					regulator-changeable-in-suspend;
527*4882a593Smuzhiyun				};
528*4882a593Smuzhiyun			};
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun			vdda0v9_pmu: LDO_REG3 {
531*4882a593Smuzhiyun				regulator-always-on;
532*4882a593Smuzhiyun				regulator-boot-on;
533*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
534*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
535*4882a593Smuzhiyun				regulator-name = "vdda0v9_pmu";
536*4882a593Smuzhiyun				regulator-state-mem {
537*4882a593Smuzhiyun					regulator-on-in-suspend;
538*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
539*4882a593Smuzhiyun					regulator-changeable-in-suspend;
540*4882a593Smuzhiyun				};
541*4882a593Smuzhiyun			};
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun			vccio_acodec: LDO_REG4 {
544*4882a593Smuzhiyun				regulator-always-on;
545*4882a593Smuzhiyun				regulator-boot-on;
546*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
547*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
548*4882a593Smuzhiyun				regulator-name = "vccio_acodec";
549*4882a593Smuzhiyun				regulator-state-mem {
550*4882a593Smuzhiyun					regulator-off-in-suspend;
551*4882a593Smuzhiyun					regulator-changeable-in-suspend;
552*4882a593Smuzhiyun				};
553*4882a593Smuzhiyun			};
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun			vccio_sd: LDO_REG5 {
556*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
557*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
558*4882a593Smuzhiyun				regulator-name = "vccio_sd";
559*4882a593Smuzhiyun				regulator-state-mem {
560*4882a593Smuzhiyun					regulator-off-in-suspend;
561*4882a593Smuzhiyun					regulator-changeable-in-suspend;
562*4882a593Smuzhiyun				};
563*4882a593Smuzhiyun			};
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun			vcc3v3_pmu: LDO_REG6 {
566*4882a593Smuzhiyun				regulator-always-on;
567*4882a593Smuzhiyun				regulator-boot-on;
568*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
569*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
570*4882a593Smuzhiyun				regulator-name = "vcc3v3_pmu";
571*4882a593Smuzhiyun				regulator-state-mem {
572*4882a593Smuzhiyun					regulator-on-in-suspend;
573*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
574*4882a593Smuzhiyun					regulator-changeable-in-suspend;
575*4882a593Smuzhiyun				};
576*4882a593Smuzhiyun			};
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun			vcc_1v8: LDO_REG7 {
579*4882a593Smuzhiyun				regulator-always-on;
580*4882a593Smuzhiyun				regulator-boot-on;
581*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
582*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
583*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
584*4882a593Smuzhiyun				regulator-state-mem {
585*4882a593Smuzhiyun					regulator-off-in-suspend;
586*4882a593Smuzhiyun					regulator-changeable-in-suspend;
587*4882a593Smuzhiyun				};
588*4882a593Smuzhiyun			};
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun			vcc1v8_dvp: LDO_REG8 {
591*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
592*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
593*4882a593Smuzhiyun				regulator-name = "vcc1v8_dvp";
594*4882a593Smuzhiyun				regulator-state-mem {
595*4882a593Smuzhiyun					regulator-off-in-suspend;
596*4882a593Smuzhiyun					regulator-changeable-in-suspend;
597*4882a593Smuzhiyun				};
598*4882a593Smuzhiyun			};
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun			sleep_sta_ctl: LDO_REG9 {
601*4882a593Smuzhiyun				regulator-name = "sleep_sta_ctl";
602*4882a593Smuzhiyun				regulator-state-mem {
603*4882a593Smuzhiyun					regulator-on-in-suspend;
604*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
605*4882a593Smuzhiyun					regulator-changeable-in-suspend;
606*4882a593Smuzhiyun				};
607*4882a593Smuzhiyun			};
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun			dcdc_boost: BOOST {
610*4882a593Smuzhiyun				regulator-always-on;
611*4882a593Smuzhiyun				regulator-boot-on;
612*4882a593Smuzhiyun				regulator-min-microvolt = <4700000>;
613*4882a593Smuzhiyun				regulator-max-microvolt = <5400000>;
614*4882a593Smuzhiyun				regulator-name = "boost";
615*4882a593Smuzhiyun				regulator-state-mem {
616*4882a593Smuzhiyun					regulator-off-in-suspend;
617*4882a593Smuzhiyun					regulator-changeable-in-suspend;
618*4882a593Smuzhiyun				};
619*4882a593Smuzhiyun			};
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun			otg_switch: OTG_SWITCH {
622*4882a593Smuzhiyun				regulator-name = "otg_switch";
623*4882a593Smuzhiyun				regulator-state-mem {
624*4882a593Smuzhiyun					regulator-off-in-suspend;
625*4882a593Smuzhiyun					regulator-changeable-in-suspend;
626*4882a593Smuzhiyun				};
627*4882a593Smuzhiyun			};
628*4882a593Smuzhiyun		};
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun		battery {
631*4882a593Smuzhiyun			compatible = "rk817,battery";
632*4882a593Smuzhiyun			ocv_table = <3400 3513 3578 3687 3734 3752 3763
633*4882a593Smuzhiyun				     3766 3771 3784 3804 3836 3885 3925
634*4882a593Smuzhiyun				     3962 4005 4063 4114 4169 4227 4303>;
635*4882a593Smuzhiyun			design_capacity = <4150>;
636*4882a593Smuzhiyun			design_qmax = <4565>;
637*4882a593Smuzhiyun			bat_res = <100>;
638*4882a593Smuzhiyun			sleep_enter_current = <150>;
639*4882a593Smuzhiyun			sleep_exit_current = <180>;
640*4882a593Smuzhiyun			sleep_filter_current = <100>;
641*4882a593Smuzhiyun			power_off_thresd = <3450>;
642*4882a593Smuzhiyun			zero_algorithm_vol = <3850>;
643*4882a593Smuzhiyun			max_soc_offset = <60>;
644*4882a593Smuzhiyun			monitor_sec = <5>;
645*4882a593Smuzhiyun			sample_res = <10>;
646*4882a593Smuzhiyun			virtual_power = <0>;
647*4882a593Smuzhiyun			low_power_sleep = <1>;
648*4882a593Smuzhiyun		};
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun		charger {
651*4882a593Smuzhiyun			compatible = "rk817,charger";
652*4882a593Smuzhiyun			min_input_voltage = <4500>;
653*4882a593Smuzhiyun			max_input_current = <1500>;
654*4882a593Smuzhiyun			max_chrg_current = <2000>;
655*4882a593Smuzhiyun			max_chrg_voltage = <4300>;
656*4882a593Smuzhiyun			chrg_term_mode = <0>;
657*4882a593Smuzhiyun			chrg_finish_cur = <300>;
658*4882a593Smuzhiyun			virtual_power = <0>;
659*4882a593Smuzhiyun			dc_det_adc = <0>;
660*4882a593Smuzhiyun			extcon = <&usb2phy0>;
661*4882a593Smuzhiyun			gate_function_disable = <1>;
662*4882a593Smuzhiyun		};
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun		rk817_codec: codec {
665*4882a593Smuzhiyun			#sound-dai-cells = <0>;
666*4882a593Smuzhiyun			compatible = "rockchip,rk817-codec";
667*4882a593Smuzhiyun			clocks = <&cru I2S1_MCLKOUT>;
668*4882a593Smuzhiyun			clock-names = "mclk";
669*4882a593Smuzhiyun			assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
670*4882a593Smuzhiyun			assigned-clock-rates = <12288000>;
671*4882a593Smuzhiyun			assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
672*4882a593Smuzhiyun			pinctrl-names = "default";
673*4882a593Smuzhiyun			pinctrl-0 = <&i2s1m0_mclk>;
674*4882a593Smuzhiyun			hp-volume = <20>;
675*4882a593Smuzhiyun			spk-volume = <3>;
676*4882a593Smuzhiyun			out-l2spk-r2hp;
677*4882a593Smuzhiyun			spk-ctl-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
678*4882a593Smuzhiyun			status = "okay";
679*4882a593Smuzhiyun		};
680*4882a593Smuzhiyun	};
681*4882a593Smuzhiyun};
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun&i2c1 {
684*4882a593Smuzhiyun	status = "okay";
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun	wacom: wacom@9 {
687*4882a593Smuzhiyun		compatible = "wacom,w9013";
688*4882a593Smuzhiyun		reg = <0x09>;
689*4882a593Smuzhiyun		pwr-supply = <&vcc_tp>;
690*4882a593Smuzhiyun		pinctrl-names = "default";
691*4882a593Smuzhiyun		pinctrl-0 = <&wacom_gpio>;
692*4882a593Smuzhiyun		gpio_detect = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
693*4882a593Smuzhiyun		gpio_intr = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
694*4882a593Smuzhiyun		gpio_rst = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
695*4882a593Smuzhiyun		revert_x = <0>;
696*4882a593Smuzhiyun		revert_y = <0>;
697*4882a593Smuzhiyun		xy_exchange = <0>;
698*4882a593Smuzhiyun	};
699*4882a593Smuzhiyun};
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun&i2c3 {
702*4882a593Smuzhiyun	status = "okay";
703*4882a593Smuzhiyun	pinctrl-names = "default";
704*4882a593Smuzhiyun	pinctrl-0 = <&i2c3m1_xfer>;
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun	tps65185: tps65185@68 {
707*4882a593Smuzhiyun		status = "okay";
708*4882a593Smuzhiyun		compatible = "ti,tps65185";
709*4882a593Smuzhiyun		reg = <0x68>;
710*4882a593Smuzhiyun		pinctrl-names = "default";
711*4882a593Smuzhiyun		pinctrl-0 = <&tps65185_gpio>;
712*4882a593Smuzhiyun		wakeup-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
713*4882a593Smuzhiyun		vcomctl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
714*4882a593Smuzhiyun		int-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
715*4882a593Smuzhiyun		powerup-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
716*4882a593Smuzhiyun		poweren-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
717*4882a593Smuzhiyun	};
718*4882a593Smuzhiyun};
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun&i2c4 {
721*4882a593Smuzhiyun	//camera
722*4882a593Smuzhiyun};
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun&i2c5 {
725*4882a593Smuzhiyun	status = "okay";
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun	sensor@4c {
728*4882a593Smuzhiyun		status = "okay";
729*4882a593Smuzhiyun		compatible = "gs_mma7660";
730*4882a593Smuzhiyun		reg = <0x4c>;
731*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
732*4882a593Smuzhiyun		irq_enable = <0>;
733*4882a593Smuzhiyun		poll_delay_ms = <30>;
734*4882a593Smuzhiyun		layout = <6>;
735*4882a593Smuzhiyun		reprobe_en = <1>;
736*4882a593Smuzhiyun	};
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun	tsc@24 {
739*4882a593Smuzhiyun		status = "okay";
740*4882a593Smuzhiyun		compatible = "cy,cyttsp5_i2c_adapter";
741*4882a593Smuzhiyun		reg = <0x24>;
742*4882a593Smuzhiyun		cy,adapter_id = "cyttsp5_i2c_adapter";
743*4882a593Smuzhiyun		pinctrl-names = "default";
744*4882a593Smuzhiyun		pinctrl-0 = <&tsc_gpio>;
745*4882a593Smuzhiyun		cytp-supply = <&vcc_tp>;
746*4882a593Smuzhiyun		cy,core {
747*4882a593Smuzhiyun			cy,name = "cyttsp5_core";
748*4882a593Smuzhiyun			cy,irq_gpio =  <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
749*4882a593Smuzhiyun			cy,rst_gpio =  <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
750*4882a593Smuzhiyun			cy,hid_desc_register = <1>;
751*4882a593Smuzhiyun			/* CY_CORE_FLAG_RESTORE_PARAMETERS */
752*4882a593Smuzhiyun			cy,flags = <6>;
753*4882a593Smuzhiyun			/* CY_CORE_EWG_NONE */
754*4882a593Smuzhiyun			cy,easy_wakeup_gesture = <0>;
755*4882a593Smuzhiyun			cy,btn_keys = <172 /* KEY_HOMEPAGE */
756*4882a593Smuzhiyun						/* previously was KEY_HOME, new Android versions use KEY_HOMEPAGE */
757*4882a593Smuzhiyun						139 /* KEY_MENU */
758*4882a593Smuzhiyun						158 /* KEY_BACK */
759*4882a593Smuzhiyun						217 /* KEY_SEARCH */
760*4882a593Smuzhiyun						114 /* KEY_VOLUMEDOWN */
761*4882a593Smuzhiyun						115 /* KEY_VOLUMEUP */
762*4882a593Smuzhiyun						212 /* KEY_CAMERA */
763*4882a593Smuzhiyun						116>; /* KEY_POWER */
764*4882a593Smuzhiyun			cy,btn_keys-tag = <0>;
765*4882a593Smuzhiyun			cy,mt {
766*4882a593Smuzhiyun				cy,name = "cyttsp5_mt";
767*4882a593Smuzhiyun				cy,inp_dev_name = "cyttsp5_mt";
768*4882a593Smuzhiyun				cy,flags = <0xA8>;
769*4882a593Smuzhiyun				cy,abs =
770*4882a593Smuzhiyun					/* ABS_MT_POSITION_X, CY_ABS_MIN_X, CY_ABS_MAX_X, 0, 0 */
771*4882a593Smuzhiyun					<0x35 0 1404 0 0
772*4882a593Smuzhiyun					/* ABS_MT_POSITION_Y, CY_ABS_MIN_Y, CY_ABS_MAX_Y, 0, 0 */
773*4882a593Smuzhiyun					0x36 0 1872 0 0
774*4882a593Smuzhiyun					/* ABS_MT_PRESSURE, CY_ABS_MIN_P, CY_ABS_MAX_P, 0, 0 */
775*4882a593Smuzhiyun					0x3a 0 255 0 0
776*4882a593Smuzhiyun					/* CY_IGNORE_VALUE, CY_ABS_MIN_W, CY_ABS_MAX_W, 0, 0 */
777*4882a593Smuzhiyun					0xffff 0 255 0 0
778*4882a593Smuzhiyun					/* ABS_MT_TRACKING_ID, CY_ABS_MIN_T, CY_ABS_MAX_T, 0, 0 */
779*4882a593Smuzhiyun					0x39 0 15 0 0
780*4882a593Smuzhiyun					/* ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0 */
781*4882a593Smuzhiyun					0x30 0 255 0 0
782*4882a593Smuzhiyun					/* ABS_MT_TOUCH_MINOR, 0, 255, 0, 0 */
783*4882a593Smuzhiyun					0x31 0 255 0 0
784*4882a593Smuzhiyun					/* ABS_MT_ORIENTATION, -127, 127, 0, 0 */
785*4882a593Smuzhiyun					0x34 0xffffff81 127 0 0
786*4882a593Smuzhiyun					/* ABS_MT_TOOL_TYPE, 0, MT_TOOL_MAX, 0, 0 */
787*4882a593Smuzhiyun					0x37 0 1 0 0
788*4882a593Smuzhiyun					/* ABS_DISTANCE, 0, 255, 0, 0 */
789*4882a593Smuzhiyun					0x19 0 255 0 0>;
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun					cy,vkeys_x = <1404>;
792*4882a593Smuzhiyun					cy,vkeys_y = <1872>;
793*4882a593Smuzhiyun					cy,revert_x = <0>;
794*4882a593Smuzhiyun					cy,revert_y = <0>;
795*4882a593Smuzhiyun					cy,xy_exchange = <0>;
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun					cy,virtual_keys =
798*4882a593Smuzhiyun						/* KeyCode CenterX CenterY Width Height */
799*4882a593Smuzhiyun						/* KEY_BACK */
800*4882a593Smuzhiyun						<158 1360 90 160 180
801*4882a593Smuzhiyun						/* KEY_MENU */
802*4882a593Smuzhiyun						139 1360 270 160 180
803*4882a593Smuzhiyun						/* KEY_HOMEPAGE */
804*4882a593Smuzhiyun						172 1360 450 160 180
805*4882a593Smuzhiyun						/* KEY SEARCH */
806*4882a593Smuzhiyun						217 1360 630 160 180>;
807*4882a593Smuzhiyun			};
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun			cy,btn {
810*4882a593Smuzhiyun				cy,name = "cyttsp5_btn";
811*4882a593Smuzhiyun				cy,inp_dev_name = "cyttsp5_btn";
812*4882a593Smuzhiyun			};
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun			cy,proximity {
815*4882a593Smuzhiyun				cy,name = "cyttsp5_proximity";
816*4882a593Smuzhiyun				cy,inp_dev_name = "cyttsp5_proximity";
817*4882a593Smuzhiyun				cy,abs =
818*4882a593Smuzhiyun			/* ABS_DISTANCE, CY_PROXIMITY_MIN_VAL, CY_PROXIMITY_MAX_VAL, 0, 0 */
819*4882a593Smuzhiyun					<0x19 0 1 0 0>;
820*4882a593Smuzhiyun			};
821*4882a593Smuzhiyun		};
822*4882a593Smuzhiyun	};
823*4882a593Smuzhiyun};
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun&i2s0_8ch {
826*4882a593Smuzhiyun	status = "disabled";
827*4882a593Smuzhiyun};
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun&i2s1_8ch {
830*4882a593Smuzhiyun	status = "okay";
831*4882a593Smuzhiyun	rockchip,clk-trcm = <1>;
832*4882a593Smuzhiyun	pinctrl-names = "default";
833*4882a593Smuzhiyun	pinctrl-0 = <&i2s1m0_sclktx
834*4882a593Smuzhiyun		     &i2s1m0_lrcktx
835*4882a593Smuzhiyun		     &i2s1m0_sdi0
836*4882a593Smuzhiyun		     &i2s1m0_sdo0>;
837*4882a593Smuzhiyun};
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun&jpegd {
840*4882a593Smuzhiyun	status = "okay";
841*4882a593Smuzhiyun};
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun&jpegd_mmu {
844*4882a593Smuzhiyun	status = "okay";
845*4882a593Smuzhiyun};
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun&video_phy0 {
848*4882a593Smuzhiyun	status = "disabled";
849*4882a593Smuzhiyun};
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun&mpp_srv {
852*4882a593Smuzhiyun	status = "okay";
853*4882a593Smuzhiyun};
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun&nandc0 {
856*4882a593Smuzhiyun	status = "disabled";
857*4882a593Smuzhiyun};
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun&pinctrl {
860*4882a593Smuzhiyun	wacom {
861*4882a593Smuzhiyun		wacom_gpio: wacom-gpio {
862*4882a593Smuzhiyun			rockchip,pins =
863*4882a593Smuzhiyun					<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>,
864*4882a593Smuzhiyun					<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>,
865*4882a593Smuzhiyun					<0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
866*4882a593Smuzhiyun		};
867*4882a593Smuzhiyun	};
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun	tsc {
870*4882a593Smuzhiyun		tsc_gpio: tsc-gpio {
871*4882a593Smuzhiyun			rockchip,pins =
872*4882a593Smuzhiyun					<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>, //touch q gpio
873*4882a593Smuzhiyun					<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
874*4882a593Smuzhiyun					<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
875*4882a593Smuzhiyun		};
876*4882a593Smuzhiyun	};
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun	tps_pmic {
879*4882a593Smuzhiyun		tps65185_gpio: tps65185-gpio {
880*4882a593Smuzhiyun			rockchip,pins =
881*4882a593Smuzhiyun					<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
882*4882a593Smuzhiyun					<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
883*4882a593Smuzhiyun					<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
884*4882a593Smuzhiyun					<3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
885*4882a593Smuzhiyun					<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
886*4882a593Smuzhiyun		};
887*4882a593Smuzhiyun	};
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun	pmic {
890*4882a593Smuzhiyun		pmic_int: pmic_int {
891*4882a593Smuzhiyun			rockchip,pins =
892*4882a593Smuzhiyun				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
893*4882a593Smuzhiyun		};
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun		soc_slppin_gpio: soc_slppin_gpio {
896*4882a593Smuzhiyun			rockchip,pins =
897*4882a593Smuzhiyun				<0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>;
898*4882a593Smuzhiyun		};
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun		soc_slppin_slp: soc_slppin_slp {
901*4882a593Smuzhiyun			rockchip,pins =
902*4882a593Smuzhiyun				<0 RK_PA2 1 &pcfg_pull_none>;
903*4882a593Smuzhiyun		};
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun		soc_slppin_rst: soc_slppin_rst {
906*4882a593Smuzhiyun			rockchip,pins =
907*4882a593Smuzhiyun				<0 RK_PA2 2 &pcfg_pull_none>;
908*4882a593Smuzhiyun		};
909*4882a593Smuzhiyun	};
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun	sdio-pwrseq {
912*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
913*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
914*4882a593Smuzhiyun		};
915*4882a593Smuzhiyun	};
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun	wireless-wlan {
918*4882a593Smuzhiyun		wifi_vbat: wifi-vbat {
919*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
920*4882a593Smuzhiyun		};
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
923*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
924*4882a593Smuzhiyun		};
925*4882a593Smuzhiyun	};
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun	wireless-bluetooth {
928*4882a593Smuzhiyun		uart1_gpios: uart1-gpios {
929*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
930*4882a593Smuzhiyun		};
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun		bt_reset_gpio: bt-reset-gpio {
933*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
934*4882a593Smuzhiyun		};
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun		bt_wake_gpio: bt-wake-gpio {
937*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
938*4882a593Smuzhiyun		};
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun		bt_irq_gpio: bt-irq-gpio {
941*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
942*4882a593Smuzhiyun		};
943*4882a593Smuzhiyun	};
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun	vcc-tp {
946*4882a593Smuzhiyun		vcc_tp_en: vcc-tp-en {
947*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
948*4882a593Smuzhiyun		};
949*4882a593Smuzhiyun	};
950*4882a593Smuzhiyun};
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun&pmu_io_domains {
953*4882a593Smuzhiyun	status = "okay";
954*4882a593Smuzhiyun	pmuio1-supply = <&vcc3v3_pmu>;
955*4882a593Smuzhiyun	pmuio2-supply = <&vcc3v3_pmu>;
956*4882a593Smuzhiyun	vccio1-supply = <&vccio_acodec>;
957*4882a593Smuzhiyun	vccio3-supply = <&vcc_1v8>;
958*4882a593Smuzhiyun	vccio4-supply = <&vcca1v8_pmu>;
959*4882a593Smuzhiyun	vccio5-supply = <&vcc_3v3>;
960*4882a593Smuzhiyun	vccio6-supply = <&vcc_3v3>;
961*4882a593Smuzhiyun	vccio7-supply = <&vcc_1v8>;
962*4882a593Smuzhiyun};
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun&pwm0 {
965*4882a593Smuzhiyun	status = "okay";
966*4882a593Smuzhiyun};
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun&rk_rga {
969*4882a593Smuzhiyun	status = "okay";
970*4882a593Smuzhiyun};
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun&rkisp {
973*4882a593Smuzhiyun	status = "okay";
974*4882a593Smuzhiyun};
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun&rkisp_mmu {
977*4882a593Smuzhiyun	status = "okay";
978*4882a593Smuzhiyun};
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun&rkisp_vir0 {
981*4882a593Smuzhiyun	status = "okay";
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun	port {
984*4882a593Smuzhiyun		#address-cells = <1>;
985*4882a593Smuzhiyun		#size-cells = <0>;
986*4882a593Smuzhiyun
987*4882a593Smuzhiyun		isp0_in: endpoint@0 {
988*4882a593Smuzhiyun			reg = <0>;
989*4882a593Smuzhiyun			remote-endpoint = <&csidphy0_out>;
990*4882a593Smuzhiyun		};
991*4882a593Smuzhiyun	};
992*4882a593Smuzhiyun};
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun&rkvdec {
995*4882a593Smuzhiyun	status = "okay";
996*4882a593Smuzhiyun};
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun&rkvdec_mmu {
999*4882a593Smuzhiyun	status = "okay";
1000*4882a593Smuzhiyun};
1001*4882a593Smuzhiyun
1002*4882a593Smuzhiyun&rkvenc {
1003*4882a593Smuzhiyun	status = "okay";
1004*4882a593Smuzhiyun};
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun&rkvenc_mmu {
1007*4882a593Smuzhiyun	status = "okay";
1008*4882a593Smuzhiyun};
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun&rockchip_suspend {
1011*4882a593Smuzhiyun	status = "okay";
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun	rockchip,regulator-off-in-mem-lite =
1014*4882a593Smuzhiyun		<&vdd_cpu>, <&vdd_logic>, <&vdd_gpu>, <&vcc_3v3>, <&vdda_0v9>, <&vcc_1v8>,
1015*4882a593Smuzhiyun		<&vccio_acodec>, <&vccio_sd>, <&vcc1v8_dvp>, <&dcdc_boost>, <&otg_switch>,
1016*4882a593Smuzhiyun		<&sleep_sta_ctl>;
1017*4882a593Smuzhiyun	rockchip,regulator-on-in-mem-lite =
1018*4882a593Smuzhiyun		<&vcc_ddr>, <&vdda0v9_pmu>, <&vcca1v8_pmu>, <&vcc3v3_pmu>;
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun	rockchip,regulator-off-in-mem =
1021*4882a593Smuzhiyun		<&vdd_cpu>, <&vdd_logic>, <&vdd_gpu>, <&vcc_3v3>, <&vdda_0v9>, <&vcc_1v8>,
1022*4882a593Smuzhiyun		<&vccio_acodec>, <&vccio_sd>, <&vcc1v8_dvp>, <&dcdc_boost>, <&otg_switch>,
1023*4882a593Smuzhiyun		<&sleep_sta_ctl>;
1024*4882a593Smuzhiyun	rockchip,regulator-on-in-mem =
1025*4882a593Smuzhiyun		<&vcc_ddr>, <&vdda0v9_pmu>, <&vcca1v8_pmu>, <&vcc3v3_pmu>;
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun	rockchip,regulator-off-in-mem-ultra =
1028*4882a593Smuzhiyun		<&vdd_logic>, <&vdd_gpu>, <&vcc_ddr>, <&vcc_3v3>, <&vdda_0v9>, <&vcc_1v8>,
1029*4882a593Smuzhiyun		<&vdda0v9_pmu>, <&vcca1v8_pmu>, <&vcc3v3_pmu>, <&vccio_acodec>, <&vccio_sd>,
1030*4882a593Smuzhiyun		<&vcc1v8_dvp>, <&dcdc_boost>, <&otg_switch>;
1031*4882a593Smuzhiyun	rockchip,regulator-on-in-mem-ultra = <&vdd_cpu>, <&sleep_sta_ctl>;
1032*4882a593Smuzhiyun};
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun&saradc {
1035*4882a593Smuzhiyun	status = "okay";
1036*4882a593Smuzhiyun	vref-supply = <&vcc_1v8>;
1037*4882a593Smuzhiyun};
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun&sdhci {
1040*4882a593Smuzhiyun	bus-width = <8>;
1041*4882a593Smuzhiyun	no-sdio;
1042*4882a593Smuzhiyun	no-sd;
1043*4882a593Smuzhiyun	non-removable;
1044*4882a593Smuzhiyun	keep-power-in-suspend;
1045*4882a593Smuzhiyun	max-frequency = <200000000>;
1046*4882a593Smuzhiyun	status = "okay";
1047*4882a593Smuzhiyun};
1048*4882a593Smuzhiyun
1049*4882a593Smuzhiyun&sdmmc1 {
1050*4882a593Smuzhiyun	max-frequency = <150000000>;
1051*4882a593Smuzhiyun	no-sd;
1052*4882a593Smuzhiyun	no-mmc;
1053*4882a593Smuzhiyun	bus-width = <4>;
1054*4882a593Smuzhiyun	disable-wp;
1055*4882a593Smuzhiyun	cap-sd-highspeed;
1056*4882a593Smuzhiyun	cap-sdio-irq;
1057*4882a593Smuzhiyun	keep-power-in-suspend;
1058*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
1059*4882a593Smuzhiyun	non-removable;
1060*4882a593Smuzhiyun	pinctrl-names = "default";
1061*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
1062*4882a593Smuzhiyun	sd-uhs-sdr104;
1063*4882a593Smuzhiyun	rockchip,default-sample-phase = <90>;
1064*4882a593Smuzhiyun	status = "okay";
1065*4882a593Smuzhiyun};
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun&tsadc {
1068*4882a593Smuzhiyun	status = "okay";
1069*4882a593Smuzhiyun};
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun&uart1 {
1072*4882a593Smuzhiyun	status = "okay";
1073*4882a593Smuzhiyun	pinctrl-names = "default";
1074*4882a593Smuzhiyun	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
1075*4882a593Smuzhiyun};
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun&u2phy0_otg {
1078*4882a593Smuzhiyun	status = "okay";
1079*4882a593Smuzhiyun};
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun&usb2phy0 {
1082*4882a593Smuzhiyun	status = "okay";
1083*4882a593Smuzhiyun};
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun&usbdrd_dwc3 {
1086*4882a593Smuzhiyun	status = "okay";
1087*4882a593Smuzhiyun};
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun&usbdrd30 {
1090*4882a593Smuzhiyun	status = "okay";
1091*4882a593Smuzhiyun};
1092*4882a593Smuzhiyun
1093*4882a593Smuzhiyun&vdpu {
1094*4882a593Smuzhiyun	status = "okay";
1095*4882a593Smuzhiyun};
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun&vdpu_mmu {
1098*4882a593Smuzhiyun	status = "okay";
1099*4882a593Smuzhiyun};
1100*4882a593Smuzhiyun
1101*4882a593Smuzhiyun&vepu {
1102*4882a593Smuzhiyun	status = "okay";
1103*4882a593Smuzhiyun};
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun&vepu_mmu {
1106*4882a593Smuzhiyun	status = "okay";
1107*4882a593Smuzhiyun};
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun&vop {
1110*4882a593Smuzhiyun	status = "okay";
1111*4882a593Smuzhiyun};
1112*4882a593Smuzhiyun
1113*4882a593Smuzhiyun&vop_mmu {
1114*4882a593Smuzhiyun	status = "okay";
1115*4882a593Smuzhiyun};
1116