1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 10*4882a593Smuzhiyun#include "rk3566.dtsi" 11*4882a593Smuzhiyun#include "rk3566-evb.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "Rockchip RK3566 EVB5 LP4X V10 Board"; 15*4882a593Smuzhiyun compatible = "rockchip,rk3566-evb5-lp4x-v10", "rockchip,rk3566"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun vcc3v3_pcie: gpio-regulator { 18*4882a593Smuzhiyun compatible = "regulator-fixed"; 19*4882a593Smuzhiyun regulator-name = "vcc3v3_pcie"; 20*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 21*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 22*4882a593Smuzhiyun enable-active-high; 23*4882a593Smuzhiyun gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 24*4882a593Smuzhiyun startup-delay-us = <5000>; 25*4882a593Smuzhiyun vin-supply = <&dc_12v>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun rk_headset: rk-headset { 29*4882a593Smuzhiyun compatible = "rockchip_headset"; 30*4882a593Smuzhiyun headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; 31*4882a593Smuzhiyun pinctrl-names = "default"; 32*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun vcc3v3_vga: vcc3v3-vga { 36*4882a593Smuzhiyun compatible = "regulator-fixed"; 37*4882a593Smuzhiyun regulator-name = "vcc3v3_vga"; 38*4882a593Smuzhiyun regulator-always-on; 39*4882a593Smuzhiyun regulator-boot-on; 40*4882a593Smuzhiyun gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; 41*4882a593Smuzhiyun enable-active-high; 42*4882a593Smuzhiyun vin-supply = <&vcc3v3_sys>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&audiopwmout_diff { 47*4882a593Smuzhiyun status = "disabled"; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&bt_sound { 51*4882a593Smuzhiyun status = "disabled"; 52*4882a593Smuzhiyun simple-audio-card,cpu { 53*4882a593Smuzhiyun sound-dai = <&i2s2_2ch>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&combphy1_usq { 58*4882a593Smuzhiyun status = "okay"; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&combphy2_psq { 62*4882a593Smuzhiyun status = "disabled"; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&dig_acodec { 66*4882a593Smuzhiyun status = "disabled"; 67*4882a593Smuzhiyun rockchip,pwm-output-mode; 68*4882a593Smuzhiyun pinctrl-names = "default"; 69*4882a593Smuzhiyun pinctrl-0 = <&audiopwm_loutp 70*4882a593Smuzhiyun &audiopwm_loutn 71*4882a593Smuzhiyun &audiopwm_routp 72*4882a593Smuzhiyun &audiopwm_routn 73*4882a593Smuzhiyun >; 74*4882a593Smuzhiyun}; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun/* 77*4882a593Smuzhiyun * video_phy0 needs to be enabled 78*4882a593Smuzhiyun * when dsi0 is enabled 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun&dsi0 { 81*4882a593Smuzhiyun status = "okay"; 82*4882a593Smuzhiyun connect = <&vp1_out_dsi0>; 83*4882a593Smuzhiyun}; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun&dsi0_in_vp0 { 86*4882a593Smuzhiyun status = "disabled"; 87*4882a593Smuzhiyun}; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun&dsi0_in_vp1 { 90*4882a593Smuzhiyun status = "okay"; 91*4882a593Smuzhiyun}; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun&dsi0_panel { 94*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd0_n>; 95*4882a593Smuzhiyun reset-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; 96*4882a593Smuzhiyun pinctrl-names = "default"; 97*4882a593Smuzhiyun pinctrl-0 = <&lcd0_rst_gpio>; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun/* 101*4882a593Smuzhiyun * video_phy1 needs to be enabled 102*4882a593Smuzhiyun * when dsi1 is enabled 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun&dsi1 { 105*4882a593Smuzhiyun status = "disabled"; 106*4882a593Smuzhiyun}; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun&dsi1_in_vp0 { 109*4882a593Smuzhiyun status = "disabled"; 110*4882a593Smuzhiyun}; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun&dsi1_in_vp1 { 113*4882a593Smuzhiyun status = "disabled"; 114*4882a593Smuzhiyun}; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun&dsi1_panel { 117*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd1_n>; 118*4882a593Smuzhiyun reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; 119*4882a593Smuzhiyun pinctrl-names = "default"; 120*4882a593Smuzhiyun pinctrl-0 = <&lcd1_rst_gpio>; 121*4882a593Smuzhiyun}; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun&edp { 124*4882a593Smuzhiyun hpd-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; 125*4882a593Smuzhiyun status = "disabled"; 126*4882a593Smuzhiyun}; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun&edp_phy { 129*4882a593Smuzhiyun status = "disabled"; 130*4882a593Smuzhiyun}; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun&edp_in_vp0 { 133*4882a593Smuzhiyun status = "disabled"; 134*4882a593Smuzhiyun}; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun&edp_in_vp1 { 137*4882a593Smuzhiyun status = "disabled"; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun&gmac1 { 141*4882a593Smuzhiyun phy-mode = "rgmii"; 142*4882a593Smuzhiyun clock_in_out = "output"; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; 145*4882a593Smuzhiyun snps,reset-active-low; 146*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 147*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 150*4882a593Smuzhiyun assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; 151*4882a593Smuzhiyun assigned-clock-rates = <0>, <125000000>; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun pinctrl-names = "default"; 154*4882a593Smuzhiyun pinctrl-0 = <&gmac1m0_miim 155*4882a593Smuzhiyun &gmac1m0_tx_bus2_level3 156*4882a593Smuzhiyun &gmac1m0_rx_bus2 157*4882a593Smuzhiyun &gmac1m0_rgmii_clk_level2 158*4882a593Smuzhiyun &gmac1m0_rgmii_bus_level3>; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun tx_delay = <0x41>; 161*4882a593Smuzhiyun rx_delay = <0x2e>; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun phy-handle = <&rgmii_phy1>; 164*4882a593Smuzhiyun status = "disabled"; 165*4882a593Smuzhiyun}; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun/* 168*4882a593Smuzhiyun * power-supply should switche to vcc3v3_lcd1_n 169*4882a593Smuzhiyun * when mipi panel is connected to dsi1. 170*4882a593Smuzhiyun */ 171*4882a593Smuzhiyun>1x { 172*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd0_n>; 173*4882a593Smuzhiyun}; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun&i2c5 { 176*4882a593Smuzhiyun status = "disabled"; 177*4882a593Smuzhiyun}; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun&i2s2_2ch { 180*4882a593Smuzhiyun pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; 181*4882a593Smuzhiyun rockchip,bclk-fs = <32>; 182*4882a593Smuzhiyun status = "disabled"; 183*4882a593Smuzhiyun}; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun&i2s3_2ch { 186*4882a593Smuzhiyun status = "disabled"; 187*4882a593Smuzhiyun}; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun&mdio1 { 190*4882a593Smuzhiyun rgmii_phy1: phy@0 { 191*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 192*4882a593Smuzhiyun reg = <0x0>; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun&video_phy0 { 197*4882a593Smuzhiyun status = "okay"; 198*4882a593Smuzhiyun}; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun&video_phy1 { 201*4882a593Smuzhiyun status = "disabled"; 202*4882a593Smuzhiyun}; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun&pcie2x1 { 205*4882a593Smuzhiyun reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 206*4882a593Smuzhiyun vpcie3v3-supply = <&vcc3v3_pcie>; 207*4882a593Smuzhiyun status = "disabled"; 208*4882a593Smuzhiyun}; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun&pdm { 211*4882a593Smuzhiyun status = "disabled"; 212*4882a593Smuzhiyun pinctrl-names = "default"; 213*4882a593Smuzhiyun pinctrl-0 = <&pdmm1_clk1 214*4882a593Smuzhiyun &pdmm1_sdi1 215*4882a593Smuzhiyun &pdmm1_sdi2 216*4882a593Smuzhiyun &pdmm1_sdi3>; 217*4882a593Smuzhiyun}; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun&pdmics { 220*4882a593Smuzhiyun status = "disabled"; 221*4882a593Smuzhiyun}; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun&pdm_mic_array { 224*4882a593Smuzhiyun status = "disabled"; 225*4882a593Smuzhiyun}; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun&route_dsi0 { 228*4882a593Smuzhiyun status = "okay"; 229*4882a593Smuzhiyun}; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun&sdmmc2 { 232*4882a593Smuzhiyun status = "disabled"; 233*4882a593Smuzhiyun}; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun&uart1 { 236*4882a593Smuzhiyun status = "okay"; 237*4882a593Smuzhiyun pinctrl-names = "default"; 238*4882a593Smuzhiyun pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; 239*4882a593Smuzhiyun}; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun&uart3 { 242*4882a593Smuzhiyun status = "disabled"; 243*4882a593Smuzhiyun}; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun&uart4 { 246*4882a593Smuzhiyun status = "disabled"; 247*4882a593Smuzhiyun}; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun&uart7 { 250*4882a593Smuzhiyun status = "disabled"; 251*4882a593Smuzhiyun}; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun&usb_host0_ehci { 254*4882a593Smuzhiyun status = "okay"; 255*4882a593Smuzhiyun}; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun&usb_host0_ohci { 258*4882a593Smuzhiyun status = "disabled"; 259*4882a593Smuzhiyun}; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun&usb_host1_ehci { 262*4882a593Smuzhiyun status = "okay"; 263*4882a593Smuzhiyun}; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun&usb_host1_ohci { 266*4882a593Smuzhiyun status = "disabled"; 267*4882a593Smuzhiyun}; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun&vcc3v3_lcd0_n { 270*4882a593Smuzhiyun gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; 271*4882a593Smuzhiyun enable-active-high; 272*4882a593Smuzhiyun}; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun&vcc3v3_lcd1_n { 275*4882a593Smuzhiyun gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; 276*4882a593Smuzhiyun enable-active-high; 277*4882a593Smuzhiyun}; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun&wireless_bluetooth { 280*4882a593Smuzhiyun uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; 281*4882a593Smuzhiyun pinctrl-names = "default", "rts_gpio"; 282*4882a593Smuzhiyun pinctrl-0 = <&uart1m1_rtsn>; 283*4882a593Smuzhiyun pinctrl-1 = <&uart1_gpios>; 284*4882a593Smuzhiyun BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; 285*4882a593Smuzhiyun BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 286*4882a593Smuzhiyun BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 287*4882a593Smuzhiyun status = "disabled"; 288*4882a593Smuzhiyun}; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun&wireless_wlan { 291*4882a593Smuzhiyun pinctrl-names = "default"; 292*4882a593Smuzhiyun pinctrl-0 = <&wifi_host_wake_irq>; 293*4882a593Smuzhiyun status = "disabled"; 294*4882a593Smuzhiyun}; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun&work_led { 297*4882a593Smuzhiyun status = "disabled"; 298*4882a593Smuzhiyun}; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun&pinctrl { 301*4882a593Smuzhiyun headphone { 302*4882a593Smuzhiyun hp_det: hp-det { 303*4882a593Smuzhiyun rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; 304*4882a593Smuzhiyun }; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun lcd0 { 308*4882a593Smuzhiyun lcd0_rst_gpio: lcd0-rst-gpio { 309*4882a593Smuzhiyun rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun lcd1 { 314*4882a593Smuzhiyun lcd1_rst_gpio: lcd1-rst-gpio { 315*4882a593Smuzhiyun rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun wireless-wlan { 320*4882a593Smuzhiyun wifi_host_wake_irq: wifi-host-wake-irq { 321*4882a593Smuzhiyun rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; 322*4882a593Smuzhiyun }; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun wireless-bluetooth { 326*4882a593Smuzhiyun uart1_gpios: uart1-gpios { 327*4882a593Smuzhiyun rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun}; 331