1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun reserved-memory { 8*4882a593Smuzhiyun #address-cells = <2>; 9*4882a593Smuzhiyun #size-cells = <2>; 10*4882a593Smuzhiyun ranges; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun waveform_reserved: waveform@10800000 { 13*4882a593Smuzhiyun reg = <0x0 0x10800000 0x0 0x100000>; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun display_reserved: framebuffer@10900000 { 17*4882a593Smuzhiyun reg = <0x0 0x10900000 0x0 0x2000000>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun ebc_dev: ebc-dev { 22*4882a593Smuzhiyun compatible = "rockchip,ebc-dev"; 23*4882a593Smuzhiyun ebc_tcon = <&ebc>; 24*4882a593Smuzhiyun eink_tcon = <&eink>; 25*4882a593Smuzhiyun memory-region = <&display_reserved>; 26*4882a593Smuzhiyun waveform-region = <&waveform_reserved>; 27*4882a593Smuzhiyun status = "okay"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun&cpu0_opp_table { 32*4882a593Smuzhiyun opp-216000000 { 33*4882a593Smuzhiyun opp-hz = /bits/ 64 <216000000>; 34*4882a593Smuzhiyun opp-microvolt = <825000 825000 1150000>; 35*4882a593Smuzhiyun clock-latency-ns = <40000>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun opp-312000000 { 38*4882a593Smuzhiyun opp-hz = /bits/ 64 <312000000>; 39*4882a593Smuzhiyun opp-microvolt = <825000 825000 1150000>; 40*4882a593Smuzhiyun clock-latency-ns = <40000>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&dfi { 45*4882a593Smuzhiyun status = "okay"; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun&dmc { 49*4882a593Smuzhiyun center-supply = <&vdd_logic>; 50*4882a593Smuzhiyun auto-freq-en = <0>; 51*4882a593Smuzhiyun status = "okay"; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&dmc_opp_table { 55*4882a593Smuzhiyun opp-324000000 { 56*4882a593Smuzhiyun opp-hz = /bits/ 64 <324000000>; 57*4882a593Smuzhiyun opp-microvolt = <875000>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun opp-528000000 { 60*4882a593Smuzhiyun opp-hz = /bits/ 64 <528000000>; 61*4882a593Smuzhiyun opp-microvolt = <875000>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&ebc { 66*4882a593Smuzhiyun status = "okay"; 67*4882a593Smuzhiyun}; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun&eink { 70*4882a593Smuzhiyun status = "okay"; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun&gpu_opp_table { 74*4882a593Smuzhiyun opp-100000000 { 75*4882a593Smuzhiyun opp-hz = /bits/ 64 <100000000>; 76*4882a593Smuzhiyun opp-microvolt = <825000>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun opp-150000000 { 79*4882a593Smuzhiyun opp-hz = /bits/ 64 <150000000>; 80*4882a593Smuzhiyun opp-microvolt = <825000>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun&lpddr4_params { 85*4882a593Smuzhiyun /* freq info, freq_0 is final frequency, unit: MHz */ 86*4882a593Smuzhiyun freq_0 = <528>; 87*4882a593Smuzhiyun freq_1 = <324>; 88*4882a593Smuzhiyun freq_2 = <324>; 89*4882a593Smuzhiyun freq_3 = <324>; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&lpddr4x_params { 93*4882a593Smuzhiyun /* freq info, freq_0 is final frequency, unit: MHz */ 94*4882a593Smuzhiyun freq_0 = <528>; 95*4882a593Smuzhiyun freq_1 = <324>; 96*4882a593Smuzhiyun freq_2 = <324>; 97*4882a593Smuzhiyun freq_3 = <324>; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&rockchip_suspend { 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun rockchip,sleep-debug-en = <0>; 104*4882a593Smuzhiyun rockchip,sleep-mode-config = < 105*4882a593Smuzhiyun (0 106*4882a593Smuzhiyun | RKPM_SLP_ARMOFF_LOGOFF 107*4882a593Smuzhiyun | RKPM_SLP_CENTER_OFF 108*4882a593Smuzhiyun | RKPM_SLP_HW_PLLS_OFF 109*4882a593Smuzhiyun | RKPM_SLP_PMUALIVE_32K 110*4882a593Smuzhiyun | RKPM_SLP_OSC_DIS 111*4882a593Smuzhiyun | RKPM_SLP_PMIC_LP 112*4882a593Smuzhiyun | RKPM_SLP_32K_PVTM 113*4882a593Smuzhiyun ) 114*4882a593Smuzhiyun >; 115*4882a593Smuzhiyun}; 116*4882a593Smuzhiyun 117