1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "rk3566-box.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Rockchip RK3566 BOX DEMO V10 Board"; 13*4882a593Smuzhiyun compatible = "rockchip,rk3568-box-demo-v10", "rockchip,rk3566"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun gpio-leds { 16*4882a593Smuzhiyun compatible = "gpio-leds"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun ir-led { 19*4882a593Smuzhiyun gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; 20*4882a593Smuzhiyun default-state = "off"; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun work-led { 24*4882a593Smuzhiyun gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; 25*4882a593Smuzhiyun linux,default-trigger = "timer"; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun vcc2v5_sys: vcc2v5-ddr { 30*4882a593Smuzhiyun compatible = "regulator-fixed"; 31*4882a593Smuzhiyun regulator-name = "vcc2v5-sys"; 32*4882a593Smuzhiyun regulator-always-on; 33*4882a593Smuzhiyun regulator-boot-on; 34*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 35*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 36*4882a593Smuzhiyun vin-supply = <&vcc3v3_sys>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 40*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 41*4882a593Smuzhiyun clocks = <&pmucru CLK_RTC_32K>; 42*4882a593Smuzhiyun clock-names = "ext_clock"; 43*4882a593Smuzhiyun pinctrl-names = "default"; 44*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h &wifi_32k>; 45*4882a593Smuzhiyun reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun vcc3v3_sd: vcc3v3-sd-regulator { 49*4882a593Smuzhiyun compatible = "regulator-gpio"; 50*4882a593Smuzhiyun regulator-name = "vcc3v3_sd"; 51*4882a593Smuzhiyun regulator-min-microvolt = <100000>; 52*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 53*4882a593Smuzhiyun gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 54*4882a593Smuzhiyun gpios-states = <0x1>; 55*4882a593Smuzhiyun states = <100000 0x1 56*4882a593Smuzhiyun 3300000 0x0>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun vccio_sd: vccio-sd-regulator { 60*4882a593Smuzhiyun compatible = "regulator-gpio"; 61*4882a593Smuzhiyun regulator-name = "vccio_sd"; 62*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 63*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 64*4882a593Smuzhiyun gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; 65*4882a593Smuzhiyun gpios-states = <0x1>; 66*4882a593Smuzhiyun states = <1800000 0x0 67*4882a593Smuzhiyun 3300000 0x1>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun vcc5v0_host: vcc5v0-host-regulator { 71*4882a593Smuzhiyun compatible = "regulator-fixed"; 72*4882a593Smuzhiyun enable-active-high; 73*4882a593Smuzhiyun gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; 74*4882a593Smuzhiyun pinctrl-names = "default"; 75*4882a593Smuzhiyun pinctrl-0 = <&vcc5v0_host_en>; 76*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 77*4882a593Smuzhiyun regulator-always-on; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun vcc5v0_otg: vcc5v0-otg-regulator { 81*4882a593Smuzhiyun compatible = "regulator-fixed"; 82*4882a593Smuzhiyun enable-active-high; 83*4882a593Smuzhiyun gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 84*4882a593Smuzhiyun pinctrl-names = "default"; 85*4882a593Smuzhiyun pinctrl-0 = <&vcc5v0_otg_en>; 86*4882a593Smuzhiyun regulator-name = "vcc5v0_otg"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun vcc_camera: vcc-camera-regulator { 90*4882a593Smuzhiyun compatible = "regulator-fixed"; 91*4882a593Smuzhiyun gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 92*4882a593Smuzhiyun pinctrl-names = "default"; 93*4882a593Smuzhiyun pinctrl-0 = <&camera_pwr>; 94*4882a593Smuzhiyun regulator-name = "vcc_camera"; 95*4882a593Smuzhiyun enable-active-high; 96*4882a593Smuzhiyun regulator-always-on; 97*4882a593Smuzhiyun regulator-boot-on; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun wireless_wlan: wireless-wlan { 101*4882a593Smuzhiyun compatible = "wlan-platdata"; 102*4882a593Smuzhiyun rockchip,grf = <&grf>; 103*4882a593Smuzhiyun wifi_chip_type = "ap6398s"; 104*4882a593Smuzhiyun pinctrl-names = "default"; 105*4882a593Smuzhiyun pinctrl-0 = <&wifi_host_wake_irq>; 106*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; 107*4882a593Smuzhiyun status = "okay"; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun wireless_bluetooth: wireless-bluetooth { 111*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 112*4882a593Smuzhiyun clocks = <&pmucru CLK_RTC_32K>; 113*4882a593Smuzhiyun clock-names = "ext_clock"; 114*4882a593Smuzhiyun //wifi-bt-power-toggle; 115*4882a593Smuzhiyun uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; 116*4882a593Smuzhiyun pinctrl-names = "default", "rts_gpio"; 117*4882a593Smuzhiyun pinctrl-0 = <&uart1m0_rtsn>; 118*4882a593Smuzhiyun pinctrl-1 = <&uart1_gpios>; 119*4882a593Smuzhiyun BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; 120*4882a593Smuzhiyun BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; 121*4882a593Smuzhiyun BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; 122*4882a593Smuzhiyun status = "okay"; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun&combphy1_usq { 127*4882a593Smuzhiyun assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 128*4882a593Smuzhiyun assigned-clock-rates = <100000000>; 129*4882a593Smuzhiyun status = "okay"; 130*4882a593Smuzhiyun}; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun&combphy2_psq { 133*4882a593Smuzhiyun status = "okay"; 134*4882a593Smuzhiyun}; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun&csi2_dphy_hw { 137*4882a593Smuzhiyun status = "okay"; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun&csi2_dphy0 { 141*4882a593Smuzhiyun status = "okay"; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun ports { 144*4882a593Smuzhiyun #address-cells = <1>; 145*4882a593Smuzhiyun #size-cells = <0>; 146*4882a593Smuzhiyun port@0 { 147*4882a593Smuzhiyun reg = <0>; 148*4882a593Smuzhiyun #address-cells = <1>; 149*4882a593Smuzhiyun #size-cells = <0>; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun mipi_in_ucam0: endpoint@1 { 152*4882a593Smuzhiyun reg = <1>; 153*4882a593Smuzhiyun remote-endpoint = <&gc4c33_out>; 154*4882a593Smuzhiyun data-lanes = <1 2>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun mipi_in_ucam1: endpoint@2 { 158*4882a593Smuzhiyun reg = <2>; 159*4882a593Smuzhiyun remote-endpoint = <&gc8034_out>; 160*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun port@1 { 165*4882a593Smuzhiyun reg = <1>; 166*4882a593Smuzhiyun #address-cells = <1>; 167*4882a593Smuzhiyun #size-cells = <0>; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun csidphy_out: endpoint@1 { 170*4882a593Smuzhiyun reg = <1>; 171*4882a593Smuzhiyun remote-endpoint = <&isp0_in>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun}; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun&gmac1 { 178*4882a593Smuzhiyun phy-mode = "rgmii"; 179*4882a593Smuzhiyun clock_in_out = "input"; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; 182*4882a593Smuzhiyun snps,reset-active-low; 183*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 184*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 187*4882a593Smuzhiyun assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun pinctrl-names = "default"; 190*4882a593Smuzhiyun pinctrl-0 = <&gmac1m1_miim 191*4882a593Smuzhiyun &gmac1m1_tx_bus2 192*4882a593Smuzhiyun &gmac1m1_rx_bus2 193*4882a593Smuzhiyun &gmac1m1_rgmii_clk 194*4882a593Smuzhiyun &gmac1m1_rgmii_bus 195*4882a593Smuzhiyun &gmac1m1_clkinout>; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun tx_delay = <0x4f>; 198*4882a593Smuzhiyun rx_delay = <0x2d>; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun phy-handle = <&rgmii_phy1>; 201*4882a593Smuzhiyun status = "okay"; 202*4882a593Smuzhiyun}; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun&i2c2{ 205*4882a593Smuzhiyun status = "okay"; 206*4882a593Smuzhiyun pinctrl-names = "default"; 207*4882a593Smuzhiyun pinctrl-0 = <&i2c2m1_xfer>; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun gc8034: gc8034@37 { 210*4882a593Smuzhiyun status = "okay"; 211*4882a593Smuzhiyun compatible = "galaxycore,gc8034"; 212*4882a593Smuzhiyun reg = <0x37>; 213*4882a593Smuzhiyun clocks = <&cru CLK_CIF_OUT>; 214*4882a593Smuzhiyun clock-names = "xvclk"; 215*4882a593Smuzhiyun power-domains = <&power RK3568_PD_VI>; 216*4882a593Smuzhiyun pinctrl-names = "default"; 217*4882a593Smuzhiyun pinctrl-0 = <&cif_clk>; 218*4882a593Smuzhiyun /*pwren-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;*/ 219*4882a593Smuzhiyun reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; 220*4882a593Smuzhiyun pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; 221*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 222*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 223*4882a593Smuzhiyun rockchip,camera-module-name = "RK-CMK-8M-2-v1"; 224*4882a593Smuzhiyun rockchip,camera-module-lens-name = "CK8401"; 225*4882a593Smuzhiyun port { 226*4882a593Smuzhiyun gc8034_out: endpoint { 227*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam1>; 228*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun gc4c33: gc4c33@29 { 234*4882a593Smuzhiyun status = "okay"; 235*4882a593Smuzhiyun compatible = "galaxycore,gc4c33"; 236*4882a593Smuzhiyun reg = <0x29>; 237*4882a593Smuzhiyun clocks = <&cru CLK_CIF_OUT>; 238*4882a593Smuzhiyun clock-names = "xvclk"; 239*4882a593Smuzhiyun power-domains = <&power RK3568_PD_VI>; 240*4882a593Smuzhiyun pinctrl-names = "default"; 241*4882a593Smuzhiyun pinctrl-0 = <&cif_clk>; 242*4882a593Smuzhiyun /*pwren-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;*/ 243*4882a593Smuzhiyun reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; 244*4882a593Smuzhiyun pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 245*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 246*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 247*4882a593Smuzhiyun rockchip,camera-module-name = "PCORW0009A"; 248*4882a593Smuzhiyun rockchip,camera-module-lens-name = "40IRC-4M"; 249*4882a593Smuzhiyun port { 250*4882a593Smuzhiyun gc4c33_out: endpoint { 251*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam0>; 252*4882a593Smuzhiyun data-lanes = <1 2>; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun}; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun&mdio1 { 259*4882a593Smuzhiyun rgmii_phy1: phy@0 { 260*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 261*4882a593Smuzhiyun reg = <0x0>; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun}; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun&pwm15 { 266*4882a593Smuzhiyun compatible = "rockchip,remotectl-pwm"; 267*4882a593Smuzhiyun pinctrl-names = "default"; 268*4882a593Smuzhiyun pinctrl-0 = <&pwm15m1_pins>; 269*4882a593Smuzhiyun remote_pwm_id = <3>; 270*4882a593Smuzhiyun handle_cpu_id = <1>; 271*4882a593Smuzhiyun remote_support_psci = <0>; 272*4882a593Smuzhiyun status = "okay"; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun ir_key1 { 275*4882a593Smuzhiyun rockchip,usercode = <0x4040>; 276*4882a593Smuzhiyun rockchip,key_table = 277*4882a593Smuzhiyun <0xf2 KEY_REPLY>, 278*4882a593Smuzhiyun <0xba KEY_BACK>, 279*4882a593Smuzhiyun <0xf4 KEY_UP>, 280*4882a593Smuzhiyun <0xf1 KEY_DOWN>, 281*4882a593Smuzhiyun <0xef KEY_LEFT>, 282*4882a593Smuzhiyun <0xee KEY_RIGHT>, 283*4882a593Smuzhiyun <0xbd KEY_HOME>, 284*4882a593Smuzhiyun <0xea KEY_VOLUMEUP>, 285*4882a593Smuzhiyun <0xe3 KEY_VOLUMEDOWN>, 286*4882a593Smuzhiyun <0xe2 KEY_SEARCH>, 287*4882a593Smuzhiyun <0xb2 KEY_POWER>, 288*4882a593Smuzhiyun <0xbc KEY_MUTE>, 289*4882a593Smuzhiyun <0xec KEY_MENU>, 290*4882a593Smuzhiyun <0xbf 0x190>, 291*4882a593Smuzhiyun <0xe0 0x191>, 292*4882a593Smuzhiyun <0xe1 0x192>, 293*4882a593Smuzhiyun <0xe9 183>, 294*4882a593Smuzhiyun <0xe6 248>, 295*4882a593Smuzhiyun <0xe8 185>, 296*4882a593Smuzhiyun <0xe7 186>, 297*4882a593Smuzhiyun <0xf0 388>, 298*4882a593Smuzhiyun <0xbe 0x175>; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun ir_key2 { 302*4882a593Smuzhiyun rockchip,usercode = <0xff00>; 303*4882a593Smuzhiyun rockchip,key_table = 304*4882a593Smuzhiyun <0xf9 KEY_HOME>, 305*4882a593Smuzhiyun <0xbf KEY_BACK>, 306*4882a593Smuzhiyun <0xfb KEY_MENU>, 307*4882a593Smuzhiyun <0xaa KEY_REPLY>, 308*4882a593Smuzhiyun <0xb9 KEY_UP>, 309*4882a593Smuzhiyun <0xe9 KEY_DOWN>, 310*4882a593Smuzhiyun <0xb8 KEY_LEFT>, 311*4882a593Smuzhiyun <0xea KEY_RIGHT>, 312*4882a593Smuzhiyun <0xeb KEY_VOLUMEDOWN>, 313*4882a593Smuzhiyun <0xef KEY_VOLUMEUP>, 314*4882a593Smuzhiyun <0xf7 KEY_MUTE>, 315*4882a593Smuzhiyun <0xe7 KEY_POWER>, 316*4882a593Smuzhiyun <0xfc KEY_POWER>, 317*4882a593Smuzhiyun <0xa9 KEY_VOLUMEDOWN>, 318*4882a593Smuzhiyun <0xa8 KEY_PLAYPAUSE>, 319*4882a593Smuzhiyun <0xe0 KEY_VOLUMEDOWN>, 320*4882a593Smuzhiyun <0xa5 KEY_VOLUMEDOWN>, 321*4882a593Smuzhiyun <0xab 183>, 322*4882a593Smuzhiyun <0xb7 388>, 323*4882a593Smuzhiyun <0xe8 388>, 324*4882a593Smuzhiyun <0xf8 184>, 325*4882a593Smuzhiyun <0xaf 185>, 326*4882a593Smuzhiyun <0xed KEY_VOLUMEDOWN>, 327*4882a593Smuzhiyun <0xee 186>, 328*4882a593Smuzhiyun <0xb3 KEY_VOLUMEDOWN>, 329*4882a593Smuzhiyun <0xf1 KEY_VOLUMEDOWN>, 330*4882a593Smuzhiyun <0xf2 KEY_VOLUMEDOWN>, 331*4882a593Smuzhiyun <0xf3 KEY_SEARCH>, 332*4882a593Smuzhiyun <0xb4 KEY_VOLUMEDOWN>, 333*4882a593Smuzhiyun <0xa4 KEY_SETUP>, 334*4882a593Smuzhiyun <0xbe KEY_SEARCH>; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun ir_key3 { 338*4882a593Smuzhiyun rockchip,usercode = <0x1dcc>; 339*4882a593Smuzhiyun rockchip,key_table = 340*4882a593Smuzhiyun <0xee KEY_REPLY>, 341*4882a593Smuzhiyun <0xf0 KEY_BACK>, 342*4882a593Smuzhiyun <0xf8 KEY_UP>, 343*4882a593Smuzhiyun <0xbb KEY_DOWN>, 344*4882a593Smuzhiyun <0xef KEY_LEFT>, 345*4882a593Smuzhiyun <0xed KEY_RIGHT>, 346*4882a593Smuzhiyun <0xfc KEY_HOME>, 347*4882a593Smuzhiyun <0xf1 KEY_VOLUMEUP>, 348*4882a593Smuzhiyun <0xfd KEY_VOLUMEDOWN>, 349*4882a593Smuzhiyun <0xb7 KEY_SEARCH>, 350*4882a593Smuzhiyun <0xff KEY_POWER>, 351*4882a593Smuzhiyun <0xf3 KEY_MUTE>, 352*4882a593Smuzhiyun <0xbf KEY_MENU>, 353*4882a593Smuzhiyun <0xf9 0x191>, 354*4882a593Smuzhiyun <0xf5 0x192>, 355*4882a593Smuzhiyun <0xb3 388>, 356*4882a593Smuzhiyun <0xbe KEY_1>, 357*4882a593Smuzhiyun <0xba KEY_2>, 358*4882a593Smuzhiyun <0xb2 KEY_3>, 359*4882a593Smuzhiyun <0xbd KEY_4>, 360*4882a593Smuzhiyun <0xf9 KEY_5>, 361*4882a593Smuzhiyun <0xb1 KEY_6>, 362*4882a593Smuzhiyun <0xfc KEY_7>, 363*4882a593Smuzhiyun <0xf8 KEY_8>, 364*4882a593Smuzhiyun <0xb0 KEY_9>, 365*4882a593Smuzhiyun <0xb6 KEY_0>, 366*4882a593Smuzhiyun <0xb5 KEY_BACKSPACE>; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun}; 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun/* Need to be modified according to the actual hardware */ 371*4882a593Smuzhiyun&pmu_io_domains { 372*4882a593Smuzhiyun status = "okay"; 373*4882a593Smuzhiyun pmuio2-supply = <&vcc_3v3>; 374*4882a593Smuzhiyun vccio1-supply = <&vcc_3v3>; 375*4882a593Smuzhiyun vccio3-supply = <&vcc_3v3>; 376*4882a593Smuzhiyun vccio4-supply = <&vcc_3v3>; 377*4882a593Smuzhiyun vccio5-supply = <&vcc_3v3>; 378*4882a593Smuzhiyun vccio6-supply = <&vcc_3v3>; 379*4882a593Smuzhiyun vccio7-supply = <&vcc_3v3>; 380*4882a593Smuzhiyun}; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun&rkisp { 383*4882a593Smuzhiyun status = "okay"; 384*4882a593Smuzhiyun}; 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun&rkisp_mmu { 387*4882a593Smuzhiyun status = "okay"; 388*4882a593Smuzhiyun}; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun&rkisp_vir0 { 391*4882a593Smuzhiyun status = "okay"; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun port { 394*4882a593Smuzhiyun #address-cells = <1>; 395*4882a593Smuzhiyun #size-cells = <0>; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun isp0_in: endpoint@0 { 398*4882a593Smuzhiyun reg = <0>; 399*4882a593Smuzhiyun remote-endpoint = <&csidphy_out>; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun}; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun&sata2 { 405*4882a593Smuzhiyun status = "okay"; 406*4882a593Smuzhiyun}; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun&sdmmc0 { 409*4882a593Smuzhiyun max-frequency = <50000000>; 410*4882a593Smuzhiyun no-sdio; 411*4882a593Smuzhiyun no-mmc; 412*4882a593Smuzhiyun bus-width = <4>; 413*4882a593Smuzhiyun cap-mmc-highspeed; 414*4882a593Smuzhiyun cap-sd-highspeed; 415*4882a593Smuzhiyun disable-wp; 416*4882a593Smuzhiyun //sd-uhs-sdr104; 417*4882a593Smuzhiyun vmmc-supply = <&vcc3v3_sd>; 418*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 419*4882a593Smuzhiyun pinctrl-names = "default"; 420*4882a593Smuzhiyun pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 421*4882a593Smuzhiyun status = "okay"; 422*4882a593Smuzhiyun}; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun&sdmmc1 { 425*4882a593Smuzhiyun max-frequency = <150000000>; 426*4882a593Smuzhiyun no-sd; 427*4882a593Smuzhiyun no-mmc; 428*4882a593Smuzhiyun bus-width = <4>; 429*4882a593Smuzhiyun disable-wp; 430*4882a593Smuzhiyun cap-sd-highspeed; 431*4882a593Smuzhiyun cap-sdio-irq; 432*4882a593Smuzhiyun keep-power-in-suspend; 433*4882a593Smuzhiyun non-removable; 434*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 435*4882a593Smuzhiyun pinctrl-names = "default"; 436*4882a593Smuzhiyun pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; 437*4882a593Smuzhiyun sd-uhs-sdr104; 438*4882a593Smuzhiyun status = "okay"; 439*4882a593Smuzhiyun}; 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun&uart1 { 442*4882a593Smuzhiyun status = "okay"; 443*4882a593Smuzhiyun pinctrl-names = "default"; 444*4882a593Smuzhiyun pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; 445*4882a593Smuzhiyun}; 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun&u2phy0_host { 448*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 449*4882a593Smuzhiyun status = "okay"; 450*4882a593Smuzhiyun}; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun&u2phy0_otg { 453*4882a593Smuzhiyun vbus-supply = <&vcc5v0_otg>; 454*4882a593Smuzhiyun status = "okay"; 455*4882a593Smuzhiyun}; 456*4882a593Smuzhiyun 457*4882a593Smuzhiyun&u2phy1_host { 458*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 459*4882a593Smuzhiyun status = "okay"; 460*4882a593Smuzhiyun}; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun&u2phy1_otg { 463*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 464*4882a593Smuzhiyun status = "okay"; 465*4882a593Smuzhiyun}; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun&usb2phy1 { 468*4882a593Smuzhiyun status = "okay"; 469*4882a593Smuzhiyun}; 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun&usb_host0_ehci { 472*4882a593Smuzhiyun status = "okay"; 473*4882a593Smuzhiyun}; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun&usb_host0_ohci { 476*4882a593Smuzhiyun status = "okay"; 477*4882a593Smuzhiyun}; 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun&usb_host1_ehci { 480*4882a593Smuzhiyun status = "okay"; 481*4882a593Smuzhiyun}; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun&usb_host1_ohci { 484*4882a593Smuzhiyun status = "okay"; 485*4882a593Smuzhiyun}; 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun&pinctrl { 488*4882a593Smuzhiyun cam { 489*4882a593Smuzhiyun camera_pwr: camera-pwr { 490*4882a593Smuzhiyun rockchip,pins = 491*4882a593Smuzhiyun /* camera power en */ 492*4882a593Smuzhiyun <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 493*4882a593Smuzhiyun }; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun sdio-pwrseq { 497*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 498*4882a593Smuzhiyun rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 499*4882a593Smuzhiyun }; 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun wifi_32k: wifi-32k { 502*4882a593Smuzhiyun rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun }; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun usb { 507*4882a593Smuzhiyun vcc5v0_host_en: vcc5v0-host-en { 508*4882a593Smuzhiyun rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 509*4882a593Smuzhiyun }; 510*4882a593Smuzhiyun 511*4882a593Smuzhiyun vcc5v0_otg_en: vcc5v0-otg-en { 512*4882a593Smuzhiyun rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 513*4882a593Smuzhiyun }; 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun }; 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun wireless-wlan { 518*4882a593Smuzhiyun wifi_host_wake_irq: wifi-host-wake-irq { 519*4882a593Smuzhiyun rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun }; 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun wireless-bluetooth { 524*4882a593Smuzhiyun uart1_gpios: uart1-gpios { 525*4882a593Smuzhiyun rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 526*4882a593Smuzhiyun }; 527*4882a593Smuzhiyun }; 528*4882a593Smuzhiyun}; 529