xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-camera.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun/ {
7*4882a593Smuzhiyun	vcc_mipipwr: vcc-mipipwr-regulator {
8*4882a593Smuzhiyun		compatible = "regulator-fixed";
9*4882a593Smuzhiyun		gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
10*4882a593Smuzhiyun		pinctrl-names = "default";
11*4882a593Smuzhiyun		pinctrl-0 = <&mipicam_pwr>;
12*4882a593Smuzhiyun		regulator-name = "vcc_mipipwr";
13*4882a593Smuzhiyun		enable-active-high;
14*4882a593Smuzhiyun	};
15*4882a593Smuzhiyun};
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun&csi2_dphy0 {
18*4882a593Smuzhiyun	status = "okay";
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	ports {
21*4882a593Smuzhiyun		#address-cells = <1>;
22*4882a593Smuzhiyun		#size-cells = <0>;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun		port@0 {
25*4882a593Smuzhiyun			reg = <0>;
26*4882a593Smuzhiyun			#address-cells = <1>;
27*4882a593Smuzhiyun			#size-cells = <0>;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
30*4882a593Smuzhiyun				reg = <1>;
31*4882a593Smuzhiyun				remote-endpoint = <&ov13855_out0>;
32*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
33*4882a593Smuzhiyun			};
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun		port@1 {
37*4882a593Smuzhiyun			reg = <1>;
38*4882a593Smuzhiyun			#address-cells = <1>;
39*4882a593Smuzhiyun			#size-cells = <0>;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun			csidphy0_out: endpoint@0 {
42*4882a593Smuzhiyun				reg = <0>;
43*4882a593Smuzhiyun				remote-endpoint = <&mipi0_csi2_input>;
44*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
45*4882a593Smuzhiyun			};
46*4882a593Smuzhiyun		};
47*4882a593Smuzhiyun	};
48*4882a593Smuzhiyun};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun&csi2_dphy4 {
51*4882a593Smuzhiyun	status = "okay";
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	ports {
54*4882a593Smuzhiyun		#address-cells = <1>;
55*4882a593Smuzhiyun		#size-cells = <0>;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun		port@0 {
58*4882a593Smuzhiyun			reg = <0>;
59*4882a593Smuzhiyun			#address-cells = <1>;
60*4882a593Smuzhiyun			#size-cells = <0>;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@1 {
63*4882a593Smuzhiyun				reg = <1>;
64*4882a593Smuzhiyun				remote-endpoint = <&gc8034_out0>;
65*4882a593Smuzhiyun				data-lanes = <1 2>;
66*4882a593Smuzhiyun			};
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun		port@1 {
70*4882a593Smuzhiyun			reg = <1>;
71*4882a593Smuzhiyun			#address-cells = <1>;
72*4882a593Smuzhiyun			#size-cells = <0>;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun			csidphy4_out: endpoint@0 {
75*4882a593Smuzhiyun				reg = <0>;
76*4882a593Smuzhiyun				remote-endpoint = <&mipi2_csi2_input>;
77*4882a593Smuzhiyun				data-lanes = <1 2>;
78*4882a593Smuzhiyun			};
79*4882a593Smuzhiyun		};
80*4882a593Smuzhiyun	};
81*4882a593Smuzhiyun};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun&i2c4 {
84*4882a593Smuzhiyun	status = "okay";
85*4882a593Smuzhiyun	pinctrl-names = "default";
86*4882a593Smuzhiyun	pinctrl-0 = <&i2c4m0_xfer>;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun	dw9763: dw9763@c {
89*4882a593Smuzhiyun		compatible = "dongwoon,dw9763";
90*4882a593Smuzhiyun		status = "okay";
91*4882a593Smuzhiyun		reg = <0x0c>;
92*4882a593Smuzhiyun		rockchip,vcm-max-current = <120>;
93*4882a593Smuzhiyun		rockchip,vcm-start-current = <20>;
94*4882a593Smuzhiyun		rockchip,vcm-rated-current = <90>;
95*4882a593Smuzhiyun		rockchip,vcm-step-mode = <3>;
96*4882a593Smuzhiyun		rockchip,vcm-t-src = <0x20>;
97*4882a593Smuzhiyun		rockchip,vcm-t-div = <1>;
98*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
99*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
100*4882a593Smuzhiyun	};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun	ov13855: ov13855@36 {
103*4882a593Smuzhiyun		status = "okay";
104*4882a593Smuzhiyun		compatible = "ovti,ov13855";
105*4882a593Smuzhiyun		reg = <0x36>;
106*4882a593Smuzhiyun		clocks = <&cru CLK_CAM0_OUT2IO>;
107*4882a593Smuzhiyun		clock-names = "xvclk";
108*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
109*4882a593Smuzhiyun		avdd-supply = <&vcc2v8_dvp>;
110*4882a593Smuzhiyun		dovdd-supply = <&vcc_mipipwr>;
111*4882a593Smuzhiyun		dvdd-supply = <&vcc1v2_dvp>;
112*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
113*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
114*4882a593Smuzhiyun		rockchip,camera-module-name = "KYT-10203-v1";
115*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "default";
116*4882a593Smuzhiyun		lens-focus = <&dw9763>;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun		port {
119*4882a593Smuzhiyun			ov13855_out0: endpoint {
120*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
121*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
122*4882a593Smuzhiyun			};
123*4882a593Smuzhiyun		};
124*4882a593Smuzhiyun	};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun	gc8034: gc8034@37 {
127*4882a593Smuzhiyun		compatible = "galaxycore,gc8034";
128*4882a593Smuzhiyun		status = "okay";
129*4882a593Smuzhiyun		reg = <0x37>;
130*4882a593Smuzhiyun		clocks = <&cru CLK_CAM0_OUT2IO>;
131*4882a593Smuzhiyun		clock-names = "xvclk";
132*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
133*4882a593Smuzhiyun		avdd-supply = <&vcc2v8_dvp>;
134*4882a593Smuzhiyun		dovdd-supply = <&vcc_mipipwr>;
135*4882a593Smuzhiyun		dvdd-supply = <&vcc1v2_dvp>;
136*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
137*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
138*4882a593Smuzhiyun		rockchip,camera-module-name = "KYT-10203-v1";
139*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "default";
140*4882a593Smuzhiyun		port {
141*4882a593Smuzhiyun			gc8034_out0: endpoint {
142*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam1>;
143*4882a593Smuzhiyun				data-lanes = <1 2>;
144*4882a593Smuzhiyun			};
145*4882a593Smuzhiyun		};
146*4882a593Smuzhiyun	};
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun&csi2_dphy0_hw {
150*4882a593Smuzhiyun	status = "okay";
151*4882a593Smuzhiyun};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun&csi2_dphy1_hw {
154*4882a593Smuzhiyun	status = "okay";
155*4882a593Smuzhiyun};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun&mipi0_csi2 {
158*4882a593Smuzhiyun	status = "okay";
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun	ports {
161*4882a593Smuzhiyun		#address-cells = <1>;
162*4882a593Smuzhiyun		#size-cells = <0>;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun		port@0 {
165*4882a593Smuzhiyun			reg = <0>;
166*4882a593Smuzhiyun			#address-cells = <1>;
167*4882a593Smuzhiyun			#size-cells = <0>;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun			mipi0_csi2_input: endpoint@1 {
170*4882a593Smuzhiyun				reg = <1>;
171*4882a593Smuzhiyun				remote-endpoint = <&csidphy0_out>;
172*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
173*4882a593Smuzhiyun			};
174*4882a593Smuzhiyun		};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun		port@1 {
177*4882a593Smuzhiyun			reg = <1>;
178*4882a593Smuzhiyun			#address-cells = <1>;
179*4882a593Smuzhiyun			#size-cells = <0>;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun			mipi0_csi2_output: endpoint@0 {
182*4882a593Smuzhiyun				reg = <0>;
183*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in>;
184*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
185*4882a593Smuzhiyun			};
186*4882a593Smuzhiyun		};
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun&mipi2_csi2 {
191*4882a593Smuzhiyun	status = "okay";
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun	ports {
194*4882a593Smuzhiyun		#address-cells = <1>;
195*4882a593Smuzhiyun		#size-cells = <0>;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun		port@0 {
198*4882a593Smuzhiyun			reg = <0>;
199*4882a593Smuzhiyun			#address-cells = <1>;
200*4882a593Smuzhiyun			#size-cells = <0>;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun			mipi2_csi2_input: endpoint@1 {
203*4882a593Smuzhiyun				reg = <1>;
204*4882a593Smuzhiyun				remote-endpoint = <&csidphy4_out>;
205*4882a593Smuzhiyun				data-lanes = <1 2>;
206*4882a593Smuzhiyun			};
207*4882a593Smuzhiyun		};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun		port@1 {
210*4882a593Smuzhiyun			reg = <1>;
211*4882a593Smuzhiyun			#address-cells = <1>;
212*4882a593Smuzhiyun			#size-cells = <0>;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun			mipi2_csi2_output: endpoint@0 {
215*4882a593Smuzhiyun				reg = <0>;
216*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in2>;
217*4882a593Smuzhiyun				data-lanes = <1 2>;
218*4882a593Smuzhiyun			};
219*4882a593Smuzhiyun		};
220*4882a593Smuzhiyun	};
221*4882a593Smuzhiyun};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun&rkcif {
224*4882a593Smuzhiyun	status = "okay";
225*4882a593Smuzhiyun	pinctrl-names = "default";
226*4882a593Smuzhiyun	pinctrl-0 = <&camm0_clk0_out>;
227*4882a593Smuzhiyun};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun&rkcif_mipi_lvds {
230*4882a593Smuzhiyun	status = "okay";
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun	port {
233*4882a593Smuzhiyun		cif_mipi_in: endpoint {
234*4882a593Smuzhiyun			remote-endpoint = <&mipi0_csi2_output>;
235*4882a593Smuzhiyun		};
236*4882a593Smuzhiyun	};
237*4882a593Smuzhiyun};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun&rkcif_mipi_lvds2 {
240*4882a593Smuzhiyun	status = "okay";
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun	port {
243*4882a593Smuzhiyun		cif_mipi_in2: endpoint {
244*4882a593Smuzhiyun			remote-endpoint = <&mipi2_csi2_output>;
245*4882a593Smuzhiyun		};
246*4882a593Smuzhiyun	};
247*4882a593Smuzhiyun};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf {
250*4882a593Smuzhiyun	status = "okay";
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun	port {
253*4882a593Smuzhiyun		mipi_lvds_sditf: endpoint {
254*4882a593Smuzhiyun			remote-endpoint = <&isp_vir0_in0>;
255*4882a593Smuzhiyun		};
256*4882a593Smuzhiyun	};
257*4882a593Smuzhiyun};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun&rkcif_mipi_lvds2_sditf {
260*4882a593Smuzhiyun	status = "okay";
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun	port {
263*4882a593Smuzhiyun		mipi_lvds2_sditf: endpoint {
264*4882a593Smuzhiyun			remote-endpoint = <&isp_vir0_in1>;
265*4882a593Smuzhiyun		};
266*4882a593Smuzhiyun	};
267*4882a593Smuzhiyun};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun&rkcif_mmu {
270*4882a593Smuzhiyun	status = "okay";
271*4882a593Smuzhiyun};
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun&rkisp {
274*4882a593Smuzhiyun	status = "okay";
275*4882a593Smuzhiyun};
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun&rkisp_mmu {
278*4882a593Smuzhiyun	status = "okay";
279*4882a593Smuzhiyun};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun&rkisp_vir0 {
282*4882a593Smuzhiyun	status = "okay";
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun	port {
285*4882a593Smuzhiyun		#address-cells = <1>;
286*4882a593Smuzhiyun		#size-cells = <0>;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun		isp_vir0_in0: endpoint@0 {
289*4882a593Smuzhiyun			reg = <0>;
290*4882a593Smuzhiyun			remote-endpoint = <&mipi_lvds_sditf>;
291*4882a593Smuzhiyun		};
292*4882a593Smuzhiyun		isp_vir0_in1: endpoint@1 {
293*4882a593Smuzhiyun			reg = <1>;
294*4882a593Smuzhiyun			remote-endpoint = <&mipi_lvds2_sditf>;
295*4882a593Smuzhiyun		};
296*4882a593Smuzhiyun	};
297*4882a593Smuzhiyun};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun&pinctrl {
300*4882a593Smuzhiyun	cam {
301*4882a593Smuzhiyun		mipicam_pwr: mipicam-pwr {
302*4882a593Smuzhiyun			rockchip,pins =
303*4882a593Smuzhiyun				/* camera power en */
304*4882a593Smuzhiyun				<3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
305*4882a593Smuzhiyun		};
306*4882a593Smuzhiyun	};
307*4882a593Smuzhiyun};
308