1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 8*4882a593Smuzhiyun#include "rk3562-evb2-ddr4-v10.dtsi" 9*4882a593Smuzhiyun#include "rk3562-android.dtsi" 10*4882a593Smuzhiyun#include "rk3562-rk809.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip RK3562 EVB2 DDR4 V10 Board + RK EVB BT1120 TO HDMI V10 Ext Board"; 14*4882a593Smuzhiyun compatible = "rockchip,rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi", "rockchip,rk3562"; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun&dsi { 18*4882a593Smuzhiyun status = "disabled"; 19*4882a593Smuzhiyun}; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun&dsi_in_vp0 { 22*4882a593Smuzhiyun status = "disabled"; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun/* 26*4882a593Smuzhiyun * The pins of gamc0 and bt1120 are multiplexed 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun&gmac0 { 29*4882a593Smuzhiyun status = "disabled"; 30*4882a593Smuzhiyun}; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&i2c1 { 33*4882a593Smuzhiyun clock-frequency = <400000>; 34*4882a593Smuzhiyun pinctrl-0 = <&i2c1m1_xfer>; 35*4882a593Smuzhiyun status = "okay"; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun sii9022: sii9022@39 { 38*4882a593Smuzhiyun compatible = "sil,sii9022"; 39*4882a593Smuzhiyun reg = <0x39>; 40*4882a593Smuzhiyun pinctrl-names = "default"; 41*4882a593Smuzhiyun pinctrl-0 = <&sii902x_hdmi_int>; 42*4882a593Smuzhiyun interrupt-parent = <&gpio4>; 43*4882a593Smuzhiyun interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>; 44*4882a593Smuzhiyun reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; 45*4882a593Smuzhiyun enable-gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * MEDIA_BUS_FMT_YUYV8_1X16 for bt1120 48*4882a593Smuzhiyun * MEDIA_BUS_FMT_UYVY8_2X8 for bt656 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_YUYV8_1X16>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun ports { 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <0>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun port@0 { 57*4882a593Smuzhiyun reg = <0>; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun sii9022_in_rgb: endpoint { 60*4882a593Smuzhiyun remote-endpoint = <&rgb_out_sii9022>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun}; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun&pinctrl { 68*4882a593Smuzhiyun sii902x { 69*4882a593Smuzhiyun sii902x_hdmi_int: sii902x-hdmi-int { 70*4882a593Smuzhiyun rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun}; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&rgb { 76*4882a593Smuzhiyun status = "okay"; 77*4882a593Smuzhiyun pinctrl-names = "default"; 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * <&bt1120_pins> for bt1120 80*4882a593Smuzhiyun * <&bt656_pins> for bt656 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun pinctrl-0 = <&bt1120_pins>; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun ports { 85*4882a593Smuzhiyun port@1 { 86*4882a593Smuzhiyun reg = <1>; 87*4882a593Smuzhiyun #address-cells = <1>; 88*4882a593Smuzhiyun #size-cells = <0>; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun rgb_out_sii9022: endpoint@0 { 91*4882a593Smuzhiyun reg = <0>; 92*4882a593Smuzhiyun remote-endpoint = <&sii9022_in_rgb>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun}; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun&rgb_in_vp0 { 99*4882a593Smuzhiyun status = "okay"; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&video_phy { 103*4882a593Smuzhiyun status = "disabled"; 104*4882a593Smuzhiyun}; 105