xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-dual-camera.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "rk3562-evb2-ddr4-v10.dtsi"
8*4882a593Smuzhiyun#include "rk3562-android.dtsi"
9*4882a593Smuzhiyun#include "rk3562-rk809.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	vcc_mipicsi0: vcc-mipicsi0-regulator {
13*4882a593Smuzhiyun		compatible = "regulator-fixed";
14*4882a593Smuzhiyun		gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
15*4882a593Smuzhiyun		pinctrl-names = "default";
16*4882a593Smuzhiyun		pinctrl-0 = <&mipicsi0_pwr>;
17*4882a593Smuzhiyun		regulator-name = "vcc_mipicsi0";
18*4882a593Smuzhiyun		enable-active-high;
19*4882a593Smuzhiyun		regulator-always-on;
20*4882a593Smuzhiyun		regulator-boot-on;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun&csi2_dphy1 {
25*4882a593Smuzhiyun	status = "okay";
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	ports {
28*4882a593Smuzhiyun		#address-cells = <1>;
29*4882a593Smuzhiyun		#size-cells = <0>;
30*4882a593Smuzhiyun		port@0 {
31*4882a593Smuzhiyun			reg = <0>;
32*4882a593Smuzhiyun			#address-cells = <1>;
33*4882a593Smuzhiyun			#size-cells = <0>;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
36*4882a593Smuzhiyun				reg = <1>;
37*4882a593Smuzhiyun				remote-endpoint = <&gc8034_out0>;
38*4882a593Smuzhiyun				data-lanes = <1 2>;
39*4882a593Smuzhiyun			};
40*4882a593Smuzhiyun		};
41*4882a593Smuzhiyun		port@1 {
42*4882a593Smuzhiyun			reg = <1>;
43*4882a593Smuzhiyun			#address-cells = <1>;
44*4882a593Smuzhiyun			#size-cells = <0>;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun			csidphy1_out: endpoint@0 {
47*4882a593Smuzhiyun				reg = <0>;
48*4882a593Smuzhiyun				remote-endpoint = <&mipi0_csi2_input>;
49*4882a593Smuzhiyun			};
50*4882a593Smuzhiyun		};
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun&csi2_dphy2 {
55*4882a593Smuzhiyun	status = "okay";
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	ports {
58*4882a593Smuzhiyun		#address-cells = <1>;
59*4882a593Smuzhiyun		#size-cells = <0>;
60*4882a593Smuzhiyun		port@0 {
61*4882a593Smuzhiyun			reg = <0>;
62*4882a593Smuzhiyun			#address-cells = <1>;
63*4882a593Smuzhiyun			#size-cells = <0>;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@1 {
66*4882a593Smuzhiyun				reg = <1>;
67*4882a593Smuzhiyun				remote-endpoint = <&ov5695_out0>;
68*4882a593Smuzhiyun				data-lanes = <1 2>;
69*4882a593Smuzhiyun			};
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun		port@1 {
72*4882a593Smuzhiyun			reg = <1>;
73*4882a593Smuzhiyun			#address-cells = <1>;
74*4882a593Smuzhiyun			#size-cells = <0>;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun			csidphy2_out: endpoint@0 {
77*4882a593Smuzhiyun				reg = <0>;
78*4882a593Smuzhiyun				remote-endpoint = <&mipi1_csi2_input>;
79*4882a593Smuzhiyun			};
80*4882a593Smuzhiyun		};
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun&i2c4 {
85*4882a593Smuzhiyun	status = "okay";
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	dw9714: dw9714@c {
88*4882a593Smuzhiyun		compatible = "dongwoon,dw9714";
89*4882a593Smuzhiyun		status = "okay";
90*4882a593Smuzhiyun		reg = <0x0c>;
91*4882a593Smuzhiyun		rockchip,vcm-start-current = <10>;
92*4882a593Smuzhiyun		rockchip,vcm-rated-current = <85>;
93*4882a593Smuzhiyun		rockchip,vcm-step-mode = <5>;
94*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
95*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
96*4882a593Smuzhiyun	};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun	gc8034: gc8034@37 {
99*4882a593Smuzhiyun		compatible = "galaxycore,gc8034";
100*4882a593Smuzhiyun		reg = <0x37>;
101*4882a593Smuzhiyun		clocks = <&cru CLK_CAM0_OUT2IO>;
102*4882a593Smuzhiyun		clock-names = "xvclk";
103*4882a593Smuzhiyun		pinctrl-names = "default";
104*4882a593Smuzhiyun		pinctrl-0 = <&camm0_clk0_out>;
105*4882a593Smuzhiyun		reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
106*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
107*4882a593Smuzhiyun		// dvdd-supply = <&vcc_mipicsi0>;
108*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
109*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
110*4882a593Smuzhiyun		rockchip,camera-module-name = "RK-CMK-8M-2-v1";
111*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "CK8401";
112*4882a593Smuzhiyun		lens-focus = <&dw9714>;
113*4882a593Smuzhiyun		port {
114*4882a593Smuzhiyun			gc8034_out0: endpoint {
115*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
116*4882a593Smuzhiyun				data-lanes = <1 2>;
117*4882a593Smuzhiyun			};
118*4882a593Smuzhiyun		};
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	ov5695: ov5695@36 {
122*4882a593Smuzhiyun		compatible = "ovti,ov5695";
123*4882a593Smuzhiyun		reg = <0x36>;
124*4882a593Smuzhiyun		clocks = <&cru CLK_CAM1_OUT2IO>;
125*4882a593Smuzhiyun		clock-names = "xvclk";
126*4882a593Smuzhiyun		pinctrl-names = "default";
127*4882a593Smuzhiyun		pinctrl-0 = <&camm0_clk1_out>;
128*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>;
129*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
130*4882a593Smuzhiyun		// dvdd-supply = <&vcc_mipicsi2>;
131*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
132*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
133*4882a593Smuzhiyun		rockchip,camera-module-name = "TongJu";
134*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "CHT842-MD";
135*4882a593Smuzhiyun		port {
136*4882a593Smuzhiyun			ov5695_out0: endpoint {
137*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam1>;
138*4882a593Smuzhiyun				data-lanes = <1 2>;
139*4882a593Smuzhiyun			};
140*4882a593Smuzhiyun		};
141*4882a593Smuzhiyun	};
142*4882a593Smuzhiyun};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun&csi2_dphy0_hw {
145*4882a593Smuzhiyun	status = "okay";
146*4882a593Smuzhiyun};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun&mipi0_csi2 {
149*4882a593Smuzhiyun	status = "okay";
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun	ports {
152*4882a593Smuzhiyun		#address-cells = <1>;
153*4882a593Smuzhiyun		#size-cells = <0>;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun		port@0 {
156*4882a593Smuzhiyun			reg = <0>;
157*4882a593Smuzhiyun			#address-cells = <1>;
158*4882a593Smuzhiyun			#size-cells = <0>;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun			mipi0_csi2_input: endpoint@1 {
161*4882a593Smuzhiyun				reg = <1>;
162*4882a593Smuzhiyun				remote-endpoint = <&csidphy1_out>;
163*4882a593Smuzhiyun			};
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun		port@1 {
167*4882a593Smuzhiyun			reg = <1>;
168*4882a593Smuzhiyun			#address-cells = <1>;
169*4882a593Smuzhiyun			#size-cells = <0>;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun			mipi0_csi2_output: endpoint@0 {
172*4882a593Smuzhiyun				reg = <0>;
173*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in0>;
174*4882a593Smuzhiyun			};
175*4882a593Smuzhiyun		};
176*4882a593Smuzhiyun	};
177*4882a593Smuzhiyun};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun&mipi1_csi2 {
180*4882a593Smuzhiyun	status = "okay";
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	ports {
183*4882a593Smuzhiyun		#address-cells = <1>;
184*4882a593Smuzhiyun		#size-cells = <0>;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun		port@0 {
187*4882a593Smuzhiyun			reg = <0>;
188*4882a593Smuzhiyun			#address-cells = <1>;
189*4882a593Smuzhiyun			#size-cells = <0>;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun			mipi1_csi2_input: endpoint@1 {
192*4882a593Smuzhiyun				reg = <1>;
193*4882a593Smuzhiyun				remote-endpoint = <&csidphy2_out>;
194*4882a593Smuzhiyun			};
195*4882a593Smuzhiyun		};
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun		port@1 {
198*4882a593Smuzhiyun			reg = <1>;
199*4882a593Smuzhiyun			#address-cells = <1>;
200*4882a593Smuzhiyun			#size-cells = <0>;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun			mipi1_csi2_output: endpoint@0 {
203*4882a593Smuzhiyun				reg = <0>;
204*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in1>;
205*4882a593Smuzhiyun			};
206*4882a593Smuzhiyun		};
207*4882a593Smuzhiyun	};
208*4882a593Smuzhiyun};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun&rkcif {
211*4882a593Smuzhiyun	status = "okay";
212*4882a593Smuzhiyun};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun&rkcif_mipi_lvds {
215*4882a593Smuzhiyun	status = "okay";
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun	port {
218*4882a593Smuzhiyun		cif_mipi_in0: endpoint {
219*4882a593Smuzhiyun			remote-endpoint = <&mipi0_csi2_output>;
220*4882a593Smuzhiyun		};
221*4882a593Smuzhiyun	};
222*4882a593Smuzhiyun};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun&rkcif_mipi_lvds1 {
225*4882a593Smuzhiyun	status = "okay";
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun	port {
228*4882a593Smuzhiyun		cif_mipi_in1: endpoint {
229*4882a593Smuzhiyun			remote-endpoint = <&mipi1_csi2_output>;
230*4882a593Smuzhiyun		};
231*4882a593Smuzhiyun	};
232*4882a593Smuzhiyun};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf {
235*4882a593Smuzhiyun	status = "okay";
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun	port {
238*4882a593Smuzhiyun		mipi_lvds_sditf: endpoint {
239*4882a593Smuzhiyun			remote-endpoint = <&isp_vir0>;
240*4882a593Smuzhiyun		};
241*4882a593Smuzhiyun	};
242*4882a593Smuzhiyun};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun&rkcif_mipi_lvds1_sditf {
245*4882a593Smuzhiyun	status = "okay";
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun	port {
248*4882a593Smuzhiyun		mipi_lvds1_sditf: endpoint {
249*4882a593Smuzhiyun			remote-endpoint = <&isp_vir1>;
250*4882a593Smuzhiyun		};
251*4882a593Smuzhiyun	};
252*4882a593Smuzhiyun};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun&rkcif_mmu {
255*4882a593Smuzhiyun	status = "okay";
256*4882a593Smuzhiyun};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun&rkisp {
259*4882a593Smuzhiyun	status = "okay";
260*4882a593Smuzhiyun};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun&rkisp_mmu {
263*4882a593Smuzhiyun	status = "okay";
264*4882a593Smuzhiyun};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun&rkisp_vir0 {
267*4882a593Smuzhiyun	status = "okay";
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun	port {
270*4882a593Smuzhiyun		#address-cells = <1>;
271*4882a593Smuzhiyun		#size-cells = <0>;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun		isp_vir0: endpoint@0 {
274*4882a593Smuzhiyun			reg = <0>;
275*4882a593Smuzhiyun			remote-endpoint = <&mipi_lvds_sditf>;
276*4882a593Smuzhiyun		};
277*4882a593Smuzhiyun	};
278*4882a593Smuzhiyun};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun&rkisp_vir1 {
281*4882a593Smuzhiyun	status = "okay";
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun	port {
284*4882a593Smuzhiyun		#address-cells = <1>;
285*4882a593Smuzhiyun		#size-cells = <0>;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun		isp_vir1: endpoint@1 {
288*4882a593Smuzhiyun			reg = <1>;
289*4882a593Smuzhiyun			remote-endpoint = <&mipi_lvds1_sditf>;
290*4882a593Smuzhiyun		};
291*4882a593Smuzhiyun	};
292*4882a593Smuzhiyun};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun&pinctrl {
295*4882a593Smuzhiyun	cam {
296*4882a593Smuzhiyun		mipicsi0_pwr: mipicsi0-pwr {
297*4882a593Smuzhiyun			rockchip,pins =
298*4882a593Smuzhiyun				/* camera power en */
299*4882a593Smuzhiyun				<4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
300*4882a593Smuzhiyun		};
301*4882a593Smuzhiyun	};
302*4882a593Smuzhiyun};
303*4882a593Smuzhiyun
304