xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3562-evb2-cam.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
 *
 */

/ {
	vcc_mipicsi0: vcc-mipicsi0-regulator {
		compatible = "regulator-fixed";
		gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&mipicsi0_pwr>;
		regulator-name = "vcc_mipicsi0";
		enable-active-high;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_mipicsi1: vcc-mipicsi1-regulator {
		compatible = "regulator-fixed";
		gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&mipicsi1_pwr>;
		regulator-name = "vcc_mipicsi1";
		enable-active-high;
		regulator-always-on;
		regulator-boot-on;
	};
};

&csi2_dphy0 {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi_in_ucam0: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&gc8034_out0>;
				data-lanes = <1 2 3 4>;
			};
		};
		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			csidphy0_out: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&mipi0_csi2_input>;
			};
		};
	};
};

&csi2_dphy3 {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi_in_ucam1: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&gc8034_out1>;
				data-lanes = <1 2 3 4>;
			};
		};
		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			csidphy3_out: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&mipi2_csi2_input>;
			};
		};
	};
};

&i2c4 {
	status = "okay";

	dw9714: dw9714@c {
		compatible = "dongwoon,dw9714";
		status = "okay";
		reg = <0x0c>;
		rockchip,vcm-start-current = <10>;
		rockchip,vcm-rated-current = <85>;
		rockchip,vcm-step-mode = <5>;
		rockchip,camera-module-index = <0>;
		rockchip,camera-module-facing = "back";
	};

	gc8034: gc8034@37 {
		compatible = "galaxycore,gc8034";
		reg = <0x37>;
		clocks = <&cru CLK_CAM0_OUT2IO>;
		clock-names = "xvclk";
		pinctrl-names = "default";
		pinctrl-0 = <&camm0_clk0_out>;
		reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
		pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
		// dvdd-supply = <&vcc_mipicsi0>;
		rockchip,camera-module-index = <0>;
		rockchip,camera-module-facing = "back";
		rockchip,camera-module-name = "RK-CMK-8M-2-v1";
		rockchip,camera-module-lens-name = "CK8401";
		lens-focus = <&dw9714>;
		port {
			gc8034_out0: endpoint {
				remote-endpoint = <&mipi_in_ucam0>;
				data-lanes = <1 2 3 4>;
			};
		};
	};
};

&i2c5 {
	status = "okay";

	dw9714_1: dw9714_1@c {
		compatible = "dongwoon,dw9714";
		status = "okay";
		reg = <0x0c>;
		rockchip,vcm-start-current = <10>;
		rockchip,vcm-rated-current = <85>;
		rockchip,vcm-step-mode = <5>;
		rockchip,camera-module-index = <1>;
		rockchip,camera-module-facing = "front";
	};

	gc8034_1: gc8034_1@37 {
		compatible = "galaxycore,gc8034";
		reg = <0x37>;
		clocks = <&cru CLK_CAM2_OUT2IO>;
		clock-names = "xvclk";
		pinctrl-names = "default";
		pinctrl-0 = <&cam_clk2_out>;
		reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
		pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
		// dvdd-supply = <&vcc_mipicsi1>;
		rockchip,camera-module-index = <1>;
		rockchip,camera-module-facing = "front";
		rockchip,camera-module-name = "RK-CMK-8M-2-v1";
		rockchip,camera-module-lens-name = "CK8401";
		lens-focus = <&dw9714_1>;
		port {
			gc8034_out1: endpoint {
				remote-endpoint = <&mipi_in_ucam1>;
				data-lanes = <1 2 3 4>;
			};
		};
	};
};

&csi2_dphy0_hw {
	status = "okay";
};

&csi2_dphy1_hw {
	status = "okay";
};

&mipi0_csi2 {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi0_csi2_input: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&csidphy0_out>;
			};
		};

		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi0_csi2_output: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&cif_mipi_in0>;
			};
		};
	};
};

&mipi2_csi2 {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi2_csi2_input: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&csidphy3_out>;
			};
		};

		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi2_csi2_output: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&cif_mipi_in1>;
			};
		};
	};
};

&rkcif {
	status = "okay";
};

&rkcif_mipi_lvds {
	status = "okay";

	port {
		cif_mipi_in0: endpoint {
			remote-endpoint = <&mipi0_csi2_output>;
		};
	};
};

&rkcif_mipi_lvds2 {
	status = "okay";

	port {
		cif_mipi_in1: endpoint {
			remote-endpoint = <&mipi2_csi2_output>;
		};
	};
};

&rkcif_mipi_lvds_sditf {
	status = "okay";

	port {
		mipi_lvds_sditf: endpoint {
			remote-endpoint = <&isp_vir0>;
		};
	};
};

&rkcif_mipi_lvds2_sditf {
	status = "okay";

	port {
		mipi_lvds2_sditf: endpoint {
			remote-endpoint = <&isp_vir1>;
		};
	};
};

&rkcif_mmu {
	status = "okay";
};

&rkisp {
	status = "okay";
};

&rkisp_mmu {
	status = "okay";
};

&rkisp_vir0 {
	status = "okay";

	port {
		#address-cells = <1>;
		#size-cells = <0>;

		isp_vir0: endpoint@0 {
			reg = <0>;
			remote-endpoint = <&mipi_lvds_sditf>;
		};
		isp_vir1: endpoint@1 {
			reg = <1>;
			remote-endpoint = <&mipi_lvds2_sditf>;
		};
	};
};

&pinctrl {
	cam {
		mipicsi0_pwr: mipicsi0-pwr {
			rockchip,pins =
				/* camera power en */
				<4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
		mipicsi1_pwr: mipicsi1-pwr {
			rockchip,pins =
				/* camera1 power en */
				<3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};