1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 8*4882a593Smuzhiyun#include "rk3562-evb1-lp4x-v10.dtsi" 9*4882a593Smuzhiyun#include "rk3562-android.dtsi" 10*4882a593Smuzhiyun#include "rk3562-rk817.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB SII9022 RGB2HDMI DISPLAY Ext Board"; 14*4882a593Smuzhiyun compatible = "rockchip,rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi", "rockchip,rk3562"; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun&dsi { 18*4882a593Smuzhiyun status = "disabled"; 19*4882a593Smuzhiyun}; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun&dsi_in_vp0 { 22*4882a593Smuzhiyun status = "disabled"; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun/* 26*4882a593Smuzhiyun * The pins of gmac0 and rgb are multiplexed 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun&gmac0 { 29*4882a593Smuzhiyun status = "disabled"; 30*4882a593Smuzhiyun}; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&i2c3 { 33*4882a593Smuzhiyun clock-frequency = <400000>; 34*4882a593Smuzhiyun pinctrl-0 = <&i2c3m0_xfer>; 35*4882a593Smuzhiyun status = "okay"; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun sii9022: sii9022@39 { 38*4882a593Smuzhiyun compatible = "sil,sii9022"; 39*4882a593Smuzhiyun reg = <0x39>; 40*4882a593Smuzhiyun pinctrl-names = "default"; 41*4882a593Smuzhiyun pinctrl-0 = <&sii902x_hdmi>; 42*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 43*4882a593Smuzhiyun interrupts = <RK_PA7 IRQ_TYPE_LEVEL_HIGH>; 44*4882a593Smuzhiyun reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; 45*4882a593Smuzhiyun enable-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; 46*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_RGB888_1X24>; 47*4882a593Smuzhiyun status = "okay"; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun ports { 50*4882a593Smuzhiyun #address-cells = <1>; 51*4882a593Smuzhiyun #size-cells = <0>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun port@0 { 54*4882a593Smuzhiyun reg = <0>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun sii9022_in_rgb: endpoint { 57*4882a593Smuzhiyun remote-endpoint = <&rgb_out_sii9022>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun}; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun/* 65*4882a593Smuzhiyun * The pins of pcie2x1/pdm_codec and rgb are multiplexed 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun&pcie2x1 { 68*4882a593Smuzhiyun status = "disabled"; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&pdm_codec { 72*4882a593Smuzhiyun status = "disabled"; 73*4882a593Smuzhiyun}; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&pinctrl { 76*4882a593Smuzhiyun sii902x { 77*4882a593Smuzhiyun sii902x_hdmi: sii902x-hdmi { 78*4882a593Smuzhiyun rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun}; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun&rgb { 84*4882a593Smuzhiyun status = "okay"; 85*4882a593Smuzhiyun pinctrl-names = "default"; 86*4882a593Smuzhiyun pinctrl-0 = <&vo_pins>; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun ports { 89*4882a593Smuzhiyun port@1 { 90*4882a593Smuzhiyun reg = <1>; 91*4882a593Smuzhiyun #address-cells = <1>; 92*4882a593Smuzhiyun #size-cells = <0>; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun rgb_out_sii9022: endpoint@0 { 95*4882a593Smuzhiyun reg = <0>; 96*4882a593Smuzhiyun remote-endpoint = <&sii9022_in_rgb>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&rgb_in_vp0 { 103*4882a593Smuzhiyun status = "okay"; 104*4882a593Smuzhiyun}; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun&route_rgb { 107*4882a593Smuzhiyun status = "disabled"; 108*4882a593Smuzhiyun connect = <&vp0_out_rgb>; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun/* 112*4882a593Smuzhiyun * The pins of sai0/vcc_mipicsi0/u2phy_host and rgb are multiplexed 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun&sai0 { 115*4882a593Smuzhiyun status = "disabled"; 116*4882a593Smuzhiyun}; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun&u2phy_host { 119*4882a593Smuzhiyun status = "disabled"; 120*4882a593Smuzhiyun}; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun&vcc5v0_usb_host { 123*4882a593Smuzhiyun status = "disabled"; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun&vcc_mipicsi0 { 127*4882a593Smuzhiyun status = "disabled"; 128*4882a593Smuzhiyun}; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun&video_phy { 131*4882a593Smuzhiyun status = "disabled"; 132*4882a593Smuzhiyun}; 133