1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/display/media-bus-format.h> 8#include "rk3562-evb1-lp4x-v10.dtsi" 9#include "rk3562-android.dtsi" 10#include "rk3562-rk817.dtsi" 11 12/ { 13 model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB SPI+RGB PANLE DISPLAY Ext Board"; 14 compatible = "rockchip,rk3562-evb1-lp4x-v10-rgb-k350c4516t", "rockchip,rk3562"; 15 16 spi_gpio: spi-gpio { 17 compatible = "spi-gpio"; 18 #address-cells = <0x1>; 19 #size-cells = <0x0>; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&spi_gpio_pins>; 22 spi-delay-us = <10>; 23 status = "okay"; 24 25 sck-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; 26 miso-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 27 mosi-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 28 cs-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; 29 num-chipselects = <1>; 30 31 /* 32 * 320x480 RGB/MCU screen K350C4516T 33 */ 34 panel: panel { 35 compatible = "simple-panel-spi"; 36 reg = <0>; 37 bus-format = <MEDIA_BUS_FMT_RGB666_1X18>; 38 backlight = <&backlight>; 39 enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; 40 enable-delay-ms = <20>; 41 reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; 42 reset-delay-ms = <10>; 43 prepare-delay-ms = <20>; 44 unprepare-delay-ms = <20>; 45 disable-delay-ms = <20>; 46 width-mm = <217>; 47 height-mm = <136>; 48 rockchip,cmd-type = "spi"; 49 status = "okay"; 50 51 // type:0 is cmd, 1 is data 52 panel-init-sequence = [ 53 /* type delay num val1 val2 val3 */ 54 00 00 01 e0 55 01 00 01 00 56 01 00 01 07 57 01 00 01 0f 58 01 00 01 0d 59 01 00 01 1b 60 01 00 01 0a 61 01 00 01 3c 62 01 00 01 78 63 01 00 01 4a 64 01 00 01 07 65 01 00 01 0e 66 01 00 01 09 67 01 00 01 1b 68 01 00 01 1e 69 01 00 01 0f 70 00 00 01 e1 71 01 00 01 00 72 01 00 01 22 73 01 00 01 24 74 01 00 01 06 75 01 00 01 12 76 01 00 01 07 77 01 00 01 36 78 01 00 01 47 79 01 00 01 47 80 01 00 01 06 81 01 00 01 0a 82 01 00 01 07 83 01 00 01 30 84 01 00 01 37 85 01 00 01 0f 86 87 00 00 01 c0 88 01 00 01 10 89 01 00 01 10 90 91 00 00 01 c1 92 01 00 01 41 93 94 00 00 01 c5 95 01 00 01 00 96 01 00 01 22 97 01 00 01 80 98 99 00 00 01 36 100 01 00 01 48 101 102 00 00 01 3a //interface pixel format 103 01 00 01 66 // bpp cfg 104 // 3 11 105 // 16 55 106 // 18 66 107 // 24 77 108 109 00 00 01 b0 /* interface mode control */ 110 01 00 01 00 111 112 00 00 01 b1 /* frame rate 60hz */ 113 01 00 01 a0 114 01 00 01 11 115 00 00 01 b4 116 01 00 01 02 117 00 00 01 B6 118 01 00 01 32 119 01 00 01 02 120 121 00 00 01 b7 122 01 00 01 c6 123 124 00 00 01 be 125 01 00 01 00 126 01 00 01 04 127 128 00 00 01 e9 129 01 00 01 00 130 131 00 00 01 f7 132 01 00 01 a9 133 01 00 01 51 134 01 00 01 2c 135 01 00 01 82 136 137 00 78 01 11 138 00 00 01 29 139 ]; 140 141 panel-exit-sequence = [ 142 //type delay num val1 val2 val3 143 00 0a 01 28 144 00 78 01 10 145 ]; 146 147 display-timings { 148 native-mode = <&kd050fwfba002_timing>; 149 150 kd050fwfba002_timing: timing0 { 151 clock-frequency = <10453500>; 152 hactive = <320>; 153 vactive = <480>; 154 hback-porch = <10>; 155 hfront-porch = <5>; 156 vback-porch = <10>; 157 vfront-porch = <5>; 158 hsync-len = <10>; 159 vsync-len = <10>; 160 hsync-active = <0>; 161 vsync-active = <0>; 162 de-active = <0>; 163 pixelclk-active = <1>; 164 }; 165 }; 166 167 port { 168 panel_in_rgb: endpoint { 169 remote-endpoint = <&rgb_out_panel>; 170 }; 171 }; 172 }; 173 }; 174}; 175 176&backlight { 177 status = "okay"; 178 pwms = <&pwm9 0 25000 0>; 179}; 180 181&dsi { 182 status = "disabled"; 183}; 184 185&dsi_in_vp0 { 186 status = "disabled"; 187}; 188 189/* 190 * The pins of gmac0/pcie2x1 and rgb are multiplexed 191 */ 192&gmac0 { 193 status = "disabled"; 194}; 195 196&pcie2x1 { 197 status = "disabled"; 198}; 199 200&pinctrl { 201 spi_gpio { 202 spi_gpio_pins: spi-gpio-pins { 203 rockchip,pins = 204 /* spi sdo */ 205 <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, 206 /* spi sdi */ 207 <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, 208 /* spi scl */ 209 <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 210 /* spi cs */ 211 <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 212 }; 213 }; 214}; 215 216&pwm9 { 217 status = "okay"; 218}; 219 220&rgb { 221 status = "okay"; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&rgb666_pins>; 224 225 ports { 226 rgb_out: port@1 { 227 reg = <1>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 231 rgb_out_panel: endpoint@0 { 232 reg = <0>; 233 remote-endpoint = <&panel_in_rgb>; 234 }; 235 }; 236 }; 237}; 238 239&rgb_in_vp0 { 240 status = "okay"; 241}; 242 243&route_rgb { 244 status = "okay"; 245 connect = <&vp0_out_rgb>; 246}; 247 248/* 249 * The pins of sai0/vcc_mipicsi0 and rgb are multiplexed 250 */ 251&sai0 { 252 status = "disabled"; 253}; 254 255&vcc_mipicsi0 { 256 status = "disabled"; 257}; 258 259&video_phy { 260 status = "disabled"; 261}; 262 263&vop { 264 status = "okay"; 265}; 266