1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 8*4882a593Smuzhiyun#include "rk3562-evb1-lp4x-v10.dtsi" 9*4882a593Smuzhiyun#include "rk3562-android.dtsi" 10*4882a593Smuzhiyun#include "rk3562-rk817.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB MCU PANLE DISPLAY Ext Board"; 14*4882a593Smuzhiyun compatible = "rockchip,rk3562-evb1-lp4x-v10-mcu-k350c4516t", "rockchip,rk3562"; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun&backlight { 18*4882a593Smuzhiyun status = "okay"; 19*4882a593Smuzhiyun pwms = <&pwm9 0 25000 0>; 20*4882a593Smuzhiyun}; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun&dsi { 23*4882a593Smuzhiyun status = "disabled"; 24*4882a593Smuzhiyun}; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun&dsi_in_vp0 { 27*4882a593Smuzhiyun status = "disabled"; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun/* 31*4882a593Smuzhiyun * The pins of gmac0/pcie2x1 and rgb are multiplexed 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun&gmac0 { 34*4882a593Smuzhiyun status = "disabled"; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&pcie2x1 { 38*4882a593Smuzhiyun status = "disabled"; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun&pwm9 { 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun}; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun&rgb { 46*4882a593Smuzhiyun status = "okay"; 47*4882a593Smuzhiyun rockchip,data-sync-bypass; 48*4882a593Smuzhiyun pinctrl-names = "default"; 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * rgb3x8_pins_m0/rgb3x8_pins_m1 for serial mcu 51*4882a593Smuzhiyun * rgb565_pins for parallel mcu 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun pinctrl-0 = <&rgb565_pins>; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * 320x480 RGB/MCU screen K350C4516T 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun mcu_panel: mcu-panel { 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * MEDIA_BUS_FMT_RGB888_3X8 for serial mcu 61*4882a593Smuzhiyun * MEDIA_BUS_FMT_RGB565_1X16 for parallel mcu 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_RGB565_1X16>; 64*4882a593Smuzhiyun backlight = <&backlight>; 65*4882a593Smuzhiyun enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; 66*4882a593Smuzhiyun enable-delay-ms = <20>; 67*4882a593Smuzhiyun reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; 68*4882a593Smuzhiyun reset-value = <0>; 69*4882a593Smuzhiyun reset-delay-ms = <10>; 70*4882a593Smuzhiyun prepare-delay-ms = <20>; 71*4882a593Smuzhiyun unprepare-delay-ms = <20>; 72*4882a593Smuzhiyun disable-delay-ms = <20>; 73*4882a593Smuzhiyun width-mm = <217>; 74*4882a593Smuzhiyun height-mm = <136>; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun // type:0 is cmd, 1 is data 77*4882a593Smuzhiyun panel-init-sequence = [ 78*4882a593Smuzhiyun //type delay num val1 val2 val3 79*4882a593Smuzhiyun 00 00 01 e0 80*4882a593Smuzhiyun 01 00 01 00 81*4882a593Smuzhiyun 01 00 01 07 82*4882a593Smuzhiyun 01 00 01 0f 83*4882a593Smuzhiyun 01 00 01 0d 84*4882a593Smuzhiyun 01 00 01 1b 85*4882a593Smuzhiyun 01 00 01 0a 86*4882a593Smuzhiyun 01 00 01 3c 87*4882a593Smuzhiyun 01 00 01 78 88*4882a593Smuzhiyun 01 00 01 4a 89*4882a593Smuzhiyun 01 00 01 07 90*4882a593Smuzhiyun 01 00 01 0e 91*4882a593Smuzhiyun 01 00 01 09 92*4882a593Smuzhiyun 01 00 01 1b 93*4882a593Smuzhiyun 01 00 01 1e 94*4882a593Smuzhiyun 01 00 01 0f 95*4882a593Smuzhiyun 00 00 01 e1 96*4882a593Smuzhiyun 01 00 01 00 97*4882a593Smuzhiyun 01 00 01 22 98*4882a593Smuzhiyun 01 00 01 24 99*4882a593Smuzhiyun 01 00 01 06 100*4882a593Smuzhiyun 01 00 01 12 101*4882a593Smuzhiyun 01 00 01 07 102*4882a593Smuzhiyun 01 00 01 36 103*4882a593Smuzhiyun 01 00 01 47 104*4882a593Smuzhiyun 01 00 01 47 105*4882a593Smuzhiyun 01 00 01 06 106*4882a593Smuzhiyun 01 00 01 0a 107*4882a593Smuzhiyun 01 00 01 07 108*4882a593Smuzhiyun 01 00 01 30 109*4882a593Smuzhiyun 01 00 01 37 110*4882a593Smuzhiyun 01 00 01 0f 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun 00 00 01 c0 113*4882a593Smuzhiyun 01 00 01 10 114*4882a593Smuzhiyun 01 00 01 10 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun 00 00 01 c1 117*4882a593Smuzhiyun 01 00 01 41 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun 00 00 01 c5 120*4882a593Smuzhiyun 01 00 01 00 121*4882a593Smuzhiyun 01 00 01 22 122*4882a593Smuzhiyun 01 00 01 80 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun 00 00 01 36 125*4882a593Smuzhiyun 01 00 01 48 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun 00 00 01 3a //interface pixel format 128*4882a593Smuzhiyun 01 00 01 55 // bpp cfg 129*4882a593Smuzhiyun // 3 11 130*4882a593Smuzhiyun // 16 55 131*4882a593Smuzhiyun // 18 66 132*4882a593Smuzhiyun // 24 77 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun 00 00 01 b0 //interface mode control 135*4882a593Smuzhiyun 01 00 01 00 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun 00 00 01 b1 //frame rate 60hz 138*4882a593Smuzhiyun 01 00 01 a0 139*4882a593Smuzhiyun 01 00 01 11 140*4882a593Smuzhiyun 00 00 01 b4 141*4882a593Smuzhiyun 01 00 01 02 142*4882a593Smuzhiyun 00 00 01 B6 143*4882a593Smuzhiyun 01 00 01 02 144*4882a593Smuzhiyun 01 00 01 02 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun 00 00 01 b7 147*4882a593Smuzhiyun 01 00 01 c6 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun 00 00 01 be 150*4882a593Smuzhiyun 01 00 01 00 151*4882a593Smuzhiyun 01 00 01 04 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun 00 00 01 e9 154*4882a593Smuzhiyun 01 00 01 00 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun 00 00 01 f7 157*4882a593Smuzhiyun 01 00 01 a9 158*4882a593Smuzhiyun 01 00 01 51 159*4882a593Smuzhiyun 01 00 01 2c 160*4882a593Smuzhiyun 01 00 01 82 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun 00 78 01 11 163*4882a593Smuzhiyun 00 32 01 29 164*4882a593Smuzhiyun 00 00 01 2c 165*4882a593Smuzhiyun ]; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun panel-exit-sequence = [ 168*4882a593Smuzhiyun //type delay num val1 val2 val3 169*4882a593Smuzhiyun 00 0a 01 28 170*4882a593Smuzhiyun 00 78 01 10 171*4882a593Smuzhiyun ]; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun display-timings { 174*4882a593Smuzhiyun native-mode = <&kd050fwfba002_timing>; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun kd050fwfba002_timing: timing0 { 177*4882a593Smuzhiyun clock-frequency = <94081500>; 178*4882a593Smuzhiyun hactive = <320>; 179*4882a593Smuzhiyun vactive = <480>; 180*4882a593Smuzhiyun hback-porch = <10>; 181*4882a593Smuzhiyun hfront-porch = <5>; 182*4882a593Smuzhiyun vback-porch = <10>; 183*4882a593Smuzhiyun vfront-porch = <5>; 184*4882a593Smuzhiyun hsync-len = <10>; 185*4882a593Smuzhiyun vsync-len = <10>; 186*4882a593Smuzhiyun hsync-active = <0>; 187*4882a593Smuzhiyun vsync-active = <0>; 188*4882a593Smuzhiyun de-active = <0>; 189*4882a593Smuzhiyun pixelclk-active = <1>; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun port { 194*4882a593Smuzhiyun panel_in_rgb: endpoint { 195*4882a593Smuzhiyun remote-endpoint = <&rgb_out_panel>; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun ports { 201*4882a593Smuzhiyun rgb_out: port@1 { 202*4882a593Smuzhiyun reg = <1>; 203*4882a593Smuzhiyun #address-cells = <1>; 204*4882a593Smuzhiyun #size-cells = <0>; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun rgb_out_panel: endpoint@0 { 207*4882a593Smuzhiyun reg = <0>; 208*4882a593Smuzhiyun remote-endpoint = <&panel_in_rgb>; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun}; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun&rgb_in_vp0 { 215*4882a593Smuzhiyun status = "okay"; 216*4882a593Smuzhiyun}; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun&route_rgb { 219*4882a593Smuzhiyun status = "okay"; 220*4882a593Smuzhiyun connect = <&vp0_out_rgb>; 221*4882a593Smuzhiyun}; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun/* 224*4882a593Smuzhiyun * The pins of sai0/vcc_mipicsi0 and rgb are multiplexed 225*4882a593Smuzhiyun */ 226*4882a593Smuzhiyun&sai0 { 227*4882a593Smuzhiyun status = "disabled"; 228*4882a593Smuzhiyun}; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun&vcc_mipicsi0 { 231*4882a593Smuzhiyun status = "disabled"; 232*4882a593Smuzhiyun}; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun&video_phy { 235*4882a593Smuzhiyun status = "disabled"; 236*4882a593Smuzhiyun}; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun&vop { 239*4882a593Smuzhiyun status = "okay"; 240*4882a593Smuzhiyun}; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun&vp0 { 243*4882a593Smuzhiyun mcu-timing { 244*4882a593Smuzhiyun mcu-pix-total = <9>; 245*4882a593Smuzhiyun mcu-cs-pst = <1>; 246*4882a593Smuzhiyun mcu-cs-pend = <8>; 247*4882a593Smuzhiyun mcu-rw-pst = <2>; 248*4882a593Smuzhiyun mcu-rw-pend = <5>; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun mcu-hold-mode = <0>; // default set to 0 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun}; 253