xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-lvds.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h>
8*4882a593Smuzhiyun#include "rk3562-evb1-lp4x-v10.dtsi"
9*4882a593Smuzhiyun#include "rk3562-android.dtsi"
10*4882a593Smuzhiyun#include "rk3562-rk817.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	panel-lvds {
15*4882a593Smuzhiyun		compatible = "simple-panel";
16*4882a593Smuzhiyun		status = "okay";
17*4882a593Smuzhiyun		backlight = <&backlight>;
18*4882a593Smuzhiyun		reset-delay-ms = <20>;
19*4882a593Smuzhiyun		enable-delay-ms = <20>;
20*4882a593Smuzhiyun		prepare-delay-ms = <20>;
21*4882a593Smuzhiyun		unprepare-delay-ms = <20>;
22*4882a593Smuzhiyun		disable-delay-ms = <20>;
23*4882a593Smuzhiyun		bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
24*4882a593Smuzhiyun		width-mm = <164>;
25*4882a593Smuzhiyun		height-mm = <100>;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd_n>;
28*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
29*4882a593Smuzhiyun		pinctrl-names = "default";
30*4882a593Smuzhiyun		pinctrl-0 = <&lcd_rst_gpio>;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		display-timings {
33*4882a593Smuzhiyun			native-mode = <&timing0>;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun			timing0: timing0 {
36*4882a593Smuzhiyun				clock-frequency = <27000000>;
37*4882a593Smuzhiyun				hactive = <1024>;
38*4882a593Smuzhiyun				vactive = <600>;
39*4882a593Smuzhiyun				hback-porch = <160>;
40*4882a593Smuzhiyun				hfront-porch = <160>;
41*4882a593Smuzhiyun				vback-porch = <20>;
42*4882a593Smuzhiyun				vfront-porch = <15>;
43*4882a593Smuzhiyun				hsync-len = <6>;
44*4882a593Smuzhiyun				vsync-len = <5>;
45*4882a593Smuzhiyun				hsync-active = <0>;
46*4882a593Smuzhiyun				vsync-active = <0>;
47*4882a593Smuzhiyun				de-active = <0>;
48*4882a593Smuzhiyun				pixelclk-active = <0>;
49*4882a593Smuzhiyun			};
50*4882a593Smuzhiyun		};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun		ports {
53*4882a593Smuzhiyun			#address-cells = <1>;
54*4882a593Smuzhiyun			#size-cells = <0>;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun			port@0 {
57*4882a593Smuzhiyun				reg = <0>;
58*4882a593Smuzhiyun				panel_in_lvds: endpoint {
59*4882a593Smuzhiyun					remote-endpoint = <&lvds_out_panel>;
60*4882a593Smuzhiyun				};
61*4882a593Smuzhiyun			};
62*4882a593Smuzhiyun		};
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun&backlight {
68*4882a593Smuzhiyun	pwms = <&pwm5 0 25000 0>;
69*4882a593Smuzhiyun	status = "okay";
70*4882a593Smuzhiyun};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun&dsi {
73*4882a593Smuzhiyun	status = "disabled";
74*4882a593Smuzhiyun};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun&lvds {
77*4882a593Smuzhiyun	status = "okay";
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	ports {
80*4882a593Smuzhiyun		port@1 {
81*4882a593Smuzhiyun			reg = <1>;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun			lvds_out_panel: endpoint {
84*4882a593Smuzhiyun				remote-endpoint = <&panel_in_lvds>;
85*4882a593Smuzhiyun			};
86*4882a593Smuzhiyun		};
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&lvds_in_vp0 {
91*4882a593Smuzhiyun	status = "okay";
92*4882a593Smuzhiyun};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun&pinctrl {
95*4882a593Smuzhiyun	lcd {
96*4882a593Smuzhiyun		lcd_rst_gpio: lcd-rst-gpio {
97*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
98*4882a593Smuzhiyun		};
99*4882a593Smuzhiyun	};
100*4882a593Smuzhiyun};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun&pwm5 {
103*4882a593Smuzhiyun	pinctrl-names = "active";
104*4882a593Smuzhiyun	pinctrl-0 = <&pwm5m0_pins>;
105*4882a593Smuzhiyun	status = "okay";
106*4882a593Smuzhiyun};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun&vcc3v3_lcd_n {
109*4882a593Smuzhiyun	gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
110*4882a593Smuzhiyun	enable-active-high;
111*4882a593Smuzhiyun	status = "okay";
112*4882a593Smuzhiyun};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun&video_phy {
115*4882a593Smuzhiyun	status = "okay";
116*4882a593Smuzhiyun};
117