xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3562-evb1-cam.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/ {
8*4882a593Smuzhiyun	vcc_mipicsi0: vcc-mipicsi0-regulator {
9*4882a593Smuzhiyun		compatible = "regulator-fixed";
10*4882a593Smuzhiyun		gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
11*4882a593Smuzhiyun		pinctrl-names = "default";
12*4882a593Smuzhiyun		pinctrl-0 = <&mipicsi0_pwr>;
13*4882a593Smuzhiyun		regulator-name = "vcc_mipicsi0";
14*4882a593Smuzhiyun		enable-active-high;
15*4882a593Smuzhiyun	};
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun&csi2_dphy0 {
20*4882a593Smuzhiyun	status = "okay";
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	ports {
23*4882a593Smuzhiyun		#address-cells = <1>;
24*4882a593Smuzhiyun		#size-cells = <0>;
25*4882a593Smuzhiyun		port@0 {
26*4882a593Smuzhiyun			reg = <0>;
27*4882a593Smuzhiyun			#address-cells = <1>;
28*4882a593Smuzhiyun			#size-cells = <0>;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
31*4882a593Smuzhiyun				reg = <1>;
32*4882a593Smuzhiyun				remote-endpoint = <&gc8034_out0>;
33*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
34*4882a593Smuzhiyun			};
35*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@2 {
36*4882a593Smuzhiyun				reg = <2>;
37*4882a593Smuzhiyun				remote-endpoint = <&ov5695_out0>;
38*4882a593Smuzhiyun				data-lanes = <1 2>;
39*4882a593Smuzhiyun			};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun		port@1 {
43*4882a593Smuzhiyun			reg = <1>;
44*4882a593Smuzhiyun			#address-cells = <1>;
45*4882a593Smuzhiyun			#size-cells = <0>;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun			csidcphy0_out: endpoint@0 {
48*4882a593Smuzhiyun				reg = <0>;
49*4882a593Smuzhiyun				remote-endpoint = <&mipi0_csi2_input>;
50*4882a593Smuzhiyun			};
51*4882a593Smuzhiyun		};
52*4882a593Smuzhiyun	};
53*4882a593Smuzhiyun};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun&i2c4 {
56*4882a593Smuzhiyun	status = "okay";
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	dw9714: dw9714@c {
59*4882a593Smuzhiyun		compatible = "dongwoon,dw9714";
60*4882a593Smuzhiyun		status = "okay";
61*4882a593Smuzhiyun		reg = <0x0c>;
62*4882a593Smuzhiyun		rockchip,vcm-start-current = <10>;
63*4882a593Smuzhiyun		rockchip,vcm-rated-current = <85>;
64*4882a593Smuzhiyun		rockchip,vcm-step-mode = <5>;
65*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
66*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
67*4882a593Smuzhiyun	};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	gc8034: gc8034@37 {
70*4882a593Smuzhiyun		compatible = "galaxycore,gc8034";
71*4882a593Smuzhiyun		reg = <0x37>;
72*4882a593Smuzhiyun		clocks = <&cru CLK_CAM0_OUT2IO>;
73*4882a593Smuzhiyun		clock-names = "xvclk";
74*4882a593Smuzhiyun		pinctrl-names = "default";
75*4882a593Smuzhiyun		pinctrl-0 = <&camm0_clk0_out>;
76*4882a593Smuzhiyun		reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
77*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
78*4882a593Smuzhiyun		avdd-supply = <&vcc2v8_dvp>;
79*4882a593Smuzhiyun		dovdd-supply = <&vcc1v8_dvp>;
80*4882a593Smuzhiyun		dvdd-supply = <&vcc_mipicsi0>;
81*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
82*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
83*4882a593Smuzhiyun		rockchip,camera-module-name = "RK-CMK-8M-2-v1";
84*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "CK8401";
85*4882a593Smuzhiyun		lens-focus = <&dw9714>;
86*4882a593Smuzhiyun		port {
87*4882a593Smuzhiyun			gc8034_out0: endpoint {
88*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
89*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
90*4882a593Smuzhiyun			};
91*4882a593Smuzhiyun		};
92*4882a593Smuzhiyun	};
93*4882a593Smuzhiyun	ov5695: ov5695@36 {
94*4882a593Smuzhiyun		compatible = "ovti,ov5695";
95*4882a593Smuzhiyun		reg = <0x36>;
96*4882a593Smuzhiyun		clocks = <&cru CLK_CAM0_OUT2IO>;
97*4882a593Smuzhiyun		clock-names = "xvclk";
98*4882a593Smuzhiyun		pinctrl-names = "default";
99*4882a593Smuzhiyun		pinctrl-0 = <&camm0_clk0_out>;
100*4882a593Smuzhiyun		reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
101*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
102*4882a593Smuzhiyun		avdd-supply = <&vcc2v8_dvp>;
103*4882a593Smuzhiyun		dovdd-supply = <&vcc1v8_dvp>;
104*4882a593Smuzhiyun		dvdd-supply = <&vcc_mipicsi0>;
105*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
106*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
107*4882a593Smuzhiyun		rockchip,camera-module-name = "TongJu";
108*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "CHT842-MD";
109*4882a593Smuzhiyun		port {
110*4882a593Smuzhiyun			ov5695_out0: endpoint {
111*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam1>;
112*4882a593Smuzhiyun				data-lanes = <1 2>;
113*4882a593Smuzhiyun			};
114*4882a593Smuzhiyun		};
115*4882a593Smuzhiyun	};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun&csi2_dphy0_hw {
120*4882a593Smuzhiyun	status = "okay";
121*4882a593Smuzhiyun};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun&mipi0_csi2 {
124*4882a593Smuzhiyun	status = "okay";
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun	ports {
127*4882a593Smuzhiyun		#address-cells = <1>;
128*4882a593Smuzhiyun		#size-cells = <0>;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun		port@0 {
131*4882a593Smuzhiyun			reg = <0>;
132*4882a593Smuzhiyun			#address-cells = <1>;
133*4882a593Smuzhiyun			#size-cells = <0>;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun			mipi0_csi2_input: endpoint@1 {
136*4882a593Smuzhiyun				reg = <1>;
137*4882a593Smuzhiyun				remote-endpoint = <&csidcphy0_out>;
138*4882a593Smuzhiyun			};
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		port@1 {
142*4882a593Smuzhiyun			reg = <1>;
143*4882a593Smuzhiyun			#address-cells = <1>;
144*4882a593Smuzhiyun			#size-cells = <0>;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun			mipi0_csi2_output: endpoint@0 {
147*4882a593Smuzhiyun				reg = <0>;
148*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in0>;
149*4882a593Smuzhiyun			};
150*4882a593Smuzhiyun		};
151*4882a593Smuzhiyun	};
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&rkcif {
155*4882a593Smuzhiyun	status = "okay";
156*4882a593Smuzhiyun};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun&rkcif_mipi_lvds {
159*4882a593Smuzhiyun	status = "okay";
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun	port {
162*4882a593Smuzhiyun		cif_mipi_in0: endpoint {
163*4882a593Smuzhiyun			remote-endpoint = <&mipi0_csi2_output>;
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf {
169*4882a593Smuzhiyun	status = "okay";
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun	port {
172*4882a593Smuzhiyun		mipi_lvds_sditf: endpoint {
173*4882a593Smuzhiyun			remote-endpoint = <&isp_vir0>;
174*4882a593Smuzhiyun		};
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun&rkcif_mmu {
179*4882a593Smuzhiyun	status = "okay";
180*4882a593Smuzhiyun};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun&rkisp {
183*4882a593Smuzhiyun	status = "okay";
184*4882a593Smuzhiyun};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun&rkisp_mmu {
187*4882a593Smuzhiyun	status = "okay";
188*4882a593Smuzhiyun};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun&rkisp_vir0 {
191*4882a593Smuzhiyun	status = "okay";
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun	port {
194*4882a593Smuzhiyun		#address-cells = <1>;
195*4882a593Smuzhiyun		#size-cells = <0>;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun		isp_vir0: endpoint@0 {
198*4882a593Smuzhiyun			reg = <0>;
199*4882a593Smuzhiyun			remote-endpoint = <&mipi_lvds_sditf>;
200*4882a593Smuzhiyun		};
201*4882a593Smuzhiyun	};
202*4882a593Smuzhiyun};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun&pinctrl {
205*4882a593Smuzhiyun	cam {
206*4882a593Smuzhiyun		mipicsi0_pwr: mipicsi0-pwr {
207*4882a593Smuzhiyun			rockchip,pins =
208*4882a593Smuzhiyun				/* camera power en */
209*4882a593Smuzhiyun				<4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
210*4882a593Smuzhiyun		};
211*4882a593Smuzhiyun	};
212*4882a593Smuzhiyun};
213*4882a593Smuzhiyun
214