1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "rk3528-evb1-ddr4-v10.dtsi" 8*4882a593Smuzhiyun#include "rk3528-linux.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun chosen: chosen { 12*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw rootwait"; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun}; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun&sdmmc { 17*4882a593Smuzhiyun status = "disabled"; 18*4882a593Smuzhiyun}; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun&sfc { 21*4882a593Smuzhiyun status = "okay"; 22*4882a593Smuzhiyun flash@0 { 23*4882a593Smuzhiyun compatible = "spi-nand"; 24*4882a593Smuzhiyun reg = <0>; 25*4882a593Smuzhiyun spi-max-frequency = <75000000>; 26*4882a593Smuzhiyun spi-rx-bus-width = <4>; 27*4882a593Smuzhiyun spi-tx-bus-width = <1>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun}; 30