xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v10-linux.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun/dts-v1/;
5*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
6*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
7*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
8*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
9*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
10*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
11*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h"
12*4882a593Smuzhiyun#include "rk3399pro.dtsi"
13*4882a593Smuzhiyun#include "rk3399-linux.dtsi"
14*4882a593Smuzhiyun#include "rk3399-opp.dtsi"
15*4882a593Smuzhiyun#include "rk3399-vop-clk-set.dtsi"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun/ {
18*4882a593Smuzhiyun	compatible = "rockchip,rk3399pro-evb-v10-linux", "rockchip,rk3399pro";
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	adc-keys {
21*4882a593Smuzhiyun		compatible = "adc-keys";
22*4882a593Smuzhiyun		io-channels = <&saradc 2>;
23*4882a593Smuzhiyun		io-channel-names = "buttons";
24*4882a593Smuzhiyun		poll-interval = <100>;
25*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		esc-key {
28*4882a593Smuzhiyun			linux,code = <KEY_ESC>;
29*4882a593Smuzhiyun			label = "esc";
30*4882a593Smuzhiyun			press-threshold-microvolt = <1310000>;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun		menu-key {
34*4882a593Smuzhiyun			linux,code = <KEY_MENU>;
35*4882a593Smuzhiyun			label = "menu";
36*4882a593Smuzhiyun			press-threshold-microvolt = <987000>;
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun		home-key {
40*4882a593Smuzhiyun			linux,code = <KEY_HOME>;
41*4882a593Smuzhiyun			label = "home";
42*4882a593Smuzhiyun			press-threshold-microvolt = <624000>;
43*4882a593Smuzhiyun		};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		vol-down-key {
46*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
47*4882a593Smuzhiyun			label = "volume down";
48*4882a593Smuzhiyun			press-threshold-microvolt = <300000>;
49*4882a593Smuzhiyun		};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun		vol-up-key {
52*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
53*4882a593Smuzhiyun			label = "volume up";
54*4882a593Smuzhiyun			press-threshold-microvolt = <17000>;
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	backlight: backlight {
59*4882a593Smuzhiyun		compatible = "pwm-backlight";
60*4882a593Smuzhiyun		pwms = <&pwm0 0 25000 0>;
61*4882a593Smuzhiyun		brightness-levels = <
62*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
63*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
64*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
65*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
66*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
67*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
68*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
69*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
70*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
71*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
72*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
73*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
74*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
75*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
76*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
77*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
78*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
79*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
80*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
81*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
82*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
83*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
84*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
85*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
86*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
87*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
88*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
89*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
90*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
91*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
92*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
93*4882a593Smuzhiyun			248 249 250 251 252 253 254 255
94*4882a593Smuzhiyun		>;
95*4882a593Smuzhiyun		default-brightness-level = <200>;
96*4882a593Smuzhiyun		enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
97*4882a593Smuzhiyun	};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun	clkin_gmac: external-gmac-clock {
100*4882a593Smuzhiyun		compatible = "fixed-clock";
101*4882a593Smuzhiyun		clock-frequency = <125000000>;
102*4882a593Smuzhiyun		clock-output-names = "clkin_gmac";
103*4882a593Smuzhiyun		#clock-cells = <0>;
104*4882a593Smuzhiyun	};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun	fiq_debugger: fiq-debugger {
107*4882a593Smuzhiyun		compatible = "rockchip,fiq-debugger";
108*4882a593Smuzhiyun		rockchip,serial-id = <2>;
109*4882a593Smuzhiyun		rockchip,wake-irq = <0>;
110*4882a593Smuzhiyun		rockchip,irq-mode-enable = <0>;  /* If enable uart uses irq instead of fiq */
111*4882a593Smuzhiyun		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
112*4882a593Smuzhiyun		pinctrl-names = "default";
113*4882a593Smuzhiyun		pinctrl-0 = <&uart2c_xfer>;
114*4882a593Smuzhiyun		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
115*4882a593Smuzhiyun	};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun	hdmi_sound: hdmi-sound {
118*4882a593Smuzhiyun		status = "okay";
119*4882a593Smuzhiyun		compatible = "simple-audio-card";
120*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
121*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
122*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,hdmi";
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun		simple-audio-card,cpu {
125*4882a593Smuzhiyun			sound-dai = <&i2s2>;
126*4882a593Smuzhiyun		};
127*4882a593Smuzhiyun		simple-audio-card,codec {
128*4882a593Smuzhiyun			sound-dai = <&hdmi>;
129*4882a593Smuzhiyun		};
130*4882a593Smuzhiyun	};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun	panel: panel {
133*4882a593Smuzhiyun		compatible = "simple-panel";
134*4882a593Smuzhiyun		backlight = <&backlight>;
135*4882a593Smuzhiyun		enable-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
136*4882a593Smuzhiyun		prepare-delay-ms = <20>;
137*4882a593Smuzhiyun		enable-delay-ms = <20>;
138*4882a593Smuzhiyun		reset-delay-ms = <20>;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun		display-timings {
141*4882a593Smuzhiyun			native-mode = <&timing0>;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun			timing0: timing0 {
144*4882a593Smuzhiyun				clock-frequency = <200000000>;
145*4882a593Smuzhiyun				hactive = <1536>;
146*4882a593Smuzhiyun				vactive = <2048>;
147*4882a593Smuzhiyun				hfront-porch = <12>;
148*4882a593Smuzhiyun				hsync-len = <16>;
149*4882a593Smuzhiyun				hback-porch = <48>;
150*4882a593Smuzhiyun				vfront-porch = <8>;
151*4882a593Smuzhiyun				vsync-len = <4>;
152*4882a593Smuzhiyun				vback-porch = <8>;
153*4882a593Smuzhiyun				hsync-active = <0>;
154*4882a593Smuzhiyun				vsync-active = <0>;
155*4882a593Smuzhiyun				de-active = <0>;
156*4882a593Smuzhiyun				pixelclk-active = <0>;
157*4882a593Smuzhiyun			};
158*4882a593Smuzhiyun		};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun		ports {
161*4882a593Smuzhiyun			panel_in: endpoint {
162*4882a593Smuzhiyun				remote-endpoint = <&edp_out>;
163*4882a593Smuzhiyun			};
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun	rk809_sound: rk809-sound {
168*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
169*4882a593Smuzhiyun		rockchip,card-name = "rockchip,rk809-codec";
170*4882a593Smuzhiyun		rockchip,codec-hp-det;
171*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
172*4882a593Smuzhiyun		rockchip,cpu = <&i2s1>;
173*4882a593Smuzhiyun		rockchip,codec = <&rk809_codec>;
174*4882a593Smuzhiyun	};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun	rk_headset: rk-headset {
177*4882a593Smuzhiyun		compatible = "rockchip_headset";
178*4882a593Smuzhiyun		headset_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
179*4882a593Smuzhiyun		pinctrl-names = "default";
180*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
181*4882a593Smuzhiyun		io-channels = <&saradc 3>;
182*4882a593Smuzhiyun	};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
185*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
186*4882a593Smuzhiyun		clocks = <&rk809 1>;
187*4882a593Smuzhiyun		clock-names = "ext_clock";
188*4882a593Smuzhiyun		pinctrl-names = "default";
189*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun		/*
192*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
193*4882a593Smuzhiyun		 * on the actual card populated):
194*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
195*4882a593Smuzhiyun		 * - PDN (power down when low)
196*4882a593Smuzhiyun		 */
197*4882a593Smuzhiyun		reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
198*4882a593Smuzhiyun	};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun	vbus_typec: vbus-typec-regulator {
201*4882a593Smuzhiyun		compatible = "regulator-fixed";
202*4882a593Smuzhiyun		enable-active-high;
203*4882a593Smuzhiyun		gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
204*4882a593Smuzhiyun		pinctrl-names = "default";
205*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_typec0_en>;
206*4882a593Smuzhiyun		regulator-name = "vbus_typec";
207*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
208*4882a593Smuzhiyun	};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun	vcc_phy: vcc-phy-regulator {
211*4882a593Smuzhiyun		compatible = "regulator-fixed";
212*4882a593Smuzhiyun		regulator-name = "vcc_phy";
213*4882a593Smuzhiyun		regulator-always-on;
214*4882a593Smuzhiyun		regulator-boot-on;
215*4882a593Smuzhiyun	};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun	vcc5v0_sys: vccsys {
218*4882a593Smuzhiyun		compatible = "regulator-fixed";
219*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
220*4882a593Smuzhiyun		regulator-always-on;
221*4882a593Smuzhiyun		regulator-boot-on;
222*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
223*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
224*4882a593Smuzhiyun	};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun	wireless-wlan {
227*4882a593Smuzhiyun		compatible = "wlan-platdata";
228*4882a593Smuzhiyun		rockchip,grf = <&grf>;
229*4882a593Smuzhiyun		wifi_chip_type = "ap6398s";
230*4882a593Smuzhiyun		sdio_vref = <1800>;
231*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
232*4882a593Smuzhiyun		status = "okay";
233*4882a593Smuzhiyun	};
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun	wireless-bluetooth {
236*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
237*4882a593Smuzhiyun		clocks = <&rk809 1>;
238*4882a593Smuzhiyun		clock-names = "ext_clock";
239*4882a593Smuzhiyun		uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
240*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
241*4882a593Smuzhiyun		pinctrl-0 = <&uart0_rts>, <&bt_irq_gpio>;
242*4882a593Smuzhiyun		pinctrl-1 = <&uart0_gpios>;
243*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
244*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
245*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
246*4882a593Smuzhiyun		status = "okay";
247*4882a593Smuzhiyun	};
248*4882a593Smuzhiyun};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun&cdn_dp {
251*4882a593Smuzhiyun	status = "okay";
252*4882a593Smuzhiyun	phys = <&tcphy0_dp>;
253*4882a593Smuzhiyun};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun&cpu_l0 {
256*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
257*4882a593Smuzhiyun};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun&cpu_l1 {
260*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
261*4882a593Smuzhiyun};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun&cpu_l2 {
264*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
265*4882a593Smuzhiyun};
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun&cpu_l3 {
268*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
269*4882a593Smuzhiyun};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun&cpu_b0 {
272*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_b>;
273*4882a593Smuzhiyun};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun&cpu_b1 {
276*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_b>;
277*4882a593Smuzhiyun};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun&display_subsystem {
280*4882a593Smuzhiyun	status = "okay";
281*4882a593Smuzhiyun};
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun&dp_in_vopb {
284*4882a593Smuzhiyun	status = "disabled";
285*4882a593Smuzhiyun};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun&edp {
288*4882a593Smuzhiyun	status = "okay";
289*4882a593Smuzhiyun	force-hpd;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun	ports {
292*4882a593Smuzhiyun		port@1 {
293*4882a593Smuzhiyun			reg = <1>;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun			edp_out: endpoint {
296*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
297*4882a593Smuzhiyun			};
298*4882a593Smuzhiyun		};
299*4882a593Smuzhiyun	};
300*4882a593Smuzhiyun};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun&edp_in_vopb {
303*4882a593Smuzhiyun	status = "disabled";
304*4882a593Smuzhiyun};
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun&emmc_phy {
307*4882a593Smuzhiyun	status = "okay";
308*4882a593Smuzhiyun};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun&fiq_debugger {
311*4882a593Smuzhiyun	pinctrl-0 = <&uart2a_xfer>;
312*4882a593Smuzhiyun};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun&gmac {
315*4882a593Smuzhiyun	phy-supply = <&vcc_phy>;
316*4882a593Smuzhiyun	phy-mode = "rgmii";
317*4882a593Smuzhiyun	clock_in_out = "input";
318*4882a593Smuzhiyun	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
319*4882a593Smuzhiyun	snps,reset-active-low;
320*4882a593Smuzhiyun	snps,reset-delays-us = <0 10000 50000>;
321*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_RMII_SRC>;
322*4882a593Smuzhiyun	assigned-clock-parents = <&clkin_gmac>;
323*4882a593Smuzhiyun	pinctrl-names = "default";
324*4882a593Smuzhiyun	pinctrl-0 = <&rgmii_pins>;
325*4882a593Smuzhiyun	tx_delay = <0x28>;
326*4882a593Smuzhiyun	rx_delay = <0x11>;
327*4882a593Smuzhiyun	status = "okay";
328*4882a593Smuzhiyun};
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun&gpu {
331*4882a593Smuzhiyun	status = "okay";
332*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
333*4882a593Smuzhiyun};
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun&hdmi {
336*4882a593Smuzhiyun	status = "okay";
337*4882a593Smuzhiyun	#sound-dai-cells = <0>;
338*4882a593Smuzhiyun	rockchip,phy-table =
339*4882a593Smuzhiyun		<74250000  0x8009 0x0004 0x0272>,
340*4882a593Smuzhiyun		<165000000 0x802b 0x0004 0x0209>,
341*4882a593Smuzhiyun		<297000000 0x8039 0x0005 0x028d>,
342*4882a593Smuzhiyun		<594000000 0x8039 0x0000 0x00f6>,
343*4882a593Smuzhiyun		<000000000 0x0000 0x0000 0x0000>;
344*4882a593Smuzhiyun};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun&hdmi_in_vopl {
347*4882a593Smuzhiyun	status = "disabled";
348*4882a593Smuzhiyun};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun&i2c0 {
351*4882a593Smuzhiyun	status = "okay";
352*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <180>;
353*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <30>;
354*4882a593Smuzhiyun	clock-frequency = <400000>;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun	rk809: pmic@20 {
357*4882a593Smuzhiyun		compatible = "rockchip,rk809";
358*4882a593Smuzhiyun		reg = <0x20>;
359*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
360*4882a593Smuzhiyun		interrupts = <RK_PC2 IRQ_TYPE_LEVEL_LOW>;
361*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-sleep",
362*4882a593Smuzhiyun				"pmic-power-off", "pmic-reset";
363*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int_l>;
364*4882a593Smuzhiyun		pinctrl-1 = <&soc_slppin_slp>, <&rk809_slppin_slp>;
365*4882a593Smuzhiyun		pinctrl-2 = <&soc_slppin_gpio>, <&rk809_slppin_pwrdn>;
366*4882a593Smuzhiyun		pinctrl-3 = <&soc_slppin_gpio>, <&rk809_slppin_rst>;
367*4882a593Smuzhiyun		rockchip,system-power-controller;
368*4882a593Smuzhiyun		pmic-reset-func = <0>;
369*4882a593Smuzhiyun		wakeup-source;
370*4882a593Smuzhiyun		#clock-cells = <1>;
371*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun		vcc1-supply = <&vcc5v0_sys>;
374*4882a593Smuzhiyun		vcc2-supply = <&vcc5v0_sys>;
375*4882a593Smuzhiyun		vcc3-supply = <&vcc5v0_sys>;
376*4882a593Smuzhiyun		vcc4-supply = <&vcc5v0_sys>;
377*4882a593Smuzhiyun		vcc5-supply = <&vcc_buck5>;
378*4882a593Smuzhiyun		vcc6-supply = <&vcc_buck5>;
379*4882a593Smuzhiyun		vcc7-supply = <&vcc3v3_sys>;
380*4882a593Smuzhiyun		vcc8-supply = <&vcc3v3_sys>;
381*4882a593Smuzhiyun		vcc9-supply = <&vcc5v0_sys>;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun		pwrkey {
384*4882a593Smuzhiyun			status = "okay";
385*4882a593Smuzhiyun		};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun		rtc {
388*4882a593Smuzhiyun			status = "okay";
389*4882a593Smuzhiyun		};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
392*4882a593Smuzhiyun			gpio-controller;
393*4882a593Smuzhiyun			#gpio-cells = <2>;
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun			rk809_slppin_null: rk809_slppin_null {
396*4882a593Smuzhiyun				pins = "gpio_slp";
397*4882a593Smuzhiyun				function = "pin_fun0";
398*4882a593Smuzhiyun			};
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun			rk809_slppin_slp: rk809_slppin_slp {
401*4882a593Smuzhiyun				pins = "gpio_slp";
402*4882a593Smuzhiyun				function = "pin_fun1";
403*4882a593Smuzhiyun			};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun			rk809_slppin_pwrdn: rk809_slppin_pwrdn {
406*4882a593Smuzhiyun				pins = "gpio_slp";
407*4882a593Smuzhiyun				function = "pin_fun2";
408*4882a593Smuzhiyun			};
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun			rk809_slppin_rst: rk809_slppin_rst {
411*4882a593Smuzhiyun				pins = "gpio_slp";
412*4882a593Smuzhiyun				function = "pin_fun3";
413*4882a593Smuzhiyun			};
414*4882a593Smuzhiyun		};
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun		regulators {
417*4882a593Smuzhiyun			vdd_log: DCDC_REG1 {
418*4882a593Smuzhiyun				regulator-always-on;
419*4882a593Smuzhiyun				regulator-boot-on;
420*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
421*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
422*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
423*4882a593Smuzhiyun				regulator-name = "vdd_log";
424*4882a593Smuzhiyun				regulator-state-mem {
425*4882a593Smuzhiyun					regulator-on-in-suspend;
426*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
427*4882a593Smuzhiyun				};
428*4882a593Smuzhiyun			};
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun			vdd_cpu_l: DCDC_REG2 {
431*4882a593Smuzhiyun				regulator-always-on;
432*4882a593Smuzhiyun				regulator-boot-on;
433*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
434*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
435*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
436*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
437*4882a593Smuzhiyun				regulator-name = "vdd_cpu_l";
438*4882a593Smuzhiyun				regulator-state-mem {
439*4882a593Smuzhiyun					regulator-off-in-suspend;
440*4882a593Smuzhiyun				};
441*4882a593Smuzhiyun			};
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
444*4882a593Smuzhiyun				regulator-always-on;
445*4882a593Smuzhiyun				regulator-boot-on;
446*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
447*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
448*4882a593Smuzhiyun				regulator-state-mem {
449*4882a593Smuzhiyun					regulator-on-in-suspend;
450*4882a593Smuzhiyun				};
451*4882a593Smuzhiyun			};
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun			vcc3v3_sys: DCDC_REG4 {
454*4882a593Smuzhiyun				regulator-always-on;
455*4882a593Smuzhiyun				regulator-boot-on;
456*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
457*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
458*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
459*4882a593Smuzhiyun				regulator-name = "vcc3v3_sys";
460*4882a593Smuzhiyun				regulator-state-mem {
461*4882a593Smuzhiyun					regulator-on-in-suspend;
462*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
463*4882a593Smuzhiyun				};
464*4882a593Smuzhiyun			};
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun			vcc_buck5: DCDC_REG5 {
467*4882a593Smuzhiyun				regulator-always-on;
468*4882a593Smuzhiyun				regulator-boot-on;
469*4882a593Smuzhiyun				regulator-min-microvolt = <2200000>;
470*4882a593Smuzhiyun				regulator-max-microvolt = <2200000>;
471*4882a593Smuzhiyun				regulator-name = "vcc_buck5";
472*4882a593Smuzhiyun				regulator-state-mem {
473*4882a593Smuzhiyun					regulator-on-in-suspend;
474*4882a593Smuzhiyun					regulator-suspend-microvolt = <2200000>;
475*4882a593Smuzhiyun				};
476*4882a593Smuzhiyun			};
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun			vcca_0v9: LDO_REG1 {
479*4882a593Smuzhiyun				regulator-always-on;
480*4882a593Smuzhiyun				regulator-boot-on;
481*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
482*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
483*4882a593Smuzhiyun				regulator-name = "vcca_0v9";
484*4882a593Smuzhiyun				regulator-state-mem {
485*4882a593Smuzhiyun					regulator-off-in-suspend;
486*4882a593Smuzhiyun				};
487*4882a593Smuzhiyun			};
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun			vcc_1v8: LDO_REG2 {
490*4882a593Smuzhiyun				regulator-always-on;
491*4882a593Smuzhiyun				regulator-boot-on;
492*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
493*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
496*4882a593Smuzhiyun				regulator-state-mem {
497*4882a593Smuzhiyun					regulator-on-in-suspend;
498*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
499*4882a593Smuzhiyun				};
500*4882a593Smuzhiyun			};
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun			vcc0v9_soc: LDO_REG3 {
503*4882a593Smuzhiyun				regulator-always-on;
504*4882a593Smuzhiyun				regulator-boot-on;
505*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
506*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun				regulator-name = "vcc0v9_soc";
509*4882a593Smuzhiyun				regulator-state-mem {
510*4882a593Smuzhiyun					regulator-on-in-suspend;
511*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
512*4882a593Smuzhiyun				};
513*4882a593Smuzhiyun			};
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun			vcca_1v8: LDO_REG4 {
516*4882a593Smuzhiyun				regulator-always-on;
517*4882a593Smuzhiyun				regulator-boot-on;
518*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
519*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun				regulator-name = "vcca_1v8";
522*4882a593Smuzhiyun				regulator-state-mem {
523*4882a593Smuzhiyun					regulator-off-in-suspend;
524*4882a593Smuzhiyun				};
525*4882a593Smuzhiyun			};
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun			vdd1v5_dvp: LDO_REG5 {
528*4882a593Smuzhiyun				regulator-always-on;
529*4882a593Smuzhiyun				regulator-boot-on;
530*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
531*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun				regulator-name = "vdd1v5_dvp";
534*4882a593Smuzhiyun				regulator-state-mem {
535*4882a593Smuzhiyun					regulator-off-in-suspend;
536*4882a593Smuzhiyun				};
537*4882a593Smuzhiyun			};
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun			vcc_1v5: LDO_REG6 {
540*4882a593Smuzhiyun				regulator-always-on;
541*4882a593Smuzhiyun				regulator-boot-on;
542*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
543*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun				regulator-name = "vcc_1v5";
546*4882a593Smuzhiyun				regulator-state-mem {
547*4882a593Smuzhiyun					regulator-off-in-suspend;
548*4882a593Smuzhiyun				};
549*4882a593Smuzhiyun			};
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun			vcc_3v0: LDO_REG7 {
552*4882a593Smuzhiyun				regulator-always-on;
553*4882a593Smuzhiyun				regulator-boot-on;
554*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
555*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun				regulator-name = "vcc_3v0";
558*4882a593Smuzhiyun				regulator-state-mem {
559*4882a593Smuzhiyun					regulator-off-in-suspend;
560*4882a593Smuzhiyun				};
561*4882a593Smuzhiyun			};
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun			vccio_sd: LDO_REG8 {
564*4882a593Smuzhiyun				regulator-always-on;
565*4882a593Smuzhiyun				regulator-boot-on;
566*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
567*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun				regulator-name = "vccio_sd";
570*4882a593Smuzhiyun				regulator-state-mem {
571*4882a593Smuzhiyun					regulator-off-in-suspend;
572*4882a593Smuzhiyun				};
573*4882a593Smuzhiyun			};
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun			vcc_sd: LDO_REG9 {
576*4882a593Smuzhiyun				regulator-always-on;
577*4882a593Smuzhiyun				regulator-boot-on;
578*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
579*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun				regulator-name = "vcc_sd";
582*4882a593Smuzhiyun				regulator-state-mem {
583*4882a593Smuzhiyun					regulator-off-in-suspend;
584*4882a593Smuzhiyun				};
585*4882a593Smuzhiyun			};
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun			vcc5v0_usb: SWITCH_REG1 {
588*4882a593Smuzhiyun				regulator-name = "vcc5v0_usb";
589*4882a593Smuzhiyun				regulator-state-mem {
590*4882a593Smuzhiyun					regulator-on-in-suspend;
591*4882a593Smuzhiyun				};
592*4882a593Smuzhiyun			};
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun			vccio_3v3: SWITCH_REG2 {
595*4882a593Smuzhiyun				regulator-always-on;
596*4882a593Smuzhiyun				regulator-boot-on;
597*4882a593Smuzhiyun				regulator-name = "vccio_3v3";
598*4882a593Smuzhiyun				regulator-state-mem {
599*4882a593Smuzhiyun					regulator-off-in-suspend;
600*4882a593Smuzhiyun				};
601*4882a593Smuzhiyun			};
602*4882a593Smuzhiyun		};
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun		rk809_codec: codec {
605*4882a593Smuzhiyun			#sound-dai-cells = <0>;
606*4882a593Smuzhiyun			compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
607*4882a593Smuzhiyun			clocks = <&cru SCLK_I2S_8CH_OUT>;
608*4882a593Smuzhiyun			clock-names = "mclk";
609*4882a593Smuzhiyun			pinctrl-names = "default";
610*4882a593Smuzhiyun			pinctrl-0 = <&i2s_8ch_mclk>;
611*4882a593Smuzhiyun			hp-volume = <20>;
612*4882a593Smuzhiyun			spk-volume = <3>;
613*4882a593Smuzhiyun			status = "okay";
614*4882a593Smuzhiyun		};
615*4882a593Smuzhiyun	};
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun	vdd_cpu_b: syr837@40 {
618*4882a593Smuzhiyun		compatible = "silergy,syr827";
619*4882a593Smuzhiyun		reg = <0x40>;
620*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
621*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
622*4882a593Smuzhiyun		pinctrl-0 = <&vsel1_gpio>;
623*4882a593Smuzhiyun		vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
624*4882a593Smuzhiyun		regulator-name = "vdd_cpu_b";
625*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
626*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
627*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
628*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
629*4882a593Smuzhiyun		regulator-always-on;
630*4882a593Smuzhiyun		regulator-boot-on;
631*4882a593Smuzhiyun		regulator-initial-state = <3>;
632*4882a593Smuzhiyun		regulator-state-mem {
633*4882a593Smuzhiyun			regulator-off-in-suspend;
634*4882a593Smuzhiyun		};
635*4882a593Smuzhiyun	};
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun	vdd_gpu: syr828@41 {
638*4882a593Smuzhiyun		compatible = "silergy,syr828";
639*4882a593Smuzhiyun		status = "okay";
640*4882a593Smuzhiyun		reg = <0x41>;
641*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
642*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
643*4882a593Smuzhiyun		pinctrl-0 = <&vsel2_gpio>;
644*4882a593Smuzhiyun		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
645*4882a593Smuzhiyun		regulator-name = "vdd_gpu";
646*4882a593Smuzhiyun		regulator-min-microvolt = <735000>;
647*4882a593Smuzhiyun		regulator-max-microvolt = <1400000>;
648*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
649*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
650*4882a593Smuzhiyun		regulator-always-on;
651*4882a593Smuzhiyun		regulator-boot-on;
652*4882a593Smuzhiyun		regulator-state-mem {
653*4882a593Smuzhiyun			regulator-off-in-suspend;
654*4882a593Smuzhiyun		};
655*4882a593Smuzhiyun	};
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun	bq25700: bq25700@6b {
658*4882a593Smuzhiyun		compatible = "ti,bq25703";
659*4882a593Smuzhiyun		reg = <0x6b>;
660*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
661*4882a593Smuzhiyun		interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
662*4882a593Smuzhiyun		pinctrl-names = "default";
663*4882a593Smuzhiyun		pinctrl-0 = <&charger_ok_int>;
664*4882a593Smuzhiyun		ti,charge-current = <1500000>;
665*4882a593Smuzhiyun		ti,max-charge-voltage = <8704000>;
666*4882a593Smuzhiyun		ti,max-input-voltage = <20000000>;
667*4882a593Smuzhiyun		ti,max-input-current = <6000000>;
668*4882a593Smuzhiyun		ti,input-current-sdp = <500000>;
669*4882a593Smuzhiyun		ti,input-current-dcp = <2000000>;
670*4882a593Smuzhiyun		ti,input-current-cdp = <2000000>;
671*4882a593Smuzhiyun		ti,input-current-dc = <2000000>;
672*4882a593Smuzhiyun		ti,minimum-sys-voltage = <6700000>;
673*4882a593Smuzhiyun		ti,otg-voltage = <5000000>;
674*4882a593Smuzhiyun		ti,otg-current = <500000>;
675*4882a593Smuzhiyun		ti,input-current = <500000>;
676*4882a593Smuzhiyun		pd-charge-only = <0>;
677*4882a593Smuzhiyun		status = "disabled";
678*4882a593Smuzhiyun	};
679*4882a593Smuzhiyun};
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun&i2c1 {
682*4882a593Smuzhiyun	status = "okay";
683*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <140>;
684*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <30>;
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun	mpu6500@68 {
687*4882a593Smuzhiyun		status = "okay";
688*4882a593Smuzhiyun		compatible = "invensense,mpu6500";
689*4882a593Smuzhiyun		reg = <0x68>;
690*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PD2 IRQ_TYPE_EDGE_RISING>;
691*4882a593Smuzhiyun		mpu-int_config = <0x10>;
692*4882a593Smuzhiyun		mpu-level_shifter = <0>;
693*4882a593Smuzhiyun		mpu-orientation = <0 1 0 1 0 0 0 0 1>;
694*4882a593Smuzhiyun		orientation-x= <1>;
695*4882a593Smuzhiyun		orientation-y= <0>;
696*4882a593Smuzhiyun		orientation-z= <0>;
697*4882a593Smuzhiyun		mpu-debug = <1>;
698*4882a593Smuzhiyun	};
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun	sensor@d {
701*4882a593Smuzhiyun		status = "okay";
702*4882a593Smuzhiyun		compatible = "ak8963";
703*4882a593Smuzhiyun		reg = <0x0d>;
704*4882a593Smuzhiyun		type = <SENSOR_TYPE_COMPASS>;
705*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PD7 IRQ_TYPE_EDGE_RISING>;
706*4882a593Smuzhiyun		irq_enable = <0>;
707*4882a593Smuzhiyun		poll_delay_ms = <30>;
708*4882a593Smuzhiyun		layout = <3>;
709*4882a593Smuzhiyun	};
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun	vm149c: vm149c@0c {
712*4882a593Smuzhiyun		compatible = "silicon touch,vm149c";
713*4882a593Smuzhiyun		status = "okay";
714*4882a593Smuzhiyun		reg = <0x0c>;
715*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
716*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
717*4882a593Smuzhiyun	};
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun	ov13850: ov13850@10 {
720*4882a593Smuzhiyun		compatible = "ovti,ov13850";
721*4882a593Smuzhiyun		status = "disabled";
722*4882a593Smuzhiyun		reg = <0x10>;
723*4882a593Smuzhiyun		clocks = <&cru SCLK_CIF_OUT>;
724*4882a593Smuzhiyun		clock-names = "xvclk";
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun		/* conflict with csi-ctl-gpios */
727*4882a593Smuzhiyun		reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
728*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
729*4882a593Smuzhiyun		pinctrl-names = "rockchip,camera_default";
730*4882a593Smuzhiyun		pinctrl-0 = <&cif_clkout>;
731*4882a593Smuzhiyun		lens-focus = <&vm149c>;
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun		port {
734*4882a593Smuzhiyun			ucam_out0: endpoint {
735*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
736*4882a593Smuzhiyun				data-lanes = <1 2>;
737*4882a593Smuzhiyun			};
738*4882a593Smuzhiyun		};
739*4882a593Smuzhiyun	};
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun	imx327: imx327@1a {
742*4882a593Smuzhiyun		compatible = "sony,imx327";
743*4882a593Smuzhiyun		status = "okay";
744*4882a593Smuzhiyun		reg = <0x1a>;
745*4882a593Smuzhiyun		clocks = <&cru SCLK_CIF_OUT>;
746*4882a593Smuzhiyun		clock-names = "xvclk";
747*4882a593Smuzhiyun		/* conflict with csi-ctl-gpios */
748*4882a593Smuzhiyun		reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
749*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
750*4882a593Smuzhiyun		pinctrl-names = "default";
751*4882a593Smuzhiyun		pinctrl-0 = <&cif_clkout>;
752*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
753*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
754*4882a593Smuzhiyun		rockchip,camera-module-name = "TongJu";
755*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "CHT842-MD";
756*4882a593Smuzhiyun		port {
757*4882a593Smuzhiyun			ucam_out2: endpoint {
758*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam2>;
759*4882a593Smuzhiyun				data-lanes = <1 2>;
760*4882a593Smuzhiyun			};
761*4882a593Smuzhiyun		};
762*4882a593Smuzhiyun	};
763*4882a593Smuzhiyun};
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun&i2c4 {
766*4882a593Smuzhiyun	status = "okay";
767*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <345>;
768*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <11>;
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun	gsl3673: gsl3673@40 {
771*4882a593Smuzhiyun		compatible = "GSL,GSL3673";
772*4882a593Smuzhiyun		reg = <0x40>;
773*4882a593Smuzhiyun		screen_max_x = <1536>;
774*4882a593Smuzhiyun		screen_max_y = <2048>;
775*4882a593Smuzhiyun		irq_gpio_number = <&gpio4 RK_PC3 IRQ_TYPE_LEVEL_LOW>;
776*4882a593Smuzhiyun		rst_gpio_number = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
777*4882a593Smuzhiyun	};
778*4882a593Smuzhiyun};
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun&i2c8 {
781*4882a593Smuzhiyun	status = "okay";
782*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <345>;
783*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <11>;
784*4882a593Smuzhiyun	clock-frequency = <100000>;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun	usbc0: fusb302@22 {
787*4882a593Smuzhiyun		compatible = "fcs,fusb302";
788*4882a593Smuzhiyun		reg = <0x22>;
789*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
790*4882a593Smuzhiyun		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
791*4882a593Smuzhiyun		pinctrl-names = "default";
792*4882a593Smuzhiyun		pinctrl-0 = <&usbc0_int>;
793*4882a593Smuzhiyun		vbus-supply = <&vbus_typec>;
794*4882a593Smuzhiyun		status = "okay";
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun		ports {
797*4882a593Smuzhiyun			#address-cells = <1>;
798*4882a593Smuzhiyun			#size-cells = <0>;
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun			port@0 {
801*4882a593Smuzhiyun				reg = <0>;
802*4882a593Smuzhiyun				usbc0_role_sw: endpoint@0 {
803*4882a593Smuzhiyun					remote-endpoint = <&dwc3_0_role_switch>;
804*4882a593Smuzhiyun				};
805*4882a593Smuzhiyun			};
806*4882a593Smuzhiyun		};
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun		usb_con: connector {
809*4882a593Smuzhiyun			compatible = "usb-c-connector";
810*4882a593Smuzhiyun			label = "USB-C";
811*4882a593Smuzhiyun			data-role = "dual";
812*4882a593Smuzhiyun			power-role = "dual";
813*4882a593Smuzhiyun			try-power-role = "sink";
814*4882a593Smuzhiyun			op-sink-microwatt = <1000000>;
815*4882a593Smuzhiyun			sink-pdos =
816*4882a593Smuzhiyun				<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
817*4882a593Smuzhiyun			source-pdos =
818*4882a593Smuzhiyun				<PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun			ports {
821*4882a593Smuzhiyun				#address-cells = <1>;
822*4882a593Smuzhiyun				#size-cells = <0>;
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun				port@0 {
825*4882a593Smuzhiyun					reg = <0>;
826*4882a593Smuzhiyun					usbc0_orien_sw: endpoint {
827*4882a593Smuzhiyun						remote-endpoint = <&tcphy0_orientation_switch>;
828*4882a593Smuzhiyun					};
829*4882a593Smuzhiyun				};
830*4882a593Smuzhiyun			};
831*4882a593Smuzhiyun		};
832*4882a593Smuzhiyun	};
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun};
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun&i2s1 {
837*4882a593Smuzhiyun	status = "okay";
838*4882a593Smuzhiyun	#sound-dai-cells = <0>;
839*4882a593Smuzhiyun};
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun&i2s2 {
842*4882a593Smuzhiyun	#sound-dai-cells = <0>;
843*4882a593Smuzhiyun	status = "okay";
844*4882a593Smuzhiyun};
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun&io_domains {
847*4882a593Smuzhiyun	status = "okay";
848*4882a593Smuzhiyun	bt656-supply = <&vcca_1v8>;
849*4882a593Smuzhiyun	audio-supply = <&vcca_1v8>;
850*4882a593Smuzhiyun	sdmmc-supply = <&vccio_sd>;
851*4882a593Smuzhiyun	gpio1830-supply = <&vcc_3v0>;
852*4882a593Smuzhiyun};
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun&isp0_mmu {
855*4882a593Smuzhiyun	status = "okay";
856*4882a593Smuzhiyun};
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun&isp1_mmu {
859*4882a593Smuzhiyun	status = "okay";
860*4882a593Smuzhiyun};
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun&mipi_dphy_tx1rx1 {
863*4882a593Smuzhiyun	status = "okay";
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun	ports {
866*4882a593Smuzhiyun		#address-cells = <1>;
867*4882a593Smuzhiyun		#size-cells = <0>;
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun		port@0 {
870*4882a593Smuzhiyun			reg = <0>;
871*4882a593Smuzhiyun			#address-cells = <1>;
872*4882a593Smuzhiyun			#size-cells = <0>;
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@1 {
875*4882a593Smuzhiyun				reg = <1>;
876*4882a593Smuzhiyun				/* Unlinked camera */
877*4882a593Smuzhiyun				//remote-endpoint = <&ucam_out1>;
878*4882a593Smuzhiyun				data-lanes = <1 2>;
879*4882a593Smuzhiyun			};
880*4882a593Smuzhiyun		};
881*4882a593Smuzhiyun
882*4882a593Smuzhiyun		port@1 {
883*4882a593Smuzhiyun			reg = <1>;
884*4882a593Smuzhiyun			#address-cells = <1>;
885*4882a593Smuzhiyun			#size-cells = <0>;
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun			dphy_tx1rx1_out: endpoint@0 {
888*4882a593Smuzhiyun				reg = <0>;
889*4882a593Smuzhiyun				remote-endpoint = <&isp1_mipi_in>;
890*4882a593Smuzhiyun			};
891*4882a593Smuzhiyun		};
892*4882a593Smuzhiyun	};
893*4882a593Smuzhiyun};
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun&mipi_dphy_rx0 {
896*4882a593Smuzhiyun	status = "okay";
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun	ports {
899*4882a593Smuzhiyun		#address-cells = <1>;
900*4882a593Smuzhiyun		#size-cells = <0>;
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun		port@0 {
903*4882a593Smuzhiyun			reg = <0>;
904*4882a593Smuzhiyun			#address-cells = <1>;
905*4882a593Smuzhiyun			#size-cells = <0>;
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
908*4882a593Smuzhiyun				reg = <1>;
909*4882a593Smuzhiyun				remote-endpoint = <&ucam_out0>;
910*4882a593Smuzhiyun				data-lanes = <1 2>;
911*4882a593Smuzhiyun			};
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun			mipi_in_ucam2: endpoint@2 {
914*4882a593Smuzhiyun				reg = <2>;
915*4882a593Smuzhiyun				remote-endpoint = <&ucam_out2>;
916*4882a593Smuzhiyun				data-lanes = <1 2>;
917*4882a593Smuzhiyun			};
918*4882a593Smuzhiyun		};
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun		port@1 {
921*4882a593Smuzhiyun			reg = <1>;
922*4882a593Smuzhiyun			#address-cells = <1>;
923*4882a593Smuzhiyun			#size-cells = <0>;
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun			dphy_rx0_out: endpoint@0 {
926*4882a593Smuzhiyun				reg = <0>;
927*4882a593Smuzhiyun				remote-endpoint = <&isp0_mipi_in>;
928*4882a593Smuzhiyun			};
929*4882a593Smuzhiyun		};
930*4882a593Smuzhiyun	};
931*4882a593Smuzhiyun};
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun&pcie_phy {
934*4882a593Smuzhiyun	status = "okay";
935*4882a593Smuzhiyun};
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun&pcie0 {
938*4882a593Smuzhiyun	status = "okay";
939*4882a593Smuzhiyun};
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun&pmu_io_domains {
942*4882a593Smuzhiyun	status = "okay";
943*4882a593Smuzhiyun	pmu1830-supply = <&vcc_1v8>;
944*4882a593Smuzhiyun};
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun&pwm0 {
947*4882a593Smuzhiyun	status = "okay";
948*4882a593Smuzhiyun};
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun&pwm2 {
951*4882a593Smuzhiyun	status = "okay";
952*4882a593Smuzhiyun};
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun&rkisp1_0 {
955*4882a593Smuzhiyun	status = "okay";
956*4882a593Smuzhiyun	assigned-clocks = <&cru PLL_NPLL>, <&cru SCLK_CIF_OUT_SRC>, <&cru SCLK_CIF_OUT>;
957*4882a593Smuzhiyun	assigned-clock-rates = <594000000>, <594000000>, <37125000>;
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun	port {
960*4882a593Smuzhiyun		#address-cells = <1>;
961*4882a593Smuzhiyun		#size-cells = <0>;
962*4882a593Smuzhiyun
963*4882a593Smuzhiyun		isp0_mipi_in: endpoint@0 {
964*4882a593Smuzhiyun			reg = <0>;
965*4882a593Smuzhiyun			remote-endpoint = <&dphy_rx0_out>;
966*4882a593Smuzhiyun		};
967*4882a593Smuzhiyun	};
968*4882a593Smuzhiyun};
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun&rkisp1_1 {
971*4882a593Smuzhiyun	status = "okay";
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun	port {
974*4882a593Smuzhiyun		#address-cells = <1>;
975*4882a593Smuzhiyun		#size-cells = <0>;
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun		isp1_mipi_in: endpoint@0 {
978*4882a593Smuzhiyun			reg = <0>;
979*4882a593Smuzhiyun			remote-endpoint = <&dphy_tx1rx1_out>;
980*4882a593Smuzhiyun		};
981*4882a593Smuzhiyun	};
982*4882a593Smuzhiyun};
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun&rockchip_suspend {
985*4882a593Smuzhiyun	status = "okay";
986*4882a593Smuzhiyun	rockchip,sleep-debug-en = <1>;
987*4882a593Smuzhiyun	rockchip,sleep-mode-config = <
988*4882a593Smuzhiyun		(0
989*4882a593Smuzhiyun		| RKPM_SLP_ARMPD
990*4882a593Smuzhiyun		| RKPM_SLP_PERILPPD
991*4882a593Smuzhiyun		| RKPM_SLP_DDR_RET
992*4882a593Smuzhiyun		| RKPM_SLP_PLLPD
993*4882a593Smuzhiyun		| RKPM_SLP_CENTER_PD
994*4882a593Smuzhiyun		| RKPM_SLP_OSC_DIS
995*4882a593Smuzhiyun		| RKPM_SLP_AP_PWROFF
996*4882a593Smuzhiyun		)
997*4882a593Smuzhiyun	>;
998*4882a593Smuzhiyun	rockchip,wakeup-config = <RKPM_GPIO_WKUP_EN>;
999*4882a593Smuzhiyun	rockchip,pwm-regulator-config = <PWM2_REGULATOR_EN>;
1000*4882a593Smuzhiyun	rockchip,power-ctrl =
1001*4882a593Smuzhiyun		<&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>,
1002*4882a593Smuzhiyun		<&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
1003*4882a593Smuzhiyun};
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun&route_edp {
1006*4882a593Smuzhiyun	status = "okay";
1007*4882a593Smuzhiyun};
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun&saradc {
1010*4882a593Smuzhiyun	status = "okay";
1011*4882a593Smuzhiyun	vref-supply = <&vcc_1v8>;
1012*4882a593Smuzhiyun};
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun&sdmmc {
1015*4882a593Smuzhiyun	sd-uhs-sdr12;
1016*4882a593Smuzhiyun	sd-uhs-sdr25;
1017*4882a593Smuzhiyun	sd-uhs-sdr50;
1018*4882a593Smuzhiyun	sd-uhs-sdr104;
1019*4882a593Smuzhiyun};
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun&spi1 {
1022*4882a593Smuzhiyun	status = "okay";
1023*4882a593Smuzhiyun	max-freq = <48000000>; /* spi internal clk, don't modify */
1024*4882a593Smuzhiyun	spi_dev@0 {
1025*4882a593Smuzhiyun		compatible = "rockchip,spidev";
1026*4882a593Smuzhiyun		reg = <0>;
1027*4882a593Smuzhiyun		spi-max-frequency = <12000000>;
1028*4882a593Smuzhiyun		spi-lsb-first;
1029*4882a593Smuzhiyun	};
1030*4882a593Smuzhiyun};
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun&tcphy0 {
1033*4882a593Smuzhiyun	status = "okay";
1034*4882a593Smuzhiyun	orientation-switch;
1035*4882a593Smuzhiyun	port {
1036*4882a593Smuzhiyun		#address-cells = <1>;
1037*4882a593Smuzhiyun		#size-cells = <0>;
1038*4882a593Smuzhiyun		tcphy0_orientation_switch: endpoint@0 {
1039*4882a593Smuzhiyun			reg = <0>;
1040*4882a593Smuzhiyun			remote-endpoint = <&usbc0_orien_sw>;
1041*4882a593Smuzhiyun		};
1042*4882a593Smuzhiyun	};
1043*4882a593Smuzhiyun};
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun&tcphy1 {
1046*4882a593Smuzhiyun	status = "okay";
1047*4882a593Smuzhiyun};
1048*4882a593Smuzhiyun
1049*4882a593Smuzhiyun&tsadc {
1050*4882a593Smuzhiyun	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
1051*4882a593Smuzhiyun	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
1052*4882a593Smuzhiyun	status = "okay";
1053*4882a593Smuzhiyun};
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun&u2phy0 {
1056*4882a593Smuzhiyun	status = "okay";
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun	u2phy0_otg: otg-port {
1059*4882a593Smuzhiyun		status = "okay";
1060*4882a593Smuzhiyun	};
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun	u2phy0_host: host-port {
1063*4882a593Smuzhiyun		phy-supply = <&vcc5v0_usb>;
1064*4882a593Smuzhiyun		status = "okay";
1065*4882a593Smuzhiyun	};
1066*4882a593Smuzhiyun};
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun&u2phy1 {
1069*4882a593Smuzhiyun	status = "okay";
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun	u2phy1_otg: otg-port {
1072*4882a593Smuzhiyun		status = "okay";
1073*4882a593Smuzhiyun	};
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun	u2phy1_host: host-port {
1076*4882a593Smuzhiyun		phy-supply = <&vcc5v0_usb>;
1077*4882a593Smuzhiyun		status = "okay";
1078*4882a593Smuzhiyun	};
1079*4882a593Smuzhiyun};
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun&uart0 {
1082*4882a593Smuzhiyun	pinctrl-names = "default";
1083*4882a593Smuzhiyun	pinctrl-0 = <&uart0_xfer &uart0_cts>;
1084*4882a593Smuzhiyun	status = "okay";
1085*4882a593Smuzhiyun};
1086*4882a593Smuzhiyun
1087*4882a593Smuzhiyun&usb_host0_ehci {
1088*4882a593Smuzhiyun	status = "okay";
1089*4882a593Smuzhiyun};
1090*4882a593Smuzhiyun
1091*4882a593Smuzhiyun&usb_host1_ehci {
1092*4882a593Smuzhiyun	status = "okay";
1093*4882a593Smuzhiyun};
1094*4882a593Smuzhiyun&usb_host0_ohci {
1095*4882a593Smuzhiyun	status = "okay";
1096*4882a593Smuzhiyun};
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun&usb_host1_ohci {
1099*4882a593Smuzhiyun	status = "okay";
1100*4882a593Smuzhiyun};
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun&usbdrd3_0 {
1103*4882a593Smuzhiyun	status = "okay";
1104*4882a593Smuzhiyun};
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun&usbdrd3_1 {
1107*4882a593Smuzhiyun	status = "okay";
1108*4882a593Smuzhiyun};
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun&usbdrd_dwc3_0 {
1111*4882a593Smuzhiyun	status = "okay";
1112*4882a593Smuzhiyun	usb-role-switch;
1113*4882a593Smuzhiyun	port {
1114*4882a593Smuzhiyun		#address-cells = <1>;
1115*4882a593Smuzhiyun		#size-cells = <0>;
1116*4882a593Smuzhiyun		dwc3_0_role_switch: endpoint@0 {
1117*4882a593Smuzhiyun			reg = <0>;
1118*4882a593Smuzhiyun			remote-endpoint = <&usbc0_role_sw>;
1119*4882a593Smuzhiyun		};
1120*4882a593Smuzhiyun	};
1121*4882a593Smuzhiyun};
1122*4882a593Smuzhiyun
1123*4882a593Smuzhiyun&usbdrd_dwc3_1 {
1124*4882a593Smuzhiyun	status = "okay";
1125*4882a593Smuzhiyun};
1126*4882a593Smuzhiyun
1127*4882a593Smuzhiyun&vopb {
1128*4882a593Smuzhiyun	status = "okay";
1129*4882a593Smuzhiyun};
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun&vopb_mmu {
1132*4882a593Smuzhiyun	status = "okay";
1133*4882a593Smuzhiyun};
1134*4882a593Smuzhiyun
1135*4882a593Smuzhiyun&vopl {
1136*4882a593Smuzhiyun	status = "okay";
1137*4882a593Smuzhiyun};
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun&vopl_mmu {
1140*4882a593Smuzhiyun	status = "okay";
1141*4882a593Smuzhiyun};
1142*4882a593Smuzhiyun
1143*4882a593Smuzhiyun&pinctrl {
1144*4882a593Smuzhiyun	pinctrl-names = "default";
1145*4882a593Smuzhiyun	pinctrl-0 = <&npu_ref_clk>;
1146*4882a593Smuzhiyun
1147*4882a593Smuzhiyun	bq2570 {
1148*4882a593Smuzhiyun		charger_ok_int: charger-ok-int {
1149*4882a593Smuzhiyun			rockchip,pins =
1150*4882a593Smuzhiyun				<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
1151*4882a593Smuzhiyun			};
1152*4882a593Smuzhiyun	};
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun	headphone {
1155*4882a593Smuzhiyun		hp_det: hp-det {
1156*4882a593Smuzhiyun			rockchip,pins =
1157*4882a593Smuzhiyun				<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
1158*4882a593Smuzhiyun		};
1159*4882a593Smuzhiyun	};
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun	lcd_rst {
1162*4882a593Smuzhiyun		lcd_rst_gpio: lcd-rst-gpio {
1163*4882a593Smuzhiyun			rockchip,pins =
1164*4882a593Smuzhiyun				<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
1165*4882a593Smuzhiyun		};
1166*4882a593Smuzhiyun	};
1167*4882a593Smuzhiyun
1168*4882a593Smuzhiyun	npu_clk {
1169*4882a593Smuzhiyun		npu_ref_clk: npu-ref-clk {
1170*4882a593Smuzhiyun		     rockchip,pins =
1171*4882a593Smuzhiyun			     <0 RK_PA2 1 &pcfg_pull_none>;
1172*4882a593Smuzhiyun	     };
1173*4882a593Smuzhiyun	};
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun	pmic {
1176*4882a593Smuzhiyun		pmic_int_l: pmic-int-l {
1177*4882a593Smuzhiyun			rockchip,pins =
1178*4882a593Smuzhiyun				<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
1179*4882a593Smuzhiyun		};
1180*4882a593Smuzhiyun		vsel1_gpio: vsel1-gpio {
1181*4882a593Smuzhiyun			rockchip,pins =
1182*4882a593Smuzhiyun				<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
1183*4882a593Smuzhiyun		};
1184*4882a593Smuzhiyun		vsel2_gpio: vsel2-gpio {
1185*4882a593Smuzhiyun			rockchip,pins =
1186*4882a593Smuzhiyun				<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
1187*4882a593Smuzhiyun		};
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun		soc_slppin_gpio: soc-slppin-gpio {
1190*4882a593Smuzhiyun			rockchip,pins =
1191*4882a593Smuzhiyun				<1 RK_PA5 RK_FUNC_GPIO &pcfg_output_low>;
1192*4882a593Smuzhiyun		};
1193*4882a593Smuzhiyun
1194*4882a593Smuzhiyun		soc_slppin_slp: soc-slppin-slp {
1195*4882a593Smuzhiyun			rockchip,pins =
1196*4882a593Smuzhiyun				<1 RK_PA5 1 &pcfg_pull_none>;
1197*4882a593Smuzhiyun		};
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun		soc_slppin_rst: soc-slppin-rst {
1200*4882a593Smuzhiyun			rockchip,pins =
1201*4882a593Smuzhiyun				<1 RK_PA5 2 &pcfg_pull_none>;
1202*4882a593Smuzhiyun		};
1203*4882a593Smuzhiyun	};
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun	usb-typec {
1206*4882a593Smuzhiyun		usbc0_int: usbc0-int {
1207*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
1208*4882a593Smuzhiyun		};
1209*4882a593Smuzhiyun
1210*4882a593Smuzhiyun		vcc5v0_typec0_en: vcc5v0-typec0-en {
1211*4882a593Smuzhiyun			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
1212*4882a593Smuzhiyun		};
1213*4882a593Smuzhiyun	};
1214*4882a593Smuzhiyun
1215*4882a593Smuzhiyun	sdio-pwrseq {
1216*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
1217*4882a593Smuzhiyun			rockchip,pins =
1218*4882a593Smuzhiyun				<2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
1219*4882a593Smuzhiyun		};
1220*4882a593Smuzhiyun	};
1221*4882a593Smuzhiyun
1222*4882a593Smuzhiyun	sdmmc {
1223*4882a593Smuzhiyun		sdmmc_bus1: sdmmc-bus1 {
1224*4882a593Smuzhiyun			rockchip,pins =
1225*4882a593Smuzhiyun				<4 RK_PB0 1 &pcfg_pull_up_10ma>;
1226*4882a593Smuzhiyun		};
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun		sdmmc_bus4: sdmmc-bus4 {
1229*4882a593Smuzhiyun			rockchip,pins =
1230*4882a593Smuzhiyun				<4 RK_PB0 1 &pcfg_pull_up_10ma>,
1231*4882a593Smuzhiyun				<4 RK_PB1 1 &pcfg_pull_up_10ma>,
1232*4882a593Smuzhiyun				<4 RK_PB2 1 &pcfg_pull_up_10ma>,
1233*4882a593Smuzhiyun				<4 RK_PB3 1 &pcfg_pull_up_10ma>;
1234*4882a593Smuzhiyun		};
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun		sdmmc_clk: sdmmc-clk {
1237*4882a593Smuzhiyun			rockchip,pins =
1238*4882a593Smuzhiyun				<4 RK_PB4 1 &pcfg_pull_none_10ma>;
1239*4882a593Smuzhiyun		};
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun		sdmmc_cmd: sdmmc-cmd {
1242*4882a593Smuzhiyun			rockchip,pins =
1243*4882a593Smuzhiyun				<4 RK_PB5 1 &pcfg_pull_up_10ma>;
1244*4882a593Smuzhiyun		};
1245*4882a593Smuzhiyun	};
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun	tp_irq {
1248*4882a593Smuzhiyun		tp_irq_gpio: tp-irq-gpio {
1249*4882a593Smuzhiyun			rockchip,pins =
1250*4882a593Smuzhiyun				<3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
1251*4882a593Smuzhiyun		};
1252*4882a593Smuzhiyun	};
1253*4882a593Smuzhiyun
1254*4882a593Smuzhiyun	wireless-bluetooth {
1255*4882a593Smuzhiyun		bt_irq_gpio: bt-irq-gpio {
1256*4882a593Smuzhiyun			rockchip,pins =
1257*4882a593Smuzhiyun				<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
1258*4882a593Smuzhiyun		};
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun		uart0_gpios: uart0-gpios {
1261*4882a593Smuzhiyun			rockchip,pins =
1262*4882a593Smuzhiyun				<2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
1263*4882a593Smuzhiyun		};
1264*4882a593Smuzhiyun	};
1265*4882a593Smuzhiyun};
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE.  PUT IT ABOVE PINCTRL */
1268*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE.  PUT IT ABOVE PINCTRL */
1269*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE.  PUT IT ABOVE PINCTRL */
1270