1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/soc/rockchip-system-status.h> 14#include <dt-bindings/suspend/rockchip-rk3399.h> 15#include <dt-bindings/thermal/thermal.h> 16 17#include "rk3399-dram-default-timing.dtsi" 18 19/ { 20 compatible = "rockchip,rk3399"; 21 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dsi0 = &dsi; 28 dsi1 = &dsi1; 29 ethernet0 = &gmac; 30 gpio0 = &gpio0; 31 gpio1 = &gpio1; 32 gpio2 = &gpio2; 33 gpio3 = &gpio3; 34 gpio4 = &gpio4; 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 i2c2 = &i2c2; 38 i2c3 = &i2c3; 39 i2c4 = &i2c4; 40 i2c5 = &i2c5; 41 i2c6 = &i2c6; 42 i2c7 = &i2c7; 43 i2c8 = &i2c8; 44 mmc0 = &sdio0; 45 mmc1 = &sdmmc; 46 mmc2 = &sdhci; 47 serial0 = &uart0; 48 serial1 = &uart1; 49 serial2 = &uart2; 50 serial3 = &uart3; 51 serial4 = &uart4; 52 }; 53 54 cpus { 55 #address-cells = <2>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu_l0>; 62 }; 63 core1 { 64 cpu = <&cpu_l1>; 65 }; 66 core2 { 67 cpu = <&cpu_l2>; 68 }; 69 core3 { 70 cpu = <&cpu_l3>; 71 }; 72 }; 73 74 cluster1 { 75 core0 { 76 cpu = <&cpu_b0>; 77 }; 78 core1 { 79 cpu = <&cpu_b1>; 80 }; 81 }; 82 }; 83 84 cpu_l0: cpu@0 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x0>; 88 enable-method = "psci"; 89 capacity-dmips-mhz = <485>; 90 clocks = <&cru ARMCLKL>; 91 #cooling-cells = <2>; /* min followed by max */ 92 dynamic-power-coefficient = <100>; 93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 94 }; 95 96 cpu_l1: cpu@1 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x1>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <485>; 102 clocks = <&cru ARMCLKL>; 103 #cooling-cells = <2>; /* min followed by max */ 104 dynamic-power-coefficient = <100>; 105 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 106 }; 107 108 cpu_l2: cpu@2 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x0 0x2>; 112 enable-method = "psci"; 113 capacity-dmips-mhz = <485>; 114 clocks = <&cru ARMCLKL>; 115 #cooling-cells = <2>; /* min followed by max */ 116 dynamic-power-coefficient = <100>; 117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 118 }; 119 120 cpu_l3: cpu@3 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x0 0x3>; 124 enable-method = "psci"; 125 capacity-dmips-mhz = <485>; 126 clocks = <&cru ARMCLKL>; 127 #cooling-cells = <2>; /* min followed by max */ 128 dynamic-power-coefficient = <100>; 129 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 130 }; 131 132 cpu_b0: cpu@100 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a72"; 135 reg = <0x0 0x100>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <1024>; 138 clocks = <&cru ARMCLKB>; 139 #cooling-cells = <2>; /* min followed by max */ 140 dynamic-power-coefficient = <436>; 141 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 142 }; 143 144 cpu_b1: cpu@101 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a72"; 147 reg = <0x0 0x101>; 148 enable-method = "psci"; 149 capacity-dmips-mhz = <1024>; 150 clocks = <&cru ARMCLKB>; 151 #cooling-cells = <2>; /* min followed by max */ 152 dynamic-power-coefficient = <436>; 153 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 154 }; 155 156 idle-states { 157 entry-method = "psci"; 158 159 CPU_SLEEP: cpu-sleep { 160 compatible = "arm,idle-state"; 161 local-timer-stop; 162 arm,psci-suspend-param = <0x0010000>; 163 entry-latency-us = <120>; 164 exit-latency-us = <250>; 165 min-residency-us = <900>; 166 }; 167 168 CLUSTER_SLEEP: cluster-sleep { 169 compatible = "arm,idle-state"; 170 local-timer-stop; 171 arm,psci-suspend-param = <0x1010000>; 172 entry-latency-us = <400>; 173 exit-latency-us = <500>; 174 min-residency-us = <2000>; 175 }; 176 }; 177 }; 178 179 display_subsystem: display-subsystem { 180 compatible = "rockchip,display-subsystem"; 181 ports = <&vopl_out>, <&vopb_out>; 182 clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>; 183 clock-names = "hdmi-tmds-pll", "default-vop-pll"; 184 }; 185 186 pmu_a53 { 187 compatible = "arm,cortex-a53-pmu"; 188 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 189 }; 190 191 pmu_a72 { 192 compatible = "arm,cortex-a72-pmu"; 193 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 194 }; 195 196 psci { 197 compatible = "arm,psci-1.0"; 198 method = "smc"; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 204 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 205 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 206 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 207 arm,no-tick-in-suspend; 208 }; 209 210 xin24m: xin24m { 211 compatible = "fixed-clock"; 212 clock-frequency = <24000000>; 213 clock-output-names = "xin24m"; 214 #clock-cells = <0>; 215 }; 216 217 dummy_cpll: dummy_cpll { 218 compatible = "fixed-clock"; 219 clock-frequency = <0>; 220 clock-output-names = "dummy_cpll"; 221 #clock-cells = <0>; 222 }; 223 224 dummy_vpll: dummy_vpll { 225 compatible = "fixed-clock"; 226 clock-frequency = <0>; 227 clock-output-names = "dummy_vpll"; 228 #clock-cells = <0>; 229 }; 230 231 amba: bus { 232 compatible = "simple-bus"; 233 #address-cells = <2>; 234 #size-cells = <2>; 235 ranges; 236 237 dmac_bus: dma-controller@ff6d0000 { 238 compatible = "arm,pl330", "arm,primecell"; 239 reg = <0x0 0xff6d0000 0x0 0x4000>; 240 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 241 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 242 #dma-cells = <1>; 243 arm,pl330-periph-burst; 244 clocks = <&cru ACLK_DMAC0_PERILP>; 245 clock-names = "apb_pclk"; 246 }; 247 248 dmac_peri: dma-controller@ff6e0000 { 249 compatible = "arm,pl330", "arm,primecell"; 250 reg = <0x0 0xff6e0000 0x0 0x4000>; 251 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 252 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 253 #dma-cells = <1>; 254 arm,pl330-periph-burst; 255 clocks = <&cru ACLK_DMAC1_PERILP>; 256 clock-names = "apb_pclk"; 257 }; 258 }; 259 260 pcie0: pcie@f8000000 { 261 compatible = "rockchip,rk3399-pcie"; 262 reg = <0x0 0xf8000000 0x0 0x2000000>, 263 <0x0 0xfd000000 0x0 0x1000000>; 264 reg-names = "axi-base", "apb-base"; 265 device_type = "pci"; 266 #address-cells = <3>; 267 #size-cells = <2>; 268 #interrupt-cells = <1>; 269 aspm-no-l0s; 270 bus-range = <0x0 0x1f>; 271 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 272 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 273 clock-names = "aclk", "aclk-perf", 274 "hclk", "pm"; 275 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 276 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 277 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 278 interrupt-names = "sys", "legacy", "client"; 279 interrupt-map-mask = <0 0 0 7>; 280 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 281 <0 0 0 2 &pcie0_intc 1>, 282 <0 0 0 3 &pcie0_intc 2>, 283 <0 0 0 4 &pcie0_intc 3>; 284 max-link-speed = <1>; 285 msi-map = <0x0 &its 0x0 0x1000>; 286 phys = <&pcie_phy 0>, <&pcie_phy 1>, 287 <&pcie_phy 2>, <&pcie_phy 3>; 288 phy-names = "pcie-phy-0", "pcie-phy-1", 289 "pcie-phy-2", "pcie-phy-3"; 290 power-domains = <&power RK3399_PD_PERIHP>; 291 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 292 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 293 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 294 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 295 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 296 <&cru SRST_A_PCIE>; 297 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 298 "pm", "pclk", "aclk"; 299 status = "disabled"; 300 301 pcie0_intc: interrupt-controller { 302 interrupt-controller; 303 #address-cells = <0>; 304 #interrupt-cells = <1>; 305 }; 306 }; 307 308 gmac: ethernet@fe300000 { 309 compatible = "rockchip,rk3399-gmac"; 310 reg = <0x0 0xfe300000 0x0 0x10000>; 311 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 312 interrupt-names = "macirq"; 313 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 314 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 315 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 316 <&cru PCLK_GMAC>; 317 clock-names = "stmmaceth", "mac_clk_rx", 318 "mac_clk_tx", "clk_mac_ref", 319 "clk_mac_refout", "aclk_mac", 320 "pclk_mac"; 321 power-domains = <&power RK3399_PD_GMAC>; 322 resets = <&cru SRST_A_GMAC>; 323 reset-names = "stmmaceth"; 324 rockchip,grf = <&grf>; 325 snps,txpbl = <0x4>; 326 status = "disabled"; 327 }; 328 329 sdio0: mmc@fe310000 { 330 compatible = "rockchip,rk3399-dw-mshc", 331 "rockchip,rk3288-dw-mshc"; 332 reg = <0x0 0xfe310000 0x0 0x4000>; 333 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 334 max-frequency = <150000000>; 335 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 336 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 337 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 338 fifo-depth = <0x100>; 339 power-domains = <&power RK3399_PD_SDIOAUDIO>; 340 resets = <&cru SRST_SDIO0>; 341 reset-names = "reset"; 342 status = "disabled"; 343 }; 344 345 sdmmc: mmc@fe320000 { 346 compatible = "rockchip,rk3399-dw-mshc", 347 "rockchip,rk3288-dw-mshc"; 348 reg = <0x0 0xfe320000 0x0 0x4000>; 349 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 350 max-frequency = <150000000>; 351 assigned-clocks = <&cru HCLK_SD>; 352 assigned-clock-rates = <200000000>; 353 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 354 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 355 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 356 fifo-depth = <0x100>; 357 power-domains = <&power RK3399_PD_SD>; 358 resets = <&cru SRST_SDMMC>; 359 reset-names = "reset"; 360 status = "disabled"; 361 }; 362 363 sdhci: sdhci@fe330000 { 364 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 365 reg = <0x0 0xfe330000 0x0 0x10000>; 366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 367 arasan,soc-ctl-syscon = <&grf>; 368 assigned-clocks = <&cru SCLK_EMMC>; 369 assigned-clock-rates = <200000000>; 370 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 371 clock-names = "clk_xin", "clk_ahb"; 372 clock-output-names = "emmc_cardclock"; 373 #clock-cells = <0>; 374 phys = <&emmc_phy>; 375 phy-names = "phy_arasan"; 376 power-domains = <&power RK3399_PD_EMMC>; 377 disable-cqe-dcmd; 378 disable-cqe; 379 status = "disabled"; 380 }; 381 382 usb_host0_ehci: usb@fe380000 { 383 compatible = "generic-ehci"; 384 reg = <0x0 0xfe380000 0x0 0x20000>; 385 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 386 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 387 <&u2phy0>; 388 phys = <&u2phy0_host>; 389 phy-names = "usb"; 390 status = "disabled"; 391 }; 392 393 usb_host0_ohci: usb@fe3a0000 { 394 compatible = "generic-ohci"; 395 reg = <0x0 0xfe3a0000 0x0 0x20000>; 396 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 397 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 398 <&u2phy0>; 399 phys = <&u2phy0_host>; 400 phy-names = "usb"; 401 status = "disabled"; 402 }; 403 404 usb_host1_ehci: usb@fe3c0000 { 405 compatible = "generic-ehci"; 406 reg = <0x0 0xfe3c0000 0x0 0x20000>; 407 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 408 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 409 <&u2phy1>; 410 phys = <&u2phy1_host>; 411 phy-names = "usb"; 412 status = "disabled"; 413 }; 414 415 usb_host1_ohci: usb@fe3e0000 { 416 compatible = "generic-ohci"; 417 reg = <0x0 0xfe3e0000 0x0 0x20000>; 418 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 419 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 420 <&u2phy1>; 421 phys = <&u2phy1_host>; 422 phy-names = "usb"; 423 status = "disabled"; 424 }; 425 426 usbdrd3_0: usb@fe800000 { 427 compatible = "rockchip,rk3399-dwc3"; 428 #address-cells = <2>; 429 #size-cells = <2>; 430 ranges; 431 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 432 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 433 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 434 clock-names = "ref_clk", "suspend_clk", 435 "bus_clk", "aclk_usb3_rksoc_axi_perf", 436 "aclk_usb3", "grf_clk"; 437 status = "disabled"; 438 439 usbdrd_dwc3_0: usb@fe800000 { 440 compatible = "snps,dwc3"; 441 reg = <0x0 0xfe800000 0x0 0x100000>; 442 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 443 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 444 <&cru SCLK_USB3OTG0_SUSPEND>; 445 clock-names = "ref", "bus_early", "suspend"; 446 resets = <&cru SRST_A_USB3_OTG0>; 447 reset-names = "usb3-otg"; 448 dr_mode = "otg"; 449 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 450 phy-names = "usb2-phy", "usb3-phy"; 451 phy_type = "utmi_wide"; 452 snps,dis_enblslpm_quirk; 453 snps,dis-u1-entry-quirk; 454 snps,dis-u2-entry-quirk; 455 snps,dis-u2-freeclk-exists-quirk; 456 snps,dis_u2_susphy_quirk; 457 snps,dis-del-phy-power-chg-quirk; 458 snps,dis-tx-ipgap-linecheck-quirk; 459 snps,parkmode-disable-ss-quirk; 460 power-domains = <&power RK3399_PD_USB3>; 461 status = "disabled"; 462 }; 463 }; 464 465 usbdrd3_1: usb@fe900000 { 466 compatible = "rockchip,rk3399-dwc3"; 467 #address-cells = <2>; 468 #size-cells = <2>; 469 ranges; 470 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 471 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 472 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 473 clock-names = "ref_clk", "suspend_clk", 474 "bus_clk", "aclk_usb3_rksoc_axi_perf", 475 "aclk_usb3", "grf_clk"; 476 status = "disabled"; 477 478 usbdrd_dwc3_1: usb@fe900000 { 479 compatible = "snps,dwc3"; 480 reg = <0x0 0xfe900000 0x0 0x100000>; 481 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 482 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 483 <&cru SCLK_USB3OTG1_SUSPEND>; 484 clock-names = "ref", "bus_early", "suspend"; 485 resets = <&cru SRST_A_USB3_OTG1>; 486 reset-names = "usb3-otg"; 487 dr_mode = "otg"; 488 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 489 phy-names = "usb2-phy", "usb3-phy"; 490 phy_type = "utmi_wide"; 491 snps,dis_enblslpm_quirk; 492 snps,dis-u2-freeclk-exists-quirk; 493 snps,dis_u2_susphy_quirk; 494 snps,dis-del-phy-power-chg-quirk; 495 snps,dis-tx-ipgap-linecheck-quirk; 496 snps,parkmode-disable-ss-quirk; 497 power-domains = <&power RK3399_PD_USB3>; 498 status = "disabled"; 499 }; 500 }; 501 502 cdn_dp: dp@fec00000 { 503 compatible = "rockchip,rk3399-cdn-dp"; 504 reg = <0x0 0xfec00000 0x0 0x100000>; 505 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 506 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 507 assigned-clock-rates = <100000000>, <200000000>; 508 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 509 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 510 clock-names = "core-clk", "pclk", "spdif", "grf"; 511 phys = <&tcphy0_dp>, <&tcphy1_dp>; 512 power-domains = <&power RK3399_PD_HDCP>; 513 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 514 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 515 reset-names = "spdif", "dptx", "apb", "core"; 516 rockchip,grf = <&grf>; 517 #sound-dai-cells = <1>; 518 status = "disabled"; 519 520 ports { 521 dp_in: port { 522 #address-cells = <1>; 523 #size-cells = <0>; 524 525 dp_in_vopb: endpoint@0 { 526 reg = <0>; 527 remote-endpoint = <&vopb_out_dp>; 528 }; 529 530 dp_in_vopl: endpoint@1 { 531 reg = <1>; 532 remote-endpoint = <&vopl_out_dp>; 533 }; 534 }; 535 }; 536 }; 537 538 gic: interrupt-controller@fee00000 { 539 compatible = "arm,gic-v3"; 540 #interrupt-cells = <4>; 541 #address-cells = <2>; 542 #size-cells = <2>; 543 ranges; 544 interrupt-controller; 545 546 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 547 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 548 <0x0 0xfff00000 0 0x10000>, /* GICC */ 549 <0x0 0xfff10000 0 0x10000>, /* GICH */ 550 <0x0 0xfff20000 0 0x10000>; /* GICV */ 551 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 552 its: interrupt-controller@fee20000 { 553 compatible = "arm,gic-v3-its"; 554 msi-controller; 555 #msi-cells = <1>; 556 reg = <0x0 0xfee20000 0x0 0x20000>; 557 }; 558 559 ppi-partitions { 560 ppi_cluster0: interrupt-partition-0 { 561 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 562 }; 563 564 ppi_cluster1: interrupt-partition-1 { 565 affinity = <&cpu_b0 &cpu_b1>; 566 }; 567 }; 568 }; 569 570 saradc: saradc@ff100000 { 571 compatible = "rockchip,rk3399-saradc"; 572 reg = <0x0 0xff100000 0x0 0x100>; 573 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 574 #io-channel-cells = <1>; 575 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 576 clock-names = "saradc", "apb_pclk"; 577 resets = <&cru SRST_P_SARADC>; 578 reset-names = "saradc-apb"; 579 status = "disabled"; 580 }; 581 582 i2c1: i2c@ff110000 { 583 compatible = "rockchip,rk3399-i2c"; 584 reg = <0x0 0xff110000 0x0 0x1000>; 585 assigned-clocks = <&cru SCLK_I2C1>; 586 assigned-clock-rates = <200000000>; 587 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 588 clock-names = "i2c", "pclk"; 589 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&i2c1_xfer>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 status = "disabled"; 595 }; 596 597 i2c2: i2c@ff120000 { 598 compatible = "rockchip,rk3399-i2c"; 599 reg = <0x0 0xff120000 0x0 0x1000>; 600 assigned-clocks = <&cru SCLK_I2C2>; 601 assigned-clock-rates = <200000000>; 602 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 603 clock-names = "i2c", "pclk"; 604 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 605 pinctrl-names = "default"; 606 pinctrl-0 = <&i2c2_xfer>; 607 #address-cells = <1>; 608 #size-cells = <0>; 609 status = "disabled"; 610 }; 611 612 i2c3: i2c@ff130000 { 613 compatible = "rockchip,rk3399-i2c"; 614 reg = <0x0 0xff130000 0x0 0x1000>; 615 assigned-clocks = <&cru SCLK_I2C3>; 616 assigned-clock-rates = <200000000>; 617 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 618 clock-names = "i2c", "pclk"; 619 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&i2c3_xfer>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 status = "disabled"; 625 }; 626 627 i2c5: i2c@ff140000 { 628 compatible = "rockchip,rk3399-i2c"; 629 reg = <0x0 0xff140000 0x0 0x1000>; 630 assigned-clocks = <&cru SCLK_I2C5>; 631 assigned-clock-rates = <200000000>; 632 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 633 clock-names = "i2c", "pclk"; 634 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&i2c5_xfer>; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 status = "disabled"; 640 }; 641 642 i2c6: i2c@ff150000 { 643 compatible = "rockchip,rk3399-i2c"; 644 reg = <0x0 0xff150000 0x0 0x1000>; 645 assigned-clocks = <&cru SCLK_I2C6>; 646 assigned-clock-rates = <200000000>; 647 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 648 clock-names = "i2c", "pclk"; 649 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 650 pinctrl-names = "default"; 651 pinctrl-0 = <&i2c6_xfer>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 status = "disabled"; 655 }; 656 657 i2c7: i2c@ff160000 { 658 compatible = "rockchip,rk3399-i2c"; 659 reg = <0x0 0xff160000 0x0 0x1000>; 660 assigned-clocks = <&cru SCLK_I2C7>; 661 assigned-clock-rates = <200000000>; 662 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 663 clock-names = "i2c", "pclk"; 664 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 665 pinctrl-names = "default"; 666 pinctrl-0 = <&i2c7_xfer>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 status = "disabled"; 670 }; 671 672 uart0: serial@ff180000 { 673 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 674 reg = <0x0 0xff180000 0x0 0x100>; 675 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 676 clock-names = "baudclk", "apb_pclk"; 677 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 678 reg-shift = <2>; 679 reg-io-width = <4>; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&uart0_xfer>; 682 status = "disabled"; 683 }; 684 685 uart1: serial@ff190000 { 686 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 687 reg = <0x0 0xff190000 0x0 0x100>; 688 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 689 clock-names = "baudclk", "apb_pclk"; 690 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 691 reg-shift = <2>; 692 reg-io-width = <4>; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&uart1_xfer>; 695 status = "disabled"; 696 }; 697 698 uart2: serial@ff1a0000 { 699 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 700 reg = <0x0 0xff1a0000 0x0 0x100>; 701 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 702 clock-names = "baudclk", "apb_pclk"; 703 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 704 reg-shift = <2>; 705 reg-io-width = <4>; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&uart2c_xfer>; 708 status = "disabled"; 709 }; 710 711 uart3: serial@ff1b0000 { 712 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 713 reg = <0x0 0xff1b0000 0x0 0x100>; 714 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 715 clock-names = "baudclk", "apb_pclk"; 716 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 717 reg-shift = <2>; 718 reg-io-width = <4>; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&uart3_xfer>; 721 status = "disabled"; 722 }; 723 724 spi0: spi@ff1c0000 { 725 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 726 reg = <0x0 0xff1c0000 0x0 0x1000>; 727 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 728 clock-names = "spiclk", "apb_pclk"; 729 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 730 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 731 dma-names = "tx", "rx"; 732 pinctrl-names = "default"; 733 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 status = "disabled"; 737 }; 738 739 spi1: spi@ff1d0000 { 740 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 741 reg = <0x0 0xff1d0000 0x0 0x1000>; 742 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 743 clock-names = "spiclk", "apb_pclk"; 744 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 745 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 746 dma-names = "tx", "rx"; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 status = "disabled"; 752 }; 753 754 spi2: spi@ff1e0000 { 755 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 756 reg = <0x0 0xff1e0000 0x0 0x1000>; 757 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 758 clock-names = "spiclk", "apb_pclk"; 759 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 760 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 761 dma-names = "tx", "rx"; 762 pinctrl-names = "default"; 763 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 status = "disabled"; 767 }; 768 769 spi4: spi@ff1f0000 { 770 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 771 reg = <0x0 0xff1f0000 0x0 0x1000>; 772 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 773 clock-names = "spiclk", "apb_pclk"; 774 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 775 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 776 dma-names = "tx", "rx"; 777 pinctrl-names = "default"; 778 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 status = "disabled"; 782 }; 783 784 spi5: spi@ff200000 { 785 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 786 reg = <0x0 0xff200000 0x0 0x1000>; 787 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 788 clock-names = "spiclk", "apb_pclk"; 789 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 790 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 791 dma-names = "tx", "rx"; 792 pinctrl-names = "default"; 793 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 794 power-domains = <&power RK3399_PD_SDIOAUDIO>; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 status = "disabled"; 798 }; 799 800 thermal_zones: thermal-zones { 801 soc_thermal: cpu_thermal: cpu-thermal { 802 polling-delay-passive = <20>; 803 polling-delay = <1000>; 804 sustainable-power = <1000>; /* milliwatts */ 805 806 thermal-sensors = <&tsadc 0>; 807 808 trips { 809 threshold: cpu_alert0: cpu_alert0 { 810 temperature = <70000>; 811 hysteresis = <2000>; 812 type = "passive"; 813 }; 814 target: cpu_alert1: cpu_alert1 { 815 temperature = <85000>; 816 hysteresis = <2000>; 817 type = "passive"; 818 }; 819 soc_crit: cpu_crit: cpu_crit { 820 temperature = <115000>; /* millicelsius */ 821 hysteresis = <2000>; /* millicelsius */ 822 type = "critical"; 823 }; 824 }; 825 826 cooling-maps { 827 map0 { 828 trip = <&target>; 829 cooling-device = 830 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 831 contribution = <4096>; 832 }; 833 map1 { 834 trip = <&target>; 835 cooling-device = 836 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 837 contribution = <1024>; 838 }; 839 map2 { 840 trip = <&target>; 841 cooling-device = 842 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 843 contribution = <4096>; 844 }; 845 }; 846 }; 847 848 gpu_thermal: gpu-thermal { 849 polling-delay-passive = <100>; 850 polling-delay = <1000>; 851 852 thermal-sensors = <&tsadc 1>; 853 }; 854 }; 855 856 tsadc: tsadc@ff260000 { 857 compatible = "rockchip,rk3399-tsadc"; 858 reg = <0x0 0xff260000 0x0 0x100>; 859 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 860 assigned-clocks = <&cru SCLK_TSADC>; 861 assigned-clock-rates = <750000>; 862 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 863 clock-names = "tsadc", "apb_pclk"; 864 resets = <&cru SRST_TSADC>; 865 reset-names = "tsadc-apb"; 866 rockchip,grf = <&grf>; 867 rockchip,hw-tshut-temp = <95000>; 868 pinctrl-names = "gpio", "otpout"; 869 pinctrl-0 = <&otp_pin>; 870 pinctrl-1 = <&otp_out>; 871 #thermal-sensor-cells = <1>; 872 status = "disabled"; 873 }; 874 875 qos_emmc: qos@ffa58000 { 876 compatible = "syscon"; 877 reg = <0x0 0xffa58000 0x0 0x20>; 878 }; 879 880 qos_gmac: qos@ffa5c000 { 881 compatible = "syscon"; 882 reg = <0x0 0xffa5c000 0x0 0x20>; 883 }; 884 885 qos_pcie: qos@ffa60080 { 886 compatible = "syscon"; 887 reg = <0x0 0xffa60080 0x0 0x20>; 888 }; 889 890 qos_usb_host0: qos@ffa60100 { 891 compatible = "syscon"; 892 reg = <0x0 0xffa60100 0x0 0x20>; 893 }; 894 895 qos_usb_host1: qos@ffa60180 { 896 compatible = "syscon"; 897 reg = <0x0 0xffa60180 0x0 0x20>; 898 }; 899 900 qos_usb_otg0: qos@ffa70000 { 901 compatible = "syscon"; 902 reg = <0x0 0xffa70000 0x0 0x20>; 903 }; 904 905 qos_usb_otg1: qos@ffa70080 { 906 compatible = "syscon"; 907 reg = <0x0 0xffa70080 0x0 0x20>; 908 }; 909 910 qos_sd: qos@ffa74000 { 911 compatible = "syscon"; 912 reg = <0x0 0xffa74000 0x0 0x20>; 913 }; 914 915 qos_sdioaudio: qos@ffa76000 { 916 compatible = "syscon"; 917 reg = <0x0 0xffa76000 0x0 0x20>; 918 }; 919 920 qos_hdcp: qos@ffa90000 { 921 compatible = "syscon"; 922 reg = <0x0 0xffa90000 0x0 0x20>; 923 }; 924 925 qos_iep: qos@ffa98000 { 926 compatible = "syscon"; 927 reg = <0x0 0xffa98000 0x0 0x20>; 928 }; 929 930 qos_isp0_m0: qos@ffaa0000 { 931 compatible = "syscon"; 932 reg = <0x0 0xffaa0000 0x0 0x20>; 933 }; 934 935 qos_isp0_m1: qos@ffaa0080 { 936 compatible = "syscon"; 937 reg = <0x0 0xffaa0080 0x0 0x20>; 938 }; 939 940 qos_isp1_m0: qos@ffaa8000 { 941 compatible = "syscon"; 942 reg = <0x0 0xffaa8000 0x0 0x20>; 943 }; 944 945 qos_isp1_m1: qos@ffaa8080 { 946 compatible = "syscon"; 947 reg = <0x0 0xffaa8080 0x0 0x20>; 948 }; 949 950 qos_rga_r: qos@ffab0000 { 951 compatible = "syscon"; 952 reg = <0x0 0xffab0000 0x0 0x20>; 953 }; 954 955 qos_rga_w: qos@ffab0080 { 956 compatible = "syscon"; 957 reg = <0x0 0xffab0080 0x0 0x20>; 958 }; 959 960 qos_video_m0: qos@ffab8000 { 961 compatible = "syscon"; 962 reg = <0x0 0xffab8000 0x0 0x20>; 963 }; 964 965 qos_video_m1_r: qos@ffac0000 { 966 compatible = "syscon"; 967 reg = <0x0 0xffac0000 0x0 0x20>; 968 }; 969 970 qos_video_m1_w: qos@ffac0080 { 971 compatible = "syscon"; 972 reg = <0x0 0xffac0080 0x0 0x20>; 973 }; 974 975 qos_vop_big_r: qos@ffac8000 { 976 compatible = "syscon"; 977 reg = <0x0 0xffac8000 0x0 0x20>; 978 }; 979 980 qos_vop_big_w: qos@ffac8080 { 981 compatible = "syscon"; 982 reg = <0x0 0xffac8080 0x0 0x20>; 983 }; 984 985 qos_vop_little: qos@ffad0000 { 986 compatible = "syscon"; 987 reg = <0x0 0xffad0000 0x0 0x20>; 988 }; 989 990 qos_perihp: qos@ffad8080 { 991 compatible = "syscon"; 992 reg = <0x0 0xffad8080 0x0 0x20>; 993 }; 994 995 qos_gpu: qos@ffae0000 { 996 compatible = "syscon"; 997 reg = <0x0 0xffae0000 0x0 0x20>; 998 }; 999 1000 pmu: power-management@ff310000 { 1001 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 1002 reg = <0x0 0xff310000 0x0 0x1000>; 1003 1004 /* 1005 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 1006 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 1007 * Some of the power domains are grouped together for every 1008 * voltage domain. 1009 * The detail contents as below. 1010 */ 1011 power: power-controller { 1012 compatible = "rockchip,rk3399-power-controller"; 1013 #power-domain-cells = <1>; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 1017 /* These power domains are grouped by VD_CENTER */ 1018 power-domain@RK3399_PD_IEP { 1019 reg = <RK3399_PD_IEP>; 1020 clocks = <&cru ACLK_IEP>, 1021 <&cru HCLK_IEP>; 1022 pm_qos = <&qos_iep>; 1023 }; 1024 power-domain@RK3399_PD_RGA { 1025 reg = <RK3399_PD_RGA>; 1026 clocks = <&cru ACLK_RGA>, 1027 <&cru HCLK_RGA>; 1028 pm_qos = <&qos_rga_r>, 1029 <&qos_rga_w>; 1030 }; 1031 power-domain@RK3399_PD_VCODEC { 1032 reg = <RK3399_PD_VCODEC>; 1033 clocks = <&cru ACLK_VCODEC>, 1034 <&cru HCLK_VCODEC>; 1035 pm_qos = <&qos_video_m0>; 1036 }; 1037 power-domain@RK3399_PD_VDU { 1038 reg = <RK3399_PD_VDU>; 1039 clocks = <&cru ACLK_VDU>, 1040 <&cru HCLK_VDU>; 1041 pm_qos = <&qos_video_m1_r>, 1042 <&qos_video_m1_w>; 1043 }; 1044 1045 /* These power domains are grouped by VD_GPU */ 1046 power-domain@RK3399_PD_GPU { 1047 reg = <RK3399_PD_GPU>; 1048 clocks = <&cru ACLK_GPU>; 1049 pm_qos = <&qos_gpu>; 1050 }; 1051 1052 /* These power domains are grouped by VD_LOGIC */ 1053 power-domain@RK3399_PD_EDP { 1054 reg = <RK3399_PD_EDP>; 1055 clocks = <&cru PCLK_EDP_CTRL>; 1056 }; 1057 power-domain@RK3399_PD_EMMC { 1058 reg = <RK3399_PD_EMMC>; 1059 clocks = <&cru ACLK_EMMC>; 1060 pm_qos = <&qos_emmc>; 1061 }; 1062 power-domain@RK3399_PD_GMAC { 1063 reg = <RK3399_PD_GMAC>; 1064 clocks = <&cru ACLK_GMAC>, 1065 <&cru PCLK_GMAC>; 1066 pm_qos = <&qos_gmac>; 1067 }; 1068 power-domain@RK3399_PD_PERIHP { 1069 reg = <RK3399_PD_PERIHP>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 clocks = <&cru ACLK_PERIHP>; 1073 pm_qos = <&qos_perihp>, 1074 <&qos_pcie>, 1075 <&qos_usb_host0>, 1076 <&qos_usb_host1>; 1077 1078 power-domain@RK3399_PD_SD { 1079 reg = <RK3399_PD_SD>; 1080 clocks = <&cru HCLK_SDMMC>, 1081 <&cru SCLK_SDMMC>; 1082 pm_qos = <&qos_sd>; 1083 }; 1084 }; 1085 power-domain@RK3399_PD_SDIOAUDIO { 1086 reg = <RK3399_PD_SDIOAUDIO>; 1087 clocks = <&cru HCLK_SDIO>; 1088 pm_qos = <&qos_sdioaudio>; 1089 }; 1090 power-domain@RK3399_PD_TCPD0 { 1091 reg = <RK3399_PD_TCPD0>; 1092 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1093 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1094 }; 1095 power-domain@RK3399_PD_TCPD1 { 1096 reg = <RK3399_PD_TCPD1>; 1097 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1098 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1099 }; 1100 power-domain@RK3399_PD_USB3 { 1101 reg = <RK3399_PD_USB3>; 1102 clocks = <&cru ACLK_USB3>; 1103 pm_qos = <&qos_usb_otg0>, 1104 <&qos_usb_otg1>; 1105 }; 1106 power-domain@RK3399_PD_VIO { 1107 reg = <RK3399_PD_VIO>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 1111 power-domain@RK3399_PD_HDCP { 1112 reg = <RK3399_PD_HDCP>; 1113 clocks = <&cru ACLK_HDCP>, 1114 <&cru HCLK_HDCP>, 1115 <&cru PCLK_HDCP>; 1116 pm_qos = <&qos_hdcp>; 1117 }; 1118 power-domain@RK3399_PD_ISP0 { 1119 reg = <RK3399_PD_ISP0>; 1120 clocks = <&cru ACLK_ISP0>, 1121 <&cru HCLK_ISP0>; 1122 pm_qos = <&qos_isp0_m0>, 1123 <&qos_isp0_m1>; 1124 }; 1125 power-domain@RK3399_PD_ISP1 { 1126 reg = <RK3399_PD_ISP1>; 1127 clocks = <&cru ACLK_ISP1>, 1128 <&cru HCLK_ISP1>; 1129 pm_qos = <&qos_isp1_m0>, 1130 <&qos_isp1_m1>; 1131 }; 1132 power-domain@RK3399_PD_VO { 1133 reg = <RK3399_PD_VO>; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 1137 power-domain@RK3399_PD_VOPB { 1138 reg = <RK3399_PD_VOPB>; 1139 clocks = <&cru ACLK_VOP0>, 1140 <&cru HCLK_VOP0>; 1141 pm_qos = <&qos_vop_big_r>, 1142 <&qos_vop_big_w>; 1143 }; 1144 power-domain@RK3399_PD_VOPL { 1145 reg = <RK3399_PD_VOPL>; 1146 clocks = <&cru ACLK_VOP1>, 1147 <&cru HCLK_VOP1>; 1148 pm_qos = <&qos_vop_little>; 1149 }; 1150 }; 1151 }; 1152 }; 1153 }; 1154 1155 pmugrf: syscon@ff320000 { 1156 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1157 reg = <0x0 0xff320000 0x0 0x1000>; 1158 1159 pmu_io_domains: io-domains { 1160 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1161 status = "disabled"; 1162 }; 1163 1164 reboot_mode: reboot-mode { 1165 compatible = "syscon-reboot-mode"; 1166 offset = <0x300>; 1167 mode-charge = <BOOT_CHARGING>; 1168 mode-fastboot = <BOOT_FASTBOOT>; 1169 mode-loader = <BOOT_BL_DOWNLOAD>; 1170 mode-normal = <BOOT_NORMAL>; 1171 mode-panic = <BOOT_PANIC>; 1172 mode-recovery = <BOOT_RECOVERY>; 1173 mode-ums = <BOOT_UMS>; 1174 }; 1175 1176 pmu_pvtm: pmu-pvtm { 1177 compatible = "rockchip,rk3399-pmu-pvtm"; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 status = "disabled"; 1181 1182 pvtm@4 { 1183 reg = <4>; 1184 clocks = <&pmucru SCLK_PVTM_PMU>; 1185 clock-names = "clk"; 1186 resets = <&pmucru SRST_PVTM>; 1187 reset-names = "rst"; 1188 }; 1189 }; 1190 }; 1191 1192 spi3: spi@ff350000 { 1193 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1194 reg = <0x0 0xff350000 0x0 0x1000>; 1195 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1196 clock-names = "spiclk", "apb_pclk"; 1197 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 uart4: serial@ff370000 { 1206 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1207 reg = <0x0 0xff370000 0x0 0x100>; 1208 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1209 clock-names = "baudclk", "apb_pclk"; 1210 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1211 reg-shift = <2>; 1212 reg-io-width = <4>; 1213 pinctrl-names = "default"; 1214 pinctrl-0 = <&uart4_xfer>; 1215 status = "disabled"; 1216 }; 1217 1218 i2c0: i2c@ff3c0000 { 1219 compatible = "rockchip,rk3399-i2c"; 1220 reg = <0x0 0xff3c0000 0x0 0x1000>; 1221 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1222 assigned-clock-rates = <200000000>; 1223 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1224 clock-names = "i2c", "pclk"; 1225 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1226 pinctrl-names = "default"; 1227 pinctrl-0 = <&i2c0_xfer>; 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 status = "disabled"; 1231 }; 1232 1233 i2c4: i2c@ff3d0000 { 1234 compatible = "rockchip,rk3399-i2c"; 1235 reg = <0x0 0xff3d0000 0x0 0x1000>; 1236 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1237 assigned-clock-rates = <200000000>; 1238 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1239 clock-names = "i2c", "pclk"; 1240 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1241 pinctrl-names = "default"; 1242 pinctrl-0 = <&i2c4_xfer>; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 status = "disabled"; 1246 }; 1247 1248 i2c8: i2c@ff3e0000 { 1249 compatible = "rockchip,rk3399-i2c"; 1250 reg = <0x0 0xff3e0000 0x0 0x1000>; 1251 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1252 assigned-clock-rates = <200000000>; 1253 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1254 clock-names = "i2c", "pclk"; 1255 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&i2c8_xfer>; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 1263 pwm0: pwm@ff420000 { 1264 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1265 reg = <0x0 0xff420000 0x0 0x10>; 1266 #pwm-cells = <3>; 1267 pinctrl-names = "active"; 1268 pinctrl-0 = <&pwm0_pin>; 1269 clocks = <&pmucru PCLK_RKPWM_PMU>; 1270 clock-names = "pwm"; 1271 status = "disabled"; 1272 }; 1273 1274 pwm1: pwm@ff420010 { 1275 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1276 reg = <0x0 0xff420010 0x0 0x10>; 1277 #pwm-cells = <3>; 1278 pinctrl-names = "active"; 1279 pinctrl-0 = <&pwm1_pin>; 1280 clocks = <&pmucru PCLK_RKPWM_PMU>; 1281 clock-names = "pwm"; 1282 status = "disabled"; 1283 }; 1284 1285 pwm2: pwm@ff420020 { 1286 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1287 reg = <0x0 0xff420020 0x0 0x10>; 1288 #pwm-cells = <3>; 1289 pinctrl-names = "active"; 1290 pinctrl-0 = <&pwm2_pin>; 1291 clocks = <&pmucru PCLK_RKPWM_PMU>; 1292 clock-names = "pwm"; 1293 status = "disabled"; 1294 }; 1295 1296 pwm3: pwm@ff420030 { 1297 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1298 reg = <0x0 0xff420030 0x0 0x10>; 1299 #pwm-cells = <3>; 1300 pinctrl-names = "active"; 1301 pinctrl-0 = <&pwm3a_pin>; 1302 clocks = <&pmucru PCLK_RKPWM_PMU>; 1303 clock-names = "pwm"; 1304 status = "disabled"; 1305 }; 1306 1307 dfi: dfi@ff630000 { 1308 reg = <0x00 0xff630000 0x00 0x4000>; 1309 compatible = "rockchip,rk3399-dfi"; 1310 rockchip,pmu = <&pmugrf>; 1311 clocks = <&cru PCLK_DDR_MON>; 1312 clock-names = "pclk_ddr_mon"; 1313 status = "disabled"; 1314 }; 1315 1316 dmc: dmc { 1317 compatible = "rockchip,rk3399-dmc"; 1318 devfreq-events = <&dfi>; 1319 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; 1320 clocks = <&cru SCLK_DDRC>; 1321 clock-names = "dmc_clk"; 1322 ddr_timing = <&ddr_timing>; 1323 status = "disabled"; 1324 }; 1325 1326 mpp_srv: mpp-srv { 1327 compatible = "rockchip,mpp-service"; 1328 rockchip,taskqueue-count = <2>; 1329 rockchip,resetgroup-count = <2>; 1330 status = "disabled"; 1331 }; 1332 1333 vpu: video-codec@ff650000 { 1334 compatible = "rockchip,rk3399-vpu"; 1335 reg = <0x0 0xff650000 0x0 0x800>; 1336 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1337 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1338 interrupt-names = "vepu", "vdpu"; 1339 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1340 clock-names = "aclk", "hclk"; 1341 iommus = <&vpu_mmu>; 1342 power-domains = <&power RK3399_PD_VCODEC>; 1343 status = "disabled"; 1344 }; 1345 1346 vepu: vepu@ff650000 { 1347 compatible = "rockchip,vpu-encoder-v2"; 1348 reg = <0x0 0xff650000 0x0 0x400>; 1349 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 1350 interrupt-names = "irq_enc"; 1351 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1352 clock-names = "aclk_vcodec", "hclk_vcodec"; 1353 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>; 1354 reset-names = "shared_video_h", "shared_video_a"; 1355 iommus = <&vpu_mmu>; 1356 rockchip,srv = <&mpp_srv>; 1357 rockchip,taskqueue-node = <0>; 1358 rockchip,resetgroup-node = <0>; 1359 power-domains = <&power RK3399_PD_VCODEC>; 1360 status = "disabled"; 1361 }; 1362 1363 vdpu: vdpu@ff650400 { 1364 compatible = "rockchip,vpu-decoder-v2"; 1365 reg = <0x0 0xff650400 0x0 0x400>; 1366 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1367 interrupt-names = "irq_dec"; 1368 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1369 clock-names = "aclk_vcodec", "hclk_vcodec"; 1370 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>; 1371 reset-names = "shared_video_h", "shared_video_a"; 1372 iommus = <&vpu_mmu>; 1373 power-domains = <&power RK3399_PD_VCODEC>; 1374 rockchip,srv = <&mpp_srv>; 1375 rockchip,taskqueue-node = <0>; 1376 rockchip,resetgroup-node = <0>; 1377 status = "disabled"; 1378 }; 1379 1380 vpu_mmu: iommu@ff650800 { 1381 compatible = "rockchip,iommu"; 1382 reg = <0x0 0xff650800 0x0 0x40>; 1383 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1384 interrupt-names = "vpu_mmu"; 1385 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1386 clock-names = "aclk", "iface"; 1387 #iommu-cells = <0>; 1388 power-domains = <&power RK3399_PD_VCODEC>; 1389 status = "disabled"; 1390 }; 1391 1392 vdec: video-codec@ff660000 { 1393 compatible = "rockchip,rk3399-vdec"; 1394 reg = <0x0 0xff660000 0x0 0x400>; 1395 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1396 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1397 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1398 clock-names = "axi", "ahb", "cabac", "core"; 1399 iommus = <&vdec_mmu>; 1400 power-domains = <&power RK3399_PD_VDU>; 1401 status = "disabled"; 1402 }; 1403 1404 rkvdec: rkvdec@ff660000 { 1405 compatible = "rockchip,rkv-decoder-rk3399"; 1406 reg = <0x0 0xff660000 0x0 0x400>; 1407 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1408 interrupt-names = "irq_dec"; 1409 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1410 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1411 clock-names = "aclk_vcodec", "hclk_vcodec", 1412 "clk_cabac", "clk_core"; 1413 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, 1414 <&cru SRST_H_VDU_NOC>, <&cru SRST_A_VDU_NOC>, 1415 <&cru SRST_VDU_CA>, <&cru SRST_VDU_CORE>; 1416 reset-names = "video_h", "video_a", "niu_h", "niu_a", 1417 "video_cabac", "video_core"; 1418 iommus = <&vdec_mmu>; 1419 rockchip,srv = <&mpp_srv>; 1420 rockchip,taskqueue-node = <1>; 1421 rockchip,resetgroup-node = <1>; 1422 power-domains = <&power RK3399_PD_VDU>; 1423 status = "disabled"; 1424 }; 1425 1426 vdec_mmu: iommu@ff660480 { 1427 compatible = "rockchip,iommu"; 1428 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1429 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1430 interrupt-names = "vdec_mmu"; 1431 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1432 clock-names = "aclk", "iface"; 1433 power-domains = <&power RK3399_PD_VDU>; 1434 #iommu-cells = <0>; 1435 status = "disabled"; 1436 }; 1437 1438 iep: iep@ff670000 { 1439 compatible = "rockchip,iep"; 1440 iommu_enabled = <1>; 1441 iommus = <&iep_mmu>; 1442 reg = <0x0 0xff670000 0x0 0x800>; 1443 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1444 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1445 clock-names = "aclk_iep", "hclk_iep"; 1446 power-domains = <&power RK3399_PD_IEP>; 1447 allocator = <1>; 1448 version = <2>; 1449 status = "disabled"; 1450 }; 1451 1452 iep_mmu: iommu@ff670800 { 1453 compatible = "rockchip,iommu"; 1454 reg = <0x0 0xff670800 0x0 0x40>; 1455 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1456 interrupt-names = "iep_mmu"; 1457 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1458 clock-names = "aclk", "iface"; 1459 power-domains = <&power RK3399_PD_IEP>; 1460 #iommu-cells = <0>; 1461 status = "disabled"; 1462 }; 1463 1464 rga: rga@ff680000 { 1465 compatible = "rockchip,rk3399-rga"; 1466 reg = <0x0 0xff680000 0x0 0x10000>; 1467 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1468 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1469 clock-names = "aclk", "hclk", "sclk"; 1470 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1471 reset-names = "core", "axi", "ahb"; 1472 power-domains = <&power RK3399_PD_RGA>; 1473 }; 1474 1475 efuse0: efuse@ff690000 { 1476 compatible = "rockchip,rk3399-efuse"; 1477 reg = <0x0 0xff690000 0x0 0x80>; 1478 #address-cells = <1>; 1479 #size-cells = <1>; 1480 clocks = <&cru PCLK_EFUSE1024NS>; 1481 clock-names = "pclk_efuse"; 1482 1483 /* Data cells */ 1484 specification_serial_number: specification-serial-number@6 { 1485 reg = <0x06 0x1>; 1486 bits = <0 5>; 1487 }; 1488 cpu_id: cpu-id@7 { 1489 reg = <0x07 0x10>; 1490 }; 1491 cpub_leakage: cpu-leakage@17 { 1492 reg = <0x17 0x1>; 1493 }; 1494 gpu_leakage: gpu-leakage@18 { 1495 reg = <0x18 0x1>; 1496 }; 1497 center_leakage: center-leakage@19 { 1498 reg = <0x19 0x1>; 1499 }; 1500 cpul_leakage: cpu-leakage@1a { 1501 reg = <0x1a 0x1>; 1502 }; 1503 logic_leakage: logic-leakage@1b { 1504 reg = <0x1b 0x1>; 1505 }; 1506 wafer_info: wafer-info@1c { 1507 reg = <0x1c 0x1>; 1508 }; 1509 customer_demand: customer-demand@22 { 1510 reg = <0x22 0x1>; 1511 bits = <4 4>; 1512 }; 1513 }; 1514 1515 pmucru: pmu-clock-controller@ff750000 { 1516 compatible = "rockchip,rk3399-pmucru"; 1517 reg = <0x0 0xff750000 0x0 0x1000>; 1518 rockchip,grf = <&pmugrf>; 1519 #clock-cells = <1>; 1520 #reset-cells = <1>; 1521 assigned-clocks = <&pmucru PLL_PPLL>; 1522 assigned-clock-rates = <676000000>; 1523 }; 1524 1525 cru: clock-controller@ff760000 { 1526 compatible = "rockchip,rk3399-cru"; 1527 reg = <0x0 0xff760000 0x0 0x1000>; 1528 rockchip,grf = <&grf>; 1529 #clock-cells = <1>; 1530 #reset-cells = <1>; 1531 assigned-clocks = 1532 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1533 <&cru PLL_NPLL>, 1534 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1535 <&cru PCLK_PERIHP>, 1536 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1537 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1538 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1539 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1540 <&cru ACLK_GIC_PRE>, 1541 <&cru PCLK_DDR>; 1542 assigned-clock-rates = 1543 <594000000>, <800000000>, 1544 <1000000000>, 1545 <150000000>, <75000000>, 1546 <37500000>, 1547 <100000000>, <100000000>, 1548 <50000000>, <600000000>, 1549 <100000000>, <50000000>, 1550 <400000000>, <400000000>, 1551 <200000000>, 1552 <200000000>; 1553 }; 1554 1555 grf: syscon@ff770000 { 1556 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1557 reg = <0x0 0xff770000 0x0 0x10000>; 1558 #address-cells = <1>; 1559 #size-cells = <1>; 1560 1561 io_domains: io-domains { 1562 compatible = "rockchip,rk3399-io-voltage-domain"; 1563 status = "disabled"; 1564 }; 1565 1566 mipi_dphy_rx0: mipi-dphy-rx0 { 1567 compatible = "rockchip,rk3399-mipi-dphy"; 1568 clocks = <&cru SCLK_MIPIDPHY_REF>, 1569 <&cru SCLK_DPHY_RX0_CFG>, 1570 <&cru PCLK_VIO_GRF>; 1571 clock-names = "dphy-ref", "dphy-cfg", "grf"; 1572 power-domains = <&power RK3399_PD_VIO>; 1573 #phy-cells = <0>; 1574 status = "disabled"; 1575 }; 1576 1577 u2phy0: usb2-phy@e450 { 1578 compatible = "rockchip,rk3399-usb2phy"; 1579 reg = <0xe450 0x10>; 1580 clocks = <&cru SCLK_USB2PHY0_REF>; 1581 clock-names = "phyclk"; 1582 #clock-cells = <0>; 1583 clock-output-names = "clk_usbphy0_480m"; 1584 status = "disabled"; 1585 1586 u2phy0_host: host-port { 1587 #phy-cells = <0>; 1588 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1589 interrupt-names = "linestate"; 1590 status = "disabled"; 1591 }; 1592 1593 u2phy0_otg: otg-port { 1594 #phy-cells = <0>; 1595 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1596 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1597 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1598 interrupt-names = "otg-bvalid", "otg-id", 1599 "linestate"; 1600 status = "disabled"; 1601 }; 1602 }; 1603 1604 u2phy1: usb2-phy@e460 { 1605 compatible = "rockchip,rk3399-usb2phy"; 1606 reg = <0xe460 0x10>; 1607 clocks = <&cru SCLK_USB2PHY1_REF>; 1608 clock-names = "phyclk"; 1609 #clock-cells = <0>; 1610 clock-output-names = "clk_usbphy1_480m"; 1611 status = "disabled"; 1612 1613 u2phy1_host: host-port { 1614 #phy-cells = <0>; 1615 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1616 interrupt-names = "linestate"; 1617 status = "disabled"; 1618 }; 1619 1620 u2phy1_otg: otg-port { 1621 #phy-cells = <0>; 1622 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1623 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1624 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1625 interrupt-names = "otg-bvalid", "otg-id", 1626 "linestate"; 1627 status = "disabled"; 1628 }; 1629 }; 1630 1631 emmc_phy: phy@f780 { 1632 compatible = "rockchip,rk3399-emmc-phy"; 1633 reg = <0xf780 0x24>; 1634 clocks = <&sdhci>; 1635 clock-names = "emmcclk"; 1636 drive-impedance-ohm = <50>; 1637 #phy-cells = <0>; 1638 status = "disabled"; 1639 }; 1640 1641 pcie_phy: pcie-phy { 1642 compatible = "rockchip,rk3399-pcie-phy"; 1643 clocks = <&cru SCLK_PCIEPHY_REF>; 1644 clock-names = "refclk"; 1645 #phy-cells = <1>; 1646 resets = <&cru SRST_PCIEPHY>; 1647 reset-names = "phy"; 1648 status = "disabled"; 1649 }; 1650 1651 pvtm: pvtm { 1652 compatible = "rockchip,rk3399-pvtm"; 1653 #address-cells = <1>; 1654 #size-cells = <0>; 1655 status = "disabled"; 1656 1657 pvtm@0 { 1658 reg = <0>; 1659 clocks = <&cru SCLK_PVTM_CORE_L>; 1660 clock-names = "clk"; 1661 resets = <&cru SRST_PVTM_CORE_L>; 1662 reset-names = "rst"; 1663 }; 1664 pvtm@1 { 1665 reg = <1>; 1666 clocks = <&cru SCLK_PVTM_CORE_B>; 1667 clock-names = "clk"; 1668 resets = <&cru SRST_PVTM_CORE_B>; 1669 reset-names = "rst"; 1670 }; 1671 pvtm@2 { 1672 reg = <2>; 1673 clocks = <&cru SCLK_PVTM_DDR>; 1674 clock-names = "clk"; 1675 resets = <&cru SRST_PVTM_DDR>; 1676 reset-names = "rst"; 1677 }; 1678 pvtm@3 { 1679 reg = <3>; 1680 clocks = <&cru SCLK_PVTM_GPU>; 1681 clock-names = "clk"; 1682 resets = <&cru SRST_PVTM_GPU>; 1683 reset-names = "rst"; 1684 }; 1685 }; 1686 }; 1687 1688 tcphy0: phy@ff7c0000 { 1689 compatible = "rockchip,rk3399-typec-phy"; 1690 reg = <0x0 0xff7c0000 0x0 0x40000>; 1691 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1692 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1693 clock-names = "tcpdcore", "tcpdphy-ref"; 1694 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1695 assigned-clock-rates = <50000000>; 1696 power-domains = <&power RK3399_PD_TCPD0>; 1697 resets = <&cru SRST_UPHY0>, 1698 <&cru SRST_UPHY0_PIPE_L00>, 1699 <&cru SRST_P_UPHY0_TCPHY>; 1700 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1701 rockchip,grf = <&grf>; 1702 status = "disabled"; 1703 1704 tcphy0_dp: dp-port { 1705 #phy-cells = <0>; 1706 }; 1707 1708 tcphy0_usb3: usb3-port { 1709 #phy-cells = <0>; 1710 }; 1711 }; 1712 1713 tcphy1: phy@ff800000 { 1714 compatible = "rockchip,rk3399-typec-phy"; 1715 reg = <0x0 0xff800000 0x0 0x40000>; 1716 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1717 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1718 clock-names = "tcpdcore", "tcpdphy-ref"; 1719 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1720 assigned-clock-rates = <50000000>; 1721 power-domains = <&power RK3399_PD_TCPD1>; 1722 resets = <&cru SRST_UPHY1>, 1723 <&cru SRST_UPHY1_PIPE_L00>, 1724 <&cru SRST_P_UPHY1_TCPHY>; 1725 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1726 rockchip,grf = <&grf>; 1727 status = "disabled"; 1728 1729 tcphy1_dp: dp-port { 1730 #phy-cells = <0>; 1731 }; 1732 1733 tcphy1_usb3: usb3-port { 1734 #phy-cells = <0>; 1735 }; 1736 }; 1737 1738 watchdog@ff848000 { 1739 compatible = "snps,dw-wdt"; 1740 reg = <0x0 0xff848000 0x0 0x100>; 1741 clocks = <&cru PCLK_WDT>; 1742 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1743 }; 1744 1745 rktimer: rktimer@ff850000 { 1746 compatible = "rockchip,rk3399-timer"; 1747 reg = <0x0 0xff850000 0x0 0x1000>; 1748 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1749 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1750 clock-names = "pclk", "timer"; 1751 }; 1752 1753 spdif: spdif@ff870000 { 1754 compatible = "rockchip,rk3399-spdif"; 1755 reg = <0x0 0xff870000 0x0 0x1000>; 1756 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1757 dmas = <&dmac_bus 7>; 1758 dma-names = "tx"; 1759 clock-names = "mclk", "hclk"; 1760 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1761 pinctrl-names = "default"; 1762 pinctrl-0 = <&spdif_bus>; 1763 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1764 #sound-dai-cells = <0>; 1765 status = "disabled"; 1766 }; 1767 1768 i2s0: i2s@ff880000 { 1769 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1770 reg = <0x0 0xff880000 0x0 0x1000>; 1771 rockchip,grf = <&grf>; 1772 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1773 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1774 dma-names = "tx", "rx"; 1775 clock-names = "i2s_clk", "i2s_hclk"; 1776 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1777 resets = <&cru SRST_I2S0_8CH>, <&cru SRST_H_I2S0_8CH>; 1778 reset-names = "reset-m", "reset-h"; 1779 pinctrl-names = "default"; 1780 pinctrl-0 = <&i2s0_8ch_bus>; 1781 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1782 #sound-dai-cells = <0>; 1783 status = "disabled"; 1784 }; 1785 1786 i2s1: i2s@ff890000 { 1787 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1788 reg = <0x0 0xff890000 0x0 0x1000>; 1789 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1790 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1791 dma-names = "tx", "rx"; 1792 clock-names = "i2s_clk", "i2s_hclk"; 1793 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1794 resets = <&cru SRST_I2S1_8CH>, <&cru SRST_H_I2S1_8CH>; 1795 reset-names = "reset-m", "reset-h"; 1796 pinctrl-names = "default"; 1797 pinctrl-0 = <&i2s1_2ch_bus>; 1798 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1799 #sound-dai-cells = <0>; 1800 status = "disabled"; 1801 }; 1802 1803 i2s2: i2s@ff8a0000 { 1804 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1805 reg = <0x0 0xff8a0000 0x0 0x1000>; 1806 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1807 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1808 dma-names = "tx", "rx"; 1809 clock-names = "i2s_clk", "i2s_hclk"; 1810 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1811 resets = <&cru SRST_I2S2_8CH>, <&cru SRST_H_I2S2_8CH>; 1812 reset-names = "reset-m", "reset-h"; 1813 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1814 #sound-dai-cells = <0>; 1815 status = "disabled"; 1816 }; 1817 1818 rng: rng@ff8b8000 { 1819 compatible = "rockchip,cryptov1-rng"; 1820 reg = <0x0 0xff8b8000 0x0 0x1000>; 1821 clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; 1822 clock-names = "clk_crypto", "hclk_crypto"; 1823 assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; 1824 assigned-clock-rates = <150000000>, <100000000>; 1825 status = "disabled"; 1826 }; 1827 1828 vopl: vop@ff8f0000 { 1829 compatible = "rockchip,rk3399-vop-lit"; 1830 reg = <0x0 0xff8f0000 0x0 0x600>, 1831 <0x0 0xff8f1c00 0x0 0x200>, 1832 <0x0 0xff8f2000 0x0 0x400>; 1833 reg-names = "regs", "cabc_lut", "gamma_lut"; 1834 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1835 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>, <&cru DCLK_VOP1_DIV>; 1836 clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source"; 1837 iommus = <&vopl_mmu>; 1838 power-domains = <&power RK3399_PD_VOPL>; 1839 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1840 reset-names = "axi", "ahb", "dclk"; 1841 status = "disabled"; 1842 1843 vopl_out: port { 1844 #address-cells = <1>; 1845 #size-cells = <0>; 1846 1847 vopl_out_dsi: endpoint@0 { 1848 reg = <0>; 1849 remote-endpoint = <&dsi_in_vopl>; 1850 }; 1851 1852 vopl_out_edp: endpoint@1 { 1853 reg = <1>; 1854 remote-endpoint = <&edp_in_vopl>; 1855 }; 1856 1857 vopl_out_hdmi: endpoint@2 { 1858 reg = <2>; 1859 remote-endpoint = <&hdmi_in_vopl>; 1860 }; 1861 1862 vopl_out_dsi1: endpoint@3 { 1863 reg = <3>; 1864 remote-endpoint = <&dsi1_in_vopl>; 1865 }; 1866 1867 vopl_out_dp: endpoint@4 { 1868 reg = <4>; 1869 remote-endpoint = <&dp_in_vopl>; 1870 }; 1871 }; 1872 }; 1873 1874 vop1_pwm: voppwm@ff8f01a0 { 1875 compatible = "rockchip,vop-pwm"; 1876 reg = <0x0 0xff8f01a0 0x0 0x10>; 1877 #pwm-cells = <3>; 1878 pinctrl-names = "active"; 1879 pinctrl-0 = <&vop1_pwm_pin>; 1880 clocks = <&cru SCLK_VOP1_PWM>; 1881 clock-names = "pwm"; 1882 status = "disabled"; 1883 }; 1884 1885 vopl_mmu: iommu@ff8f3f00 { 1886 compatible = "rockchip,iommu"; 1887 reg = <0x0 0xff8f3f00 0x0 0x100>; 1888 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1889 interrupt-names = "vopl_mmu"; 1890 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1891 clock-names = "aclk", "iface"; 1892 power-domains = <&power RK3399_PD_VOPL>; 1893 #iommu-cells = <0>; 1894 rockchip,disable-device-link-resume; 1895 status = "disabled"; 1896 }; 1897 1898 vopb: vop@ff900000 { 1899 compatible = "rockchip,rk3399-vop-big"; 1900 reg = <0x0 0xff900000 0x0 0x600>, 1901 <0x0 0xff901c00 0x0 0x200>, 1902 <0x0 0xff902000 0x0 0x1000>; 1903 reg-names = "regs", "cabc_lut", "gamma_lut"; 1904 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1905 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>, <&cru DCLK_VOP0_DIV>; 1906 clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source"; 1907 iommus = <&vopb_mmu>; 1908 power-domains = <&power RK3399_PD_VOPB>; 1909 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1910 reset-names = "axi", "ahb", "dclk"; 1911 status = "disabled"; 1912 1913 vopb_out: port { 1914 #address-cells = <1>; 1915 #size-cells = <0>; 1916 1917 vopb_out_edp: endpoint@0 { 1918 reg = <0>; 1919 remote-endpoint = <&edp_in_vopb>; 1920 }; 1921 1922 vopb_out_dsi: endpoint@1 { 1923 reg = <1>; 1924 remote-endpoint = <&dsi_in_vopb>; 1925 }; 1926 1927 vopb_out_hdmi: endpoint@2 { 1928 reg = <2>; 1929 remote-endpoint = <&hdmi_in_vopb>; 1930 }; 1931 1932 vopb_out_dsi1: endpoint@3 { 1933 reg = <3>; 1934 remote-endpoint = <&dsi1_in_vopb>; 1935 }; 1936 1937 vopb_out_dp: endpoint@4 { 1938 reg = <4>; 1939 remote-endpoint = <&dp_in_vopb>; 1940 }; 1941 }; 1942 }; 1943 1944 vop0_pwm: voppwm@ff9001a0 { 1945 compatible = "rockchip,vop-pwm"; 1946 reg = <0x0 0xff9001a0 0x0 0x10>; 1947 #pwm-cells = <3>; 1948 pinctrl-names = "active"; 1949 pinctrl-0 = <&vop0_pwm_pin>; 1950 clocks = <&cru SCLK_VOP0_PWM>; 1951 clock-names = "pwm"; 1952 status = "disabled"; 1953 }; 1954 1955 vopb_mmu: iommu@ff903f00 { 1956 compatible = "rockchip,iommu"; 1957 reg = <0x0 0xff903f00 0x0 0x100>; 1958 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1959 interrupt-names = "vopb_mmu"; 1960 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1961 clock-names = "aclk", "iface"; 1962 power-domains = <&power RK3399_PD_VOPB>; 1963 #iommu-cells = <0>; 1964 rockchip,disable-device-link-resume; 1965 status = "disabled"; 1966 }; 1967 1968 rkisp1_0: rkisp1@ff910000 { 1969 compatible = "rockchip,rk3399-rkisp1"; 1970 reg = <0x0 0xff910000 0x0 0x4000>; 1971 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1972 interrupt-names = "isp_irq"; 1973 clocks = <&cru SCLK_ISP0>, 1974 <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, 1975 <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1976 clock-names = "clk_isp", 1977 "aclk_isp", "hclk_isp", 1978 "aclk_isp_wrap", "hclk_isp_wrap"; 1979 devfreq = <&dmc>; 1980 power-domains = <&power RK3399_PD_ISP0>; 1981 iommus = <&isp0_mmu>; 1982 status = "disabled"; 1983 }; 1984 1985 isp0_mmu: iommu@ff914000 { 1986 compatible = "rockchip,iommu"; 1987 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1988 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1989 interrupt-names = "isp0_mmu"; 1990 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1991 clock-names = "aclk", "iface"; 1992 #iommu-cells = <0>; 1993 power-domains = <&power RK3399_PD_ISP0>; 1994 rockchip,disable-mmu-reset; 1995 status = "disabled"; 1996 }; 1997 1998 rkisp1_1: rkisp1@ff920000 { 1999 compatible = "rockchip,rk3399-rkisp1"; 2000 reg = <0x0 0xff920000 0x0 0x4000>; 2001 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 2002 interrupt-names = "isp_irq"; 2003 clocks = <&cru SCLK_ISP1>, 2004 <&cru ACLK_ISP1>, <&cru HCLK_ISP1>, 2005 <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>, 2006 <&cru PCLK_ISP1_WRAPPER>; 2007 clock-names = "clk_isp", 2008 "aclk_isp", "hclk_isp", 2009 "aclk_isp_wrap", "hclk_isp_wrap", 2010 "pclk_isp_wrap"; 2011 devfreq = <&dmc>; 2012 power-domains = <&power RK3399_PD_ISP1>; 2013 iommus = <&isp1_mmu>; 2014 status = "disabled"; 2015 }; 2016 2017 isp1_mmu: iommu@ff924000 { 2018 compatible = "rockchip,iommu"; 2019 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 2020 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 2021 interrupt-names = "isp1_mmu"; 2022 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 2023 clock-names = "aclk", "iface"; 2024 #iommu-cells = <0>; 2025 power-domains = <&power RK3399_PD_ISP1>; 2026 rockchip,disable-mmu-reset; 2027 status = "disabled"; 2028 }; 2029 2030 hdmi_sound: hdmi-sound { 2031 compatible = "simple-audio-card"; 2032 simple-audio-card,format = "i2s"; 2033 simple-audio-card,mclk-fs = <256>; 2034 simple-audio-card,name = "hdmi-sound"; 2035 status = "disabled"; 2036 2037 simple-audio-card,cpu { 2038 sound-dai = <&i2s2>; 2039 }; 2040 simple-audio-card,codec { 2041 sound-dai = <&hdmi>; 2042 }; 2043 }; 2044 2045 hdmi: hdmi@ff940000 { 2046 compatible = "rockchip,rk3399-dw-hdmi"; 2047 reg = <0x0 0xff940000 0x0 0x20000>; 2048 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 2049 clocks = <&cru PCLK_HDMI_CTRL>, 2050 <&cru SCLK_HDMI_SFR>, 2051 <&cru SCLK_HDMI_CEC>, 2052 <&cru PCLK_VIO_GRF>, 2053 <&cru PLL_VPLL>; 2054 clock-names = "iahb", "isfr", "cec", "grf", "vpll"; 2055 power-domains = <&power RK3399_PD_HDCP>; 2056 reg-io-width = <4>; 2057 rockchip,grf = <&grf>; 2058 #sound-dai-cells = <0>; 2059 pinctrl-names = "default"; 2060 pinctrl-0 = <&hdmi_i2c_xfer>; 2061 status = "disabled"; 2062 2063 ports { 2064 hdmi_in: port { 2065 #address-cells = <1>; 2066 #size-cells = <0>; 2067 2068 hdmi_in_vopb: endpoint@0 { 2069 reg = <0>; 2070 remote-endpoint = <&vopb_out_hdmi>; 2071 }; 2072 hdmi_in_vopl: endpoint@1 { 2073 reg = <1>; 2074 remote-endpoint = <&vopl_out_hdmi>; 2075 }; 2076 }; 2077 }; 2078 }; 2079 2080 dsi: mipi_dsi: dsi@ff960000 { 2081 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 2082 reg = <0x0 0xff960000 0x0 0x8000>; 2083 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 2084 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 2085 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 2086 clock-names = "ref", "pclk", "phy_cfg", "grf"; 2087 power-domains = <&power RK3399_PD_VIO>; 2088 resets = <&cru SRST_P_MIPI_DSI0>; 2089 reset-names = "apb"; 2090 rockchip,grf = <&grf>; 2091 #address-cells = <1>; 2092 #size-cells = <0>; 2093 status = "disabled"; 2094 2095 ports { 2096 #address-cells = <1>; 2097 #size-cells = <0>; 2098 2099 port@0 { 2100 reg = <0>; 2101 #address-cells = <1>; 2102 #size-cells = <0>; 2103 2104 dsi_in_vopb: endpoint@0 { 2105 reg = <0>; 2106 remote-endpoint = <&vopb_out_dsi>; 2107 }; 2108 dsi_in_vopl: endpoint@1 { 2109 reg = <1>; 2110 remote-endpoint = <&vopl_out_dsi>; 2111 }; 2112 }; 2113 }; 2114 }; 2115 2116 dsi1: mipi_dsi1: dsi@ff968000 { 2117 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 2118 reg = <0x0 0xff968000 0x0 0x8000>; 2119 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 2120 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 2121 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 2122 clock-names = "ref", "pclk", "phy_cfg", "grf"; 2123 power-domains = <&power RK3399_PD_VIO>; 2124 resets = <&cru SRST_P_MIPI_DSI1>; 2125 reset-names = "apb"; 2126 rockchip,grf = <&grf>; 2127 #address-cells = <1>; 2128 #size-cells = <0>; 2129 status = "disabled"; 2130 2131 ports { 2132 #address-cells = <1>; 2133 #size-cells = <0>; 2134 2135 port@0 { 2136 reg = <0>; 2137 #address-cells = <1>; 2138 #size-cells = <0>; 2139 2140 dsi1_in_vopb: endpoint@0 { 2141 reg = <0>; 2142 remote-endpoint = <&vopb_out_dsi1>; 2143 }; 2144 2145 dsi1_in_vopl: endpoint@1 { 2146 reg = <1>; 2147 remote-endpoint = <&vopl_out_dsi1>; 2148 }; 2149 }; 2150 }; 2151 }; 2152 2153 mipi_dphy_tx1rx1: mipi-dphy-tx1rx1@ff968000 { 2154 compatible = "rockchip,rk3399-mipi-dphy"; 2155 reg = <0x0 0xff968000 0x0 0x8000>; 2156 clocks = <&cru SCLK_MIPIDPHY_REF>, 2157 <&cru SCLK_DPHY_TX1RX1_CFG>, 2158 <&cru PCLK_VIO_GRF>, 2159 <&cru PCLK_MIPI_DSI1>; 2160 clock-names = "dphy-ref", "dphy-cfg", 2161 "grf", "pclk_mipi_dsi"; 2162 rockchip,grf = <&grf>; 2163 power-domains = <&power RK3399_PD_VIO>; 2164 status = "disabled"; 2165 }; 2166 2167 edp: edp@ff970000 { 2168 compatible = "rockchip,rk3399-edp"; 2169 reg = <0x0 0xff970000 0x0 0x8000>; 2170 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 2171 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 2172 clock-names = "dp", "pclk", "grf"; 2173 pinctrl-names = "default"; 2174 pinctrl-0 = <&edp_hpd>; 2175 power-domains = <&power RK3399_PD_EDP>; 2176 resets = <&cru SRST_P_EDP_CTRL>; 2177 reset-names = "dp"; 2178 rockchip,grf = <&grf>; 2179 status = "disabled"; 2180 2181 ports { 2182 #address-cells = <1>; 2183 #size-cells = <0>; 2184 edp_in: port@0 { 2185 reg = <0>; 2186 #address-cells = <1>; 2187 #size-cells = <0>; 2188 2189 edp_in_vopb: endpoint@0 { 2190 reg = <0>; 2191 remote-endpoint = <&vopb_out_edp>; 2192 }; 2193 2194 edp_in_vopl: endpoint@1 { 2195 reg = <1>; 2196 remote-endpoint = <&vopl_out_edp>; 2197 }; 2198 }; 2199 }; 2200 }; 2201 2202 gpu: gpu@ff9a0000 { 2203 compatible = "arm,malit860", 2204 "arm,malit86x", 2205 "arm,malit8xx", 2206 "arm,mali-midgard"; 2207 reg = <0x0 0xff9a0000 0x0 0x10000>; 2208 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 2209 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 2210 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 2211 interrupt-names = "job", "mmu", "gpu"; 2212 clocks = <&cru ACLK_GPU>; 2213 clock-names = "clk_mali"; 2214 #cooling-cells = <2>; 2215 power-domains = <&power RK3399_PD_GPU>; 2216 power-off-delay-ms = <200>; 2217 upthreshold = <40>; 2218 downdifferential = <10>; 2219 status = "disabled"; 2220 2221 gpu_power_model: power_model { 2222 compatible = "arm,mali-simple-power-model"; 2223 static-coefficient = <411000>; 2224 dynamic-coefficient = <733>; 2225 ts = <32000 4700 (-80) 2>; 2226 thermal-zone = "gpu-thermal"; 2227 }; 2228 }; 2229 2230 nocp_cci_msch0: nocp-cci-msch0@ffa86000 { 2231 compatible = "rockchip,rk3399-nocp"; 2232 reg = <0x0 0xffa86000 0x0 0x400>; 2233 }; 2234 2235 nocp_gpu_msch0: nocp-gpu-msch0@ffa86400 { 2236 compatible = "rockchip,rk3399-nocp"; 2237 reg = <0x0 0xffa86400 0x0 0x400>; 2238 }; 2239 2240 nocp_hp_msch0: nocp-hp-msch0@ffa86800 { 2241 compatible = "rockchip,rk3399-nocp"; 2242 reg = <0x0 0xffa86800 0x0 0x400>; 2243 }; 2244 2245 nocp_lp_msch0: nocp-lp-msch0@ffa86c00 { 2246 compatible = "rockchip,rk3399-nocp"; 2247 reg = <0x0 0xffa86c00 0x0 0x400>; 2248 }; 2249 2250 nocp_video_msch0: nocp-video-msch0@ffa87000 { 2251 compatible = "rockchip,rk3399-nocp"; 2252 reg = <0x0 0xffa87000 0x0 0x400>; 2253 }; 2254 2255 nocp_vio0_msch0: nocp-vio0-msch0@ffa87400 { 2256 compatible = "rockchip,rk3399-nocp"; 2257 reg = <0x0 0xffa87400 0x0 0x400>; 2258 }; 2259 2260 nocp_vio1_msch0: nocp-vio1-msch0@ffa87800 { 2261 compatible = "rockchip,rk3399-nocp"; 2262 reg = <0x0 0xffa87800 0x0 0x400>; 2263 }; 2264 2265 nocp_cci_msch1: nocp-cci-msch1@ffa8e000 { 2266 compatible = "rockchip,rk3399-nocp"; 2267 reg = <0x0 0xffa8e000 0x0 0x400>; 2268 }; 2269 2270 nocp_gpu_msch1: nocp-gpu-msch1@ffa8e400 { 2271 compatible = "rockchip,rk3399-nocp"; 2272 reg = <0x0 0xffa8e400 0x0 0x400>; 2273 }; 2274 2275 nocp_hp_msch1: nocp-hp-msch1@ffa8e800 { 2276 compatible = "rockchip,rk3399-nocp"; 2277 reg = <0x0 0xffa8e800 0x0 0x400>; 2278 }; 2279 2280 nocp_lp_msch1: nocp-lp-msch1@ffa8ec00 { 2281 compatible = "rockchip,rk3399-nocp"; 2282 reg = <0x0 0xffa8ec00 0x0 0x400>; 2283 }; 2284 2285 nocp_video_msch1: nocp-video-msch1@ffa8f000 { 2286 compatible = "rockchip,rk3399-nocp"; 2287 reg = <0x0 0xffa8f000 0x0 0x400>; 2288 }; 2289 2290 nocp_vio0_msch1: nocp-vio0-msch1@ffa8f400 { 2291 compatible = "rockchip,rk3399-nocp"; 2292 reg = <0x0 0xffa8f400 0x0 0x400>; 2293 }; 2294 2295 nocp_vio1_msch1: nocp-vio1-msch1@ffa8f800 { 2296 compatible = "rockchip,rk3399-nocp"; 2297 reg = <0x0 0xffa8f800 0x0 0x400>; 2298 }; 2299 2300 rockchip_system_monitor: rockchip-system-monitor { 2301 compatible = "rockchip,system-monitor"; 2302 2303 rockchip,thermal-zone = "soc-thermal"; 2304 rockchip,polling-delay = <200>; /* milliseconds */ 2305 }; 2306 2307 pinctrl: pinctrl { 2308 compatible = "rockchip,rk3399-pinctrl"; 2309 rockchip,grf = <&grf>; 2310 rockchip,pmu = <&pmugrf>; 2311 #address-cells = <2>; 2312 #size-cells = <2>; 2313 ranges; 2314 2315 gpio0: gpio0@ff720000 { 2316 compatible = "rockchip,gpio-bank"; 2317 reg = <0x0 0xff720000 0x0 0x100>; 2318 clocks = <&pmucru PCLK_GPIO0_PMU>; 2319 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 2320 2321 gpio-controller; 2322 #gpio-cells = <0x2>; 2323 2324 interrupt-controller; 2325 #interrupt-cells = <0x2>; 2326 }; 2327 2328 gpio1: gpio1@ff730000 { 2329 compatible = "rockchip,gpio-bank"; 2330 reg = <0x0 0xff730000 0x0 0x100>; 2331 clocks = <&pmucru PCLK_GPIO1_PMU>; 2332 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 2333 2334 gpio-controller; 2335 #gpio-cells = <0x2>; 2336 2337 interrupt-controller; 2338 #interrupt-cells = <0x2>; 2339 }; 2340 2341 gpio2: gpio2@ff780000 { 2342 compatible = "rockchip,gpio-bank"; 2343 reg = <0x0 0xff780000 0x0 0x100>; 2344 clocks = <&cru PCLK_GPIO2>; 2345 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 2346 2347 gpio-controller; 2348 #gpio-cells = <0x2>; 2349 2350 interrupt-controller; 2351 #interrupt-cells = <0x2>; 2352 }; 2353 2354 gpio3: gpio3@ff788000 { 2355 compatible = "rockchip,gpio-bank"; 2356 reg = <0x0 0xff788000 0x0 0x100>; 2357 clocks = <&cru PCLK_GPIO3>; 2358 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 2359 2360 gpio-controller; 2361 #gpio-cells = <0x2>; 2362 2363 interrupt-controller; 2364 #interrupt-cells = <0x2>; 2365 }; 2366 2367 gpio4: gpio4@ff790000 { 2368 compatible = "rockchip,gpio-bank"; 2369 reg = <0x0 0xff790000 0x0 0x100>; 2370 clocks = <&cru PCLK_GPIO4>; 2371 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 2372 2373 gpio-controller; 2374 #gpio-cells = <0x2>; 2375 2376 interrupt-controller; 2377 #interrupt-cells = <0x2>; 2378 }; 2379 2380 pcfg_pull_up: pcfg-pull-up { 2381 bias-pull-up; 2382 }; 2383 2384 pcfg_pull_down: pcfg-pull-down { 2385 bias-pull-down; 2386 }; 2387 2388 pcfg_pull_none: pcfg-pull-none { 2389 bias-disable; 2390 }; 2391 2392 pcfg_pull_none_10ma: pcfg-pull-none-10ma { 2393 bias-disable; 2394 drive-strength = <10>; 2395 }; 2396 2397 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2398 bias-disable; 2399 drive-strength = <12>; 2400 }; 2401 2402 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 2403 bias-disable; 2404 drive-strength = <13>; 2405 }; 2406 2407 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 2408 bias-disable; 2409 drive-strength = <18>; 2410 }; 2411 2412 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2413 bias-disable; 2414 drive-strength = <20>; 2415 }; 2416 2417 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2418 bias-pull-up; 2419 drive-strength = <2>; 2420 }; 2421 2422 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2423 bias-pull-up; 2424 drive-strength = <8>; 2425 }; 2426 2427 pcfg_pull_up_10ma: pcfg-pull-up-10ma { 2428 bias-pull-up; 2429 drive-strength = <10>; 2430 }; 2431 2432 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2433 bias-pull-up; 2434 drive-strength = <18>; 2435 }; 2436 2437 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2438 bias-pull-up; 2439 drive-strength = <20>; 2440 }; 2441 2442 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2443 bias-pull-down; 2444 drive-strength = <4>; 2445 }; 2446 2447 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2448 bias-pull-down; 2449 drive-strength = <8>; 2450 }; 2451 2452 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2453 bias-pull-down; 2454 drive-strength = <12>; 2455 }; 2456 2457 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2458 bias-pull-down; 2459 drive-strength = <18>; 2460 }; 2461 2462 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2463 bias-pull-down; 2464 drive-strength = <20>; 2465 }; 2466 2467 pcfg_output_high: pcfg-output-high { 2468 output-high; 2469 }; 2470 2471 pcfg_output_low: pcfg-output-low { 2472 output-low; 2473 }; 2474 2475 clock { 2476 clk_32k: clk-32k { 2477 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2478 }; 2479 }; 2480 2481 edp { 2482 edp_hpd: edp-hpd { 2483 rockchip,pins = 2484 <4 RK_PC7 2 &pcfg_pull_none>; 2485 }; 2486 }; 2487 2488 gmac { 2489 rgmii_pins: rgmii-pins { 2490 rockchip,pins = 2491 /* mac_txclk */ 2492 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2493 /* mac_rxclk */ 2494 <3 RK_PB6 1 &pcfg_pull_none>, 2495 /* mac_mdio */ 2496 <3 RK_PB5 1 &pcfg_pull_none>, 2497 /* mac_txen */ 2498 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2499 /* mac_clk */ 2500 <3 RK_PB3 1 &pcfg_pull_none>, 2501 /* mac_rxdv */ 2502 <3 RK_PB1 1 &pcfg_pull_none>, 2503 /* mac_mdc */ 2504 <3 RK_PB0 1 &pcfg_pull_none>, 2505 /* mac_rxd1 */ 2506 <3 RK_PA7 1 &pcfg_pull_none>, 2507 /* mac_rxd0 */ 2508 <3 RK_PA6 1 &pcfg_pull_none>, 2509 /* mac_txd1 */ 2510 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2511 /* mac_txd0 */ 2512 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2513 /* mac_rxd3 */ 2514 <3 RK_PA3 1 &pcfg_pull_none>, 2515 /* mac_rxd2 */ 2516 <3 RK_PA2 1 &pcfg_pull_none>, 2517 /* mac_txd3 */ 2518 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2519 /* mac_txd2 */ 2520 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2521 }; 2522 2523 rmii_pins: rmii-pins { 2524 rockchip,pins = 2525 /* mac_mdio */ 2526 <3 RK_PB5 1 &pcfg_pull_none>, 2527 /* mac_txen */ 2528 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2529 /* mac_clk */ 2530 <3 RK_PB3 1 &pcfg_pull_none>, 2531 /* mac_rxer */ 2532 <3 RK_PB2 1 &pcfg_pull_none>, 2533 /* mac_rxdv */ 2534 <3 RK_PB1 1 &pcfg_pull_none>, 2535 /* mac_mdc */ 2536 <3 RK_PB0 1 &pcfg_pull_none>, 2537 /* mac_rxd1 */ 2538 <3 RK_PA7 1 &pcfg_pull_none>, 2539 /* mac_rxd0 */ 2540 <3 RK_PA6 1 &pcfg_pull_none>, 2541 /* mac_txd1 */ 2542 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2543 /* mac_txd0 */ 2544 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2545 }; 2546 }; 2547 2548 i2c0 { 2549 i2c0_xfer: i2c0-xfer { 2550 rockchip,pins = 2551 <1 RK_PB7 2 &pcfg_pull_none>, 2552 <1 RK_PC0 2 &pcfg_pull_none>; 2553 }; 2554 }; 2555 2556 i2c1 { 2557 i2c1_xfer: i2c1-xfer { 2558 rockchip,pins = 2559 <4 RK_PA2 1 &pcfg_pull_none>, 2560 <4 RK_PA1 1 &pcfg_pull_none>; 2561 }; 2562 }; 2563 2564 i2c2 { 2565 i2c2_xfer: i2c2-xfer { 2566 rockchip,pins = 2567 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2568 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2569 }; 2570 }; 2571 2572 i2c3 { 2573 i2c3_xfer: i2c3-xfer { 2574 rockchip,pins = 2575 <4 RK_PC1 1 &pcfg_pull_none>, 2576 <4 RK_PC0 1 &pcfg_pull_none>; 2577 }; 2578 2579 i2c3_gpio: i2c3_gpio { 2580 rockchip,pins = 2581 <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, 2582 <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; 2583 }; 2584 2585 }; 2586 2587 i2c4 { 2588 i2c4_xfer: i2c4-xfer { 2589 rockchip,pins = 2590 <1 RK_PB4 1 &pcfg_pull_none>, 2591 <1 RK_PB3 1 &pcfg_pull_none>; 2592 }; 2593 }; 2594 2595 i2c5 { 2596 i2c5_xfer: i2c5-xfer { 2597 rockchip,pins = 2598 <3 RK_PB3 2 &pcfg_pull_none>, 2599 <3 RK_PB2 2 &pcfg_pull_none>; 2600 }; 2601 }; 2602 2603 i2c6 { 2604 i2c6_xfer: i2c6-xfer { 2605 rockchip,pins = 2606 <2 RK_PB2 2 &pcfg_pull_none>, 2607 <2 RK_PB1 2 &pcfg_pull_none>; 2608 }; 2609 }; 2610 2611 i2c7 { 2612 i2c7_xfer: i2c7-xfer { 2613 rockchip,pins = 2614 <2 RK_PB0 2 &pcfg_pull_none>, 2615 <2 RK_PA7 2 &pcfg_pull_none>; 2616 }; 2617 }; 2618 2619 i2c8 { 2620 i2c8_xfer: i2c8-xfer { 2621 rockchip,pins = 2622 <1 RK_PC5 1 &pcfg_pull_none>, 2623 <1 RK_PC4 1 &pcfg_pull_none>; 2624 }; 2625 }; 2626 2627 i2s0 { 2628 i2s0_2ch_bus: i2s0-2ch-bus { 2629 rockchip,pins = 2630 <3 RK_PD0 1 &pcfg_pull_none>, 2631 <3 RK_PD1 1 &pcfg_pull_none>, 2632 <3 RK_PD2 1 &pcfg_pull_none>, 2633 <3 RK_PD3 1 &pcfg_pull_none>, 2634 <3 RK_PD7 1 &pcfg_pull_none>, 2635 <4 RK_PA0 1 &pcfg_pull_none>; 2636 }; 2637 2638 i2s0_8ch_bus: i2s0-8ch-bus { 2639 rockchip,pins = 2640 <3 RK_PD0 1 &pcfg_pull_none>, 2641 <3 RK_PD1 1 &pcfg_pull_none>, 2642 <3 RK_PD2 1 &pcfg_pull_none>, 2643 <3 RK_PD3 1 &pcfg_pull_none>, 2644 <3 RK_PD4 1 &pcfg_pull_none>, 2645 <3 RK_PD5 1 &pcfg_pull_none>, 2646 <3 RK_PD6 1 &pcfg_pull_none>, 2647 <3 RK_PD7 1 &pcfg_pull_none>; 2648 }; 2649 2650 i2s_8ch_mclk: i2s-8ch-mclk { 2651 rockchip,pins = 2652 <4 RK_PA0 1 &pcfg_pull_none>; 2653 }; 2654 }; 2655 2656 i2s1 { 2657 i2s1_2ch_bus: i2s1-2ch-bus { 2658 rockchip,pins = 2659 <4 RK_PA3 1 &pcfg_pull_none>, 2660 <4 RK_PA4 1 &pcfg_pull_none>, 2661 <4 RK_PA5 1 &pcfg_pull_none>, 2662 <4 RK_PA6 1 &pcfg_pull_none>, 2663 <4 RK_PA7 1 &pcfg_pull_none>; 2664 }; 2665 }; 2666 2667 sdio0 { 2668 sdio0_bus1: sdio0-bus1 { 2669 rockchip,pins = 2670 <2 RK_PC4 1 &pcfg_pull_up>; 2671 }; 2672 2673 sdio0_bus4: sdio0-bus4 { 2674 rockchip,pins = 2675 <2 RK_PC4 1 &pcfg_pull_up>, 2676 <2 RK_PC5 1 &pcfg_pull_up>, 2677 <2 RK_PC6 1 &pcfg_pull_up>, 2678 <2 RK_PC7 1 &pcfg_pull_up>; 2679 }; 2680 2681 sdio0_cmd: sdio0-cmd { 2682 rockchip,pins = 2683 <2 RK_PD0 1 &pcfg_pull_up>; 2684 }; 2685 2686 sdio0_clk: sdio0-clk { 2687 rockchip,pins = 2688 <2 RK_PD1 1 &pcfg_pull_none>; 2689 }; 2690 2691 sdio0_cd: sdio0-cd { 2692 rockchip,pins = 2693 <2 RK_PD2 1 &pcfg_pull_up>; 2694 }; 2695 2696 sdio0_pwr: sdio0-pwr { 2697 rockchip,pins = 2698 <2 RK_PD3 1 &pcfg_pull_up>; 2699 }; 2700 2701 sdio0_bkpwr: sdio0-bkpwr { 2702 rockchip,pins = 2703 <2 RK_PD4 1 &pcfg_pull_up>; 2704 }; 2705 2706 sdio0_wp: sdio0-wp { 2707 rockchip,pins = 2708 <0 RK_PA3 1 &pcfg_pull_up>; 2709 }; 2710 2711 sdio0_int: sdio0-int { 2712 rockchip,pins = 2713 <0 RK_PA4 1 &pcfg_pull_up>; 2714 }; 2715 }; 2716 2717 sdmmc { 2718 sdmmc_bus1: sdmmc-bus1 { 2719 rockchip,pins = 2720 <4 RK_PB0 1 &pcfg_pull_up>; 2721 }; 2722 2723 sdmmc_bus4: sdmmc-bus4 { 2724 rockchip,pins = 2725 <4 RK_PB0 1 &pcfg_pull_up>, 2726 <4 RK_PB1 1 &pcfg_pull_up>, 2727 <4 RK_PB2 1 &pcfg_pull_up>, 2728 <4 RK_PB3 1 &pcfg_pull_up>; 2729 }; 2730 2731 sdmmc_clk: sdmmc-clk { 2732 rockchip,pins = 2733 <4 RK_PB4 1 &pcfg_pull_none>; 2734 }; 2735 2736 sdmmc_cmd: sdmmc-cmd { 2737 rockchip,pins = 2738 <4 RK_PB5 1 &pcfg_pull_up>; 2739 }; 2740 2741 sdmmc_cd: sdmmc-cd { 2742 rockchip,pins = 2743 <0 RK_PA7 1 &pcfg_pull_up>; 2744 }; 2745 2746 sdmmc_wp: sdmmc-wp { 2747 rockchip,pins = 2748 <0 RK_PB0 1 &pcfg_pull_up>; 2749 }; 2750 }; 2751 2752 suspend { 2753 ap_pwroff: ap-pwroff { 2754 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2755 }; 2756 2757 ddrio_pwroff: ddrio-pwroff { 2758 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2759 }; 2760 }; 2761 2762 spdif { 2763 spdif_bus: spdif-bus { 2764 rockchip,pins = 2765 <4 RK_PC5 1 &pcfg_pull_none>; 2766 }; 2767 2768 spdif_bus_1: spdif-bus-1 { 2769 rockchip,pins = 2770 <3 RK_PC0 3 &pcfg_pull_none>; 2771 }; 2772 }; 2773 2774 spi0 { 2775 spi0_clk: spi0-clk { 2776 rockchip,pins = 2777 <3 RK_PA6 2 &pcfg_pull_up>; 2778 }; 2779 spi0_cs0: spi0-cs0 { 2780 rockchip,pins = 2781 <3 RK_PA7 2 &pcfg_pull_up>; 2782 }; 2783 spi0_cs1: spi0-cs1 { 2784 rockchip,pins = 2785 <3 RK_PB0 2 &pcfg_pull_up>; 2786 }; 2787 spi0_tx: spi0-tx { 2788 rockchip,pins = 2789 <3 RK_PA5 2 &pcfg_pull_up>; 2790 }; 2791 spi0_rx: spi0-rx { 2792 rockchip,pins = 2793 <3 RK_PA4 2 &pcfg_pull_up>; 2794 }; 2795 }; 2796 2797 spi1 { 2798 spi1_clk: spi1-clk { 2799 rockchip,pins = 2800 <1 RK_PB1 2 &pcfg_pull_up>; 2801 }; 2802 spi1_cs0: spi1-cs0 { 2803 rockchip,pins = 2804 <1 RK_PB2 2 &pcfg_pull_up>; 2805 }; 2806 spi1_rx: spi1-rx { 2807 rockchip,pins = 2808 <1 RK_PA7 2 &pcfg_pull_up>; 2809 }; 2810 spi1_tx: spi1-tx { 2811 rockchip,pins = 2812 <1 RK_PB0 2 &pcfg_pull_up>; 2813 }; 2814 }; 2815 2816 spi2 { 2817 spi2_clk: spi2-clk { 2818 rockchip,pins = 2819 <2 RK_PB3 1 &pcfg_pull_up>; 2820 }; 2821 spi2_cs0: spi2-cs0 { 2822 rockchip,pins = 2823 <2 RK_PB4 1 &pcfg_pull_up>; 2824 }; 2825 spi2_rx: spi2-rx { 2826 rockchip,pins = 2827 <2 RK_PB1 1 &pcfg_pull_up>; 2828 }; 2829 spi2_tx: spi2-tx { 2830 rockchip,pins = 2831 <2 RK_PB2 1 &pcfg_pull_up>; 2832 }; 2833 }; 2834 2835 spi3 { 2836 spi3_clk: spi3-clk { 2837 rockchip,pins = 2838 <1 RK_PC1 1 &pcfg_pull_up>; 2839 }; 2840 spi3_cs0: spi3-cs0 { 2841 rockchip,pins = 2842 <1 RK_PC2 1 &pcfg_pull_up>; 2843 }; 2844 spi3_rx: spi3-rx { 2845 rockchip,pins = 2846 <1 RK_PB7 1 &pcfg_pull_up>; 2847 }; 2848 spi3_tx: spi3-tx { 2849 rockchip,pins = 2850 <1 RK_PC0 1 &pcfg_pull_up>; 2851 }; 2852 }; 2853 2854 spi4 { 2855 spi4_clk: spi4-clk { 2856 rockchip,pins = 2857 <3 RK_PA2 2 &pcfg_pull_up>; 2858 }; 2859 spi4_cs0: spi4-cs0 { 2860 rockchip,pins = 2861 <3 RK_PA3 2 &pcfg_pull_up>; 2862 }; 2863 spi4_rx: spi4-rx { 2864 rockchip,pins = 2865 <3 RK_PA0 2 &pcfg_pull_up>; 2866 }; 2867 spi4_tx: spi4-tx { 2868 rockchip,pins = 2869 <3 RK_PA1 2 &pcfg_pull_up>; 2870 }; 2871 }; 2872 2873 spi5 { 2874 spi5_clk: spi5-clk { 2875 rockchip,pins = 2876 <2 RK_PC6 2 &pcfg_pull_up>; 2877 }; 2878 spi5_cs0: spi5-cs0 { 2879 rockchip,pins = 2880 <2 RK_PC7 2 &pcfg_pull_up>; 2881 }; 2882 spi5_rx: spi5-rx { 2883 rockchip,pins = 2884 <2 RK_PC4 2 &pcfg_pull_up>; 2885 }; 2886 spi5_tx: spi5-tx { 2887 rockchip,pins = 2888 <2 RK_PC5 2 &pcfg_pull_up>; 2889 }; 2890 }; 2891 2892 testclk { 2893 test_clkout0: test-clkout0 { 2894 rockchip,pins = 2895 <0 RK_PA0 1 &pcfg_pull_none>; 2896 }; 2897 2898 test_clkout1: test-clkout1 { 2899 rockchip,pins = 2900 <2 RK_PD1 2 &pcfg_pull_none>; 2901 }; 2902 2903 test_clkout2: test-clkout2 { 2904 rockchip,pins = 2905 <0 RK_PB0 3 &pcfg_pull_none>; 2906 }; 2907 }; 2908 2909 tsadc { 2910 otp_pin: otp-pin { 2911 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2912 }; 2913 2914 otp_out: otp-out { 2915 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2916 }; 2917 }; 2918 2919 uart0 { 2920 uart0_xfer: uart0-xfer { 2921 rockchip,pins = 2922 <2 RK_PC0 1 &pcfg_pull_up>, 2923 <2 RK_PC1 1 &pcfg_pull_up>; 2924 }; 2925 2926 uart0_cts: uart0-cts { 2927 rockchip,pins = 2928 <2 RK_PC2 1 &pcfg_pull_none>; 2929 }; 2930 2931 uart0_rts: uart0-rts { 2932 rockchip,pins = 2933 <2 RK_PC3 1 &pcfg_pull_none>; 2934 }; 2935 }; 2936 2937 uart1 { 2938 uart1_xfer: uart1-xfer { 2939 rockchip,pins = 2940 <3 RK_PB4 2 &pcfg_pull_up>, 2941 <3 RK_PB5 2 &pcfg_pull_up>; 2942 }; 2943 }; 2944 2945 uart2a { 2946 uart2a_xfer: uart2a-xfer { 2947 rockchip,pins = 2948 <4 RK_PB0 2 &pcfg_pull_up>, 2949 <4 RK_PB1 2 &pcfg_pull_up>; 2950 }; 2951 }; 2952 2953 uart2b { 2954 uart2b_xfer: uart2b-xfer { 2955 rockchip,pins = 2956 <4 RK_PC0 2 &pcfg_pull_up>, 2957 <4 RK_PC1 2 &pcfg_pull_up>; 2958 }; 2959 }; 2960 2961 uart2c { 2962 uart2c_xfer: uart2c-xfer { 2963 rockchip,pins = 2964 <4 RK_PC3 1 &pcfg_pull_up>, 2965 <4 RK_PC4 1 &pcfg_pull_up>; 2966 }; 2967 }; 2968 2969 uart3 { 2970 uart3_xfer: uart3-xfer { 2971 rockchip,pins = 2972 <3 RK_PB6 2 &pcfg_pull_up>, 2973 <3 RK_PB7 2 &pcfg_pull_up>; 2974 }; 2975 2976 uart3_cts: uart3-cts { 2977 rockchip,pins = 2978 <3 RK_PC0 2 &pcfg_pull_none>; 2979 }; 2980 2981 uart3_rts: uart3-rts { 2982 rockchip,pins = 2983 <3 RK_PC1 2 &pcfg_pull_none>; 2984 }; 2985 }; 2986 2987 uart4 { 2988 uart4_xfer: uart4-xfer { 2989 rockchip,pins = 2990 <1 RK_PA7 1 &pcfg_pull_up>, 2991 <1 RK_PB0 1 &pcfg_pull_up>; 2992 }; 2993 }; 2994 2995 uarthdcp { 2996 uarthdcp_xfer: uarthdcp-xfer { 2997 rockchip,pins = 2998 <4 RK_PC5 2 &pcfg_pull_up>, 2999 <4 RK_PC6 2 &pcfg_pull_up>; 3000 }; 3001 }; 3002 3003 pwm0 { 3004 pwm0_pin: pwm0-pin { 3005 rockchip,pins = 3006 <4 RK_PC2 1 &pcfg_pull_none>; 3007 }; 3008 3009 pwm0_pin_pull_down: pwm0-pin-pull-down { 3010 rockchip,pins = 3011 <4 RK_PC2 1 &pcfg_pull_down>; 3012 }; 3013 3014 vop0_pwm_pin: vop0-pwm-pin { 3015 rockchip,pins = 3016 <4 RK_PC2 2 &pcfg_pull_none>; 3017 }; 3018 3019 vop1_pwm_pin: vop1-pwm-pin { 3020 rockchip,pins = 3021 <4 RK_PC2 3 &pcfg_pull_none>; 3022 }; 3023 }; 3024 3025 pwm1 { 3026 pwm1_pin: pwm1-pin { 3027 rockchip,pins = 3028 <4 RK_PC6 1 &pcfg_pull_none>; 3029 }; 3030 3031 pwm1_pin_pull_down: pwm1-pin-pull-down { 3032 rockchip,pins = 3033 <4 RK_PC6 1 &pcfg_pull_down>; 3034 }; 3035 }; 3036 3037 pwm2 { 3038 pwm2_pin: pwm2-pin { 3039 rockchip,pins = 3040 <1 RK_PC3 1 &pcfg_pull_none>; 3041 }; 3042 3043 pwm2_pin_pull_down: pwm2-pin-pull-down { 3044 rockchip,pins = 3045 <1 RK_PC3 1 &pcfg_pull_down>; 3046 }; 3047 }; 3048 3049 pwm3a { 3050 pwm3a_pin: pwm3a-pin { 3051 rockchip,pins = 3052 <0 RK_PA6 1 &pcfg_pull_none>; 3053 }; 3054 3055 pwm3a_pin_pull_down: pwm3a-pin-pull-down { 3056 rockchip,pins = 3057 <0 RK_PA6 1 &pcfg_pull_down>; 3058 }; 3059 }; 3060 3061 pwm3b { 3062 pwm3b_pin: pwm3b-pin { 3063 rockchip,pins = 3064 <1 RK_PB6 1 &pcfg_pull_none>; 3065 }; 3066 3067 pwm3b_pin_pull_down: pwm3b-pin-pull-down { 3068 rockchip,pins = 3069 <1 RK_PB6 1 &pcfg_pull_down>; 3070 }; 3071 }; 3072 3073 hdmi { 3074 hdmi_i2c_xfer: hdmi-i2c-xfer { 3075 rockchip,pins = 3076 <4 RK_PC1 3 &pcfg_pull_none>, 3077 <4 RK_PC0 3 &pcfg_pull_none>; 3078 }; 3079 3080 hdmi_cec: hdmi-cec { 3081 rockchip,pins = 3082 <4 RK_PC7 1 &pcfg_pull_none>; 3083 }; 3084 }; 3085 3086 pcie { 3087 pcie_clkreqn_cpm: pci-clkreqn-cpm { 3088 rockchip,pins = 3089 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 3090 }; 3091 3092 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 3093 rockchip,pins = 3094 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 3095 }; 3096 }; 3097 3098 }; 3099 3100 rockchip_suspend: rockchip-suspend { 3101 compatible = "rockchip,pm-rk3399"; 3102 status = "disabled"; 3103 rockchip,sleep-debug-en = <0>; 3104 rockchip,virtual-poweroff = <0>; 3105 rockchip,sleep-mode-config = < 3106 (0 3107 | RKPM_SLP_ARMPD 3108 | RKPM_SLP_PERILPPD 3109 | RKPM_SLP_DDR_RET 3110 | RKPM_SLP_PLLPD 3111 | RKPM_SLP_OSC_DIS 3112 | RKPM_SLP_CENTER_PD 3113 | RKPM_SLP_AP_PWROFF 3114 ) 3115 >; 3116 rockchip,wakeup-config = < 3117 (0 3118 | RKPM_GPIO_WKUP_EN 3119 ) 3120 >; 3121 }; 3122}; 3123