1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd. 3 4/dts-v1/; 5 6#include "rk3399-excavator-sapphire.dtsi" 7#include "rk3399-linux.dtsi" 8#include <dt-bindings/input/input.h> 9 10/ { 11 model = "Rockchip RK3399 Excavator Board (Linux Opensource)"; 12 compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399"; 13 14 vcc_lcd: vcc-lcd { 15 compatible = "regulator-fixed"; 16 regulator-name = "vcc_lcd"; 17 gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; 18 startup-delay-us = <20000>; 19 enable-active-high; 20 regulator-min-microvolt = <3300000>; 21 regulator-max-microvolt = <3300000>; 22 regulator-boot-on; 23 vin-supply = <&vcc5v0_sys>; 24 }; 25 26 panel: panel { 27 compatible = "simple-panel"; 28 backlight = <&backlight>; 29 power-supply = <&vcc_lcd>; 30 enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 31 prepare-delay-ms = <20>; 32 enable-delay-ms = <20>; 33 34 display-timings { 35 native-mode = <&timing0>; 36 37 timing0: timing0 { 38 clock-frequency = <200000000>; 39 hactive = <1536>; 40 vactive = <2048>; 41 hfront-porch = <12>; 42 hsync-len = <16>; 43 hback-porch = <48>; 44 vfront-porch = <8>; 45 vsync-len = <4>; 46 vback-porch = <8>; 47 hsync-active = <0>; 48 vsync-active = <0>; 49 de-active = <0>; 50 pixelclk-active = <0>; 51 }; 52 }; 53 54 ports { 55 panel_in: endpoint { 56 remote-endpoint = <&edp_out>; 57 }; 58 }; 59 }; 60 61 hdmi_sound: hdmi-sound { 62 status = "okay"; 63 }; 64 65 gpio-keys { 66 compatible = "gpio-keys"; 67 #address-cells = <1>; 68 #size-cells = <0>; 69 autorepeat; 70 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pwrbtn>; 73 74 button@0 { 75 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; 76 linux,code = <KEY_POWER>; 77 label = "GPIO Key Power"; 78 linux,input-type = <1>; 79 gpio-key,wakeup = <1>; 80 debounce-interval = <100>; 81 }; 82 }; 83 84 vccadc_ref: vccadc-ref { 85 compatible = "regulator-fixed"; 86 regulator-name = "vcc1v8_sys"; 87 regulator-always-on; 88 regulator-boot-on; 89 regulator-min-microvolt = <1800000>; 90 regulator-max-microvolt = <1800000>; 91 }; 92 93 ext_cam_clk: external-camera-clock { 94 compatible = "fixed-clock"; 95 clock-frequency = <27000000>; 96 clock-output-names = "CLK_CAMERA_27MHZ"; 97 #clock-cells = <0>; 98 }; 99 100 adc-keys { 101 compatible = "adc-keys"; 102 io-channels = <&saradc 1>; 103 io-channel-names = "buttons"; 104 poll-interval = <100>; 105 keyup-threshold-microvolt = <1800000>; 106 107 button-up { 108 label = "Volume Up"; 109 linux,code = <KEY_VOLUMEUP>; 110 press-threshold-microvolt = <100000>; 111 }; 112 113 button-down { 114 label = "Volume Down"; 115 linux,code = <KEY_VOLUMEDOWN>; 116 press-threshold-microvolt = <300000>; 117 }; 118 119 back { 120 label = "Back"; 121 linux,code = <KEY_BACK>; 122 press-threshold-microvolt = <985000>; 123 }; 124 125 menu { 126 label = "Menu"; 127 linux,code = <KEY_MENU>; 128 press-threshold-microvolt = <1314000>; 129 }; 130 }; 131}; 132 133&dfi { 134 status = "okay"; 135}; 136 137&dmc { 138 status = "okay"; 139 center-supply = <&vdd_center>; 140 upthreshold = <40>; 141 downdifferential = <20>; 142 system-status-freq = < 143 /*system status freq(KHz)*/ 144 SYS_STATUS_NORMAL 856000 145 SYS_STATUS_REBOOT 856000 146 SYS_STATUS_SUSPEND 328000 147 SYS_STATUS_VIDEO_1080P 666000 148 SYS_STATUS_VIDEO_4K 856000 149 SYS_STATUS_VIDEO_4K_10B 856000 150 SYS_STATUS_PERFORMANCE 856000 151 SYS_STATUS_BOOST 856000 152 SYS_STATUS_DUALVIEW 856000 153 SYS_STATUS_ISP 856000 154 >; 155 vop-bw-dmc-freq = < 156 /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ 157 0 762 416000 158 763 3012 666000 159 3013 99999 856000 160 >; 161 162 vop-pn-msch-readlatency = < 163 0 0x20 164 4 0x20 165 >; 166 167 auto-min-freq = <328000>; 168 auto-freq-en = <0>; 169}; 170 171&dmc_opp_table { 172 compatible = "operating-points-v2"; 173 174 opp-200000000 { 175 opp-hz = /bits/ 64 <200000000>; 176 opp-microvolt = <900000>; 177 status = "disabled"; 178 }; 179 opp-300000000 { 180 opp-hz = /bits/ 64 <300000000>; 181 opp-microvolt = <900000>; 182 status = "disabled"; 183 }; 184 opp-328000000 { 185 opp-hz = /bits/ 64 <328000000>; 186 opp-microvolt = <900000>; 187 }; 188 opp-400000000 { 189 opp-hz = /bits/ 64 <400000000>; 190 opp-microvolt = <900000>; 191 status = "disabled"; 192 }; 193 opp-416000000 { 194 opp-hz = /bits/ 64 <416000000>; 195 opp-microvolt = <900000>; 196 }; 197 opp-528000000 { 198 opp-hz = /bits/ 64 <528000000>; 199 opp-microvolt = <900000>; 200 status = "disabled"; 201 }; 202 opp-600000000 { 203 opp-hz = /bits/ 64 <600000000>; 204 opp-microvolt = <900000>; 205 status = "disabled"; 206 }; 207 opp-666000000 { 208 opp-hz = /bits/ 64 <666000000>; 209 opp-microvolt = <900000>; 210 }; 211 opp-800000000 { 212 opp-hz = /bits/ 64 <800000000>; 213 opp-microvolt = <900000>; 214 status = "disabled"; 215 }; 216 opp-856000000 { 217 opp-hz = /bits/ 64 <856000000>; 218 opp-microvolt = <900000>; 219 }; 220 opp-928000000 { 221 opp-hz = /bits/ 64 <928000000>; 222 opp-microvolt = <900000>; 223 status = "disabled"; 224 }; 225}; 226 227&rkisp1_0 { 228 status = "okay"; 229 230 port { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 234 isp0_mipi_in: endpoint@0 { 235 reg = <0>; 236 remote-endpoint = <&dphy_rx0_out>; 237 }; 238 }; 239}; 240 241&mipi_dphy_rx0 { 242 status = "okay"; 243 244 ports { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 248 port@0 { 249 reg = <0>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 253 mipi_in_ucam0: endpoint@1 { 254 reg = <1>; 255 remote-endpoint = <&ucam_out0>; 256 data-lanes = <1 2>; 257 }; 258 }; 259 260 port@1 { 261 reg = <1>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 265 dphy_rx0_out: endpoint@0 { 266 reg = <0>; 267 remote-endpoint = <&isp0_mipi_in>; 268 }; 269 }; 270 }; 271}; 272 273&isp0_mmu { 274 status = "okay"; 275}; 276 277&rkisp1_1 { 278 status = "okay"; 279 280 port { 281 #address-cells = <1>; 282 #size-cells = <0>; 283 284 isp1_mipi_in: endpoint@0 { 285 reg = <0>; 286 remote-endpoint = <&dphy_tx1rx1_out>; 287 }; 288 }; 289}; 290 291&mipi_dphy_tx1rx1 { 292 status = "okay"; 293 294 ports { 295 #address-cells = <1>; 296 #size-cells = <0>; 297 298 port@0 { 299 reg = <0>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 303 mipi_in_ucam1: endpoint@1 { 304 reg = <1>; 305 /* Unlinked camera */ 306 //remote-endpoint = <&ucam_out1>; 307 data-lanes = <1 2>; 308 }; 309 }; 310 311 port@1 { 312 reg = <1>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 316 dphy_tx1rx1_out: endpoint@0 { 317 reg = <0>; 318 remote-endpoint = <&isp1_mipi_in>; 319 }; 320 }; 321 }; 322}; 323 324&isp1_mmu { 325 status = "okay"; 326}; 327 328&saradc { 329 vref-supply = <&vccadc_ref>; 330}; 331 332&backlight { 333 status = "okay"; 334 enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 335}; 336 337&cdn_dp { 338 status = "okay"; 339 extcon = <&fusb0>; 340 phys = <&tcphy0_dp>; 341}; 342 343&display_subsystem { 344 status = "okay"; 345}; 346 347&route_edp { 348 status = "okay"; 349}; 350 351&edp { 352 status = "okay"; 353 force-hpd; 354 355 ports { 356 port@1 { 357 reg = <1>; 358 359 edp_out: endpoint { 360 remote-endpoint = <&panel_in>; 361 }; 362 }; 363 }; 364}; 365 366&edp_in_vopb { 367 status = "disabled"; 368}; 369 370&hdmi { 371 pinctrl-names = "default"; 372 pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 #sound-dai-cells = <0>; 376 status = "okay"; 377}; 378 379&hdmi_in_vopl { 380 status = "disabled"; 381}; 382 383&i2c1 { 384 status = "okay"; 385 386 gsl3673: gsl3673@40 { 387 compatible = "GSL,GSL3673"; 388 reg = <0x40>; 389 screen_max_x = <1536>; 390 screen_max_y = <2048>; 391 irq_gpio_number = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; 392 rst_gpio_number = <&gpio4 22 GPIO_ACTIVE_HIGH>; 393 }; 394 395 tc358749x: tc358749x@f { 396 compatible = "toshiba,tc358749"; 397 reg = <0xf>; 398 clocks = <&ext_cam_clk>; 399 clock-names = "refclk"; 400 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; 401 interrupt-parent = <&gpio2>; 402 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&hdmiin_gpios>; 405 status = "disabled"; 406 port { 407 hdmiin_out0: endpoint { 408 /* Unlinked mipi dphy rx0 */ 409 //remote-endpoint = <&mipi_in_ucam0>; 410 data-lanes = <1 2 3 4>; 411 clock-noncontinuous; 412 link-frequencies = 413 /bits/ 64 <297000000>; 414 }; 415 }; 416 }; 417 418 ov13850: ov13850@10 { 419 compatible = "ovti,ov13850"; 420 status = "okay"; 421 reg = <0x10>; 422 clocks = <&cru SCLK_CIF_OUT>; 423 clock-names = "xvclk"; 424 425 /* conflict with csi-ctl-gpios */ 426 reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 427 pwdn-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 428 pinctrl-names = "rockchip,camera_default"; 429 pinctrl-0 = <&cif_clkout>; 430 431 port { 432 ucam_out0: endpoint { 433 remote-endpoint = <&mipi_in_ucam0>; 434 data-lanes = <1 2>; 435 }; 436 }; 437 }; 438}; 439 440&i2c4 { 441 status = "okay"; 442}; 443 444&pcie_phy { 445 status = "okay"; 446}; 447 448&pcie0 { 449 status = "okay"; 450}; 451 452&vopb { 453 status = "okay"; 454 assigned-clocks = <&cru DCLK_VOP0_DIV>; 455 assigned-clock-parents = <&cru PLL_CPLL>; 456}; 457 458&vopb_mmu { 459 status = "okay"; 460}; 461 462&vopl { 463 status = "okay"; 464 assigned-clocks = <&cru DCLK_VOP1_DIV>; 465 assigned-clock-parents = <&cru PLL_VPLL>; 466}; 467 468&vopl_mmu { 469 status = "okay"; 470}; 471 472&pinctrl { 473 buttons { 474 pwrbtn: pwrbtn { 475 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 476 }; 477 }; 478 479 lcd-panel { 480 lcd_panel_reset: lcd-panel-reset { 481 rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; 482 }; 483 }; 484 485 hdmiin { 486 hdmiin_gpios: hdmiin-gpios { 487 rockchip,pins = 488 <2 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>, 489 <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>, 490 <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, 491 <2 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>, 492 <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>, 493 <2 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>, 494 <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 495 }; 496 }; 497}; 498