xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator-edp-avb.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include "rk3399-sapphire-excavator-edp.dtsi"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	model = "Rockchip RK3399 Excavator Board edp avb (Android)";
11*4882a593Smuzhiyun	compatible = "rockchip,android", "rockchip,rk3399-excavator-edp-avb", "rockchip,rk3399";
12*4882a593Smuzhiyun	chosen: chosen {
13*4882a593Smuzhiyun	bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init initrd=0x62000001,0x00800000 coherent_pool=1m";
14*4882a593Smuzhiyun	};
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	ext_cam_clk: external-camera-clock {
17*4882a593Smuzhiyun		compatible = "fixed-clock";
18*4882a593Smuzhiyun		clock-frequency = <27000000>;
19*4882a593Smuzhiyun		clock-output-names = "CLK_CAMERA_27MHZ";
20*4882a593Smuzhiyun		#clock-cells = <0>;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun&i2c1 {
25*4882a593Smuzhiyun	status = "okay";
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	/delete-node/ tc358749x@0f;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	tc35874x: tc35874x@0f {
30*4882a593Smuzhiyun		status = "disabled";
31*4882a593Smuzhiyun		reg = <0x0f>;
32*4882a593Smuzhiyun		compatible = "toshiba,tc358749";
33*4882a593Smuzhiyun		clocks = <&ext_cam_clk>;
34*4882a593Smuzhiyun		clock-names = "refclk";
35*4882a593Smuzhiyun		reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
36*4882a593Smuzhiyun		/* interrupt-parent = <&gpio2>; */
37*4882a593Smuzhiyun		/* interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; */
38*4882a593Smuzhiyun		pinctrl-names = "default";
39*4882a593Smuzhiyun		pinctrl-0 = <&tc35874x_gpios>;
40*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
41*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
42*4882a593Smuzhiyun		rockchip,camera-module-name = "TC358749XBG";
43*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "NC";
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		port {
46*4882a593Smuzhiyun			hdmiin_out0: endpoint {
47*4882a593Smuzhiyun				remote-endpoint = <&hdmi_to_mipi_in>;
48*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
49*4882a593Smuzhiyun				clock-noncontinuous;
50*4882a593Smuzhiyun				link-frequencies =
51*4882a593Smuzhiyun					/bits/ 64 <297000000>;
52*4882a593Smuzhiyun			};
53*4882a593Smuzhiyun		};
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun&mipi_dphy_rx0 {
58*4882a593Smuzhiyun	status = "okay";
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun	ports {
61*4882a593Smuzhiyun		#address-cells = <1>;
62*4882a593Smuzhiyun		#size-cells = <0>;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun		port@0 {
65*4882a593Smuzhiyun			reg = <0>;
66*4882a593Smuzhiyun			#address-cells = <1>;
67*4882a593Smuzhiyun			#size-cells = <0>;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
70*4882a593Smuzhiyun				reg = <1>;
71*4882a593Smuzhiyun				remote-endpoint = <&ucam_out0>;
72*4882a593Smuzhiyun				data-lanes = <1 2>;
73*4882a593Smuzhiyun			};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun			hdmi_to_mipi_in: endpoint@2 {
76*4882a593Smuzhiyun				reg = <2>;
77*4882a593Smuzhiyun				remote-endpoint = <&hdmiin_out0>;
78*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
79*4882a593Smuzhiyun			};
80*4882a593Smuzhiyun		};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun		port@1 {
83*4882a593Smuzhiyun			reg = <1>;
84*4882a593Smuzhiyun			#address-cells = <1>;
85*4882a593Smuzhiyun			#size-cells = <0>;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun			dphy_rx0_out: endpoint@0 {
88*4882a593Smuzhiyun				reg = <0>;
89*4882a593Smuzhiyun				remote-endpoint = <&isp0_mipi_in>;
90*4882a593Smuzhiyun			};
91*4882a593Smuzhiyun		};
92*4882a593Smuzhiyun	};
93*4882a593Smuzhiyun};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun&mipi_dphy_tx1rx1 {
96*4882a593Smuzhiyun	status = "disabled";
97*4882a593Smuzhiyun};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun&pinctrl {
100*4882a593Smuzhiyun	hdmiin {
101*4882a593Smuzhiyun		tc35874x_gpios: tc35874x_gpios {
102*4882a593Smuzhiyun			rockchip,pins =
103*4882a593Smuzhiyun				/* PWREN_3.3 */
104*4882a593Smuzhiyun				<2 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>,
105*4882a593Smuzhiyun				/* PWREN_1.2 */
106*4882a593Smuzhiyun				<2 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>,
107*4882a593Smuzhiyun				/* HDMIIN_RST */
108*4882a593Smuzhiyun				<2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>,
109*4882a593Smuzhiyun				/* HDMIIN_STBY */
110*4882a593Smuzhiyun				<2 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>,
111*4882a593Smuzhiyun				/* MIPI_RST */
112*4882a593Smuzhiyun				<2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>,
113*4882a593Smuzhiyun				/* CSI_CTL */
114*4882a593Smuzhiyun				<2 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>,
115*4882a593Smuzhiyun				/* HDMIIN_INT */
116*4882a593Smuzhiyun				<2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
117*4882a593Smuzhiyun		};
118*4882a593Smuzhiyun	};
119*4882a593Smuzhiyun};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun&rkisp1_0 {
122*4882a593Smuzhiyun	status = "okay";
123*4882a593Smuzhiyun};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun&rkisp1_1 {
126*4882a593Smuzhiyun	status = "disabled";
127*4882a593Smuzhiyun};
128*4882a593Smuzhiyun
129