xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include "dt-bindings/pwm/pwm.h"
10*4882a593Smuzhiyun#include "rk3399.dtsi"
11*4882a593Smuzhiyun#include "rk3399-opp.dtsi"
12*4882a593Smuzhiyun#include "rk3399-linux.dtsi"
13*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun/ {
16*4882a593Smuzhiyun	model = "Rockchip RK3399 Firefly Board (Linux Opensource)";
17*4882a593Smuzhiyun	compatible = "rockchip,rk3399-firefly-linux", "rockchip,rk3399";
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	backlight: backlight {
20*4882a593Smuzhiyun		status = "disabled";
21*4882a593Smuzhiyun		compatible = "pwm-backlight";
22*4882a593Smuzhiyun		pwms = <&pwm0 0 25000 0>;
23*4882a593Smuzhiyun		brightness-levels = <
24*4882a593Smuzhiyun			  0   1   2   3   4   5   6   7
25*4882a593Smuzhiyun			  8   9  10  11  12  13  14  15
26*4882a593Smuzhiyun			 16  17  18  19  20  21  22  23
27*4882a593Smuzhiyun			 24  25  26  27  28  29  30  31
28*4882a593Smuzhiyun			 32  33  34  35  36  37  38  39
29*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
30*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
31*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
32*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
33*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
34*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
35*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
36*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
37*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
38*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
39*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
40*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
41*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
42*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
43*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
44*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
45*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
46*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
47*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
48*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
49*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
50*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
51*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
52*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
53*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
54*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
55*4882a593Smuzhiyun			248 249 250 251 252 253 254 255>;
56*4882a593Smuzhiyun		default-brightness-level = <200>;
57*4882a593Smuzhiyun	};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun	clkin_gmac: external-gmac-clock {
60*4882a593Smuzhiyun		compatible = "fixed-clock";
61*4882a593Smuzhiyun		clock-frequency = <125000000>;
62*4882a593Smuzhiyun		clock-output-names = "clkin_gmac";
63*4882a593Smuzhiyun		#clock-cells = <0>;
64*4882a593Smuzhiyun	};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun	dw_hdmi_audio: dw-hdmi-audio {
67*4882a593Smuzhiyun		status = "disabled";
68*4882a593Smuzhiyun		compatible = "rockchip,dw-hdmi-audio";
69*4882a593Smuzhiyun		#sound-dai-cells = <0>;
70*4882a593Smuzhiyun	};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun	edp_panel: edp-panel {
73*4882a593Smuzhiyun		status = "disabled";
74*4882a593Smuzhiyun		compatible = "sharp,lcd-f402", "panel-simple";
75*4882a593Smuzhiyun		backlight = <&backlight>;
76*4882a593Smuzhiyun		power-supply = <&vcc_lcd>;
77*4882a593Smuzhiyun		enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
78*4882a593Smuzhiyun		pinctrl-names = "default";
79*4882a593Smuzhiyun		pinctrl-0 = <&lcd_panel_reset>;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun		ports {
82*4882a593Smuzhiyun			panel_in_edp: endpoint {
83*4882a593Smuzhiyun				remote-endpoint = <&edp_out_panel>;
84*4882a593Smuzhiyun			};
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun	};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun	gpio-keys {
89*4882a593Smuzhiyun		compatible = "gpio-keys";
90*4882a593Smuzhiyun		#address-cells = <1>;
91*4882a593Smuzhiyun		#size-cells = <0>;
92*4882a593Smuzhiyun		autorepeat;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun		pinctrl-names = "default";
95*4882a593Smuzhiyun		pinctrl-0 = <&pwrbtn>;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		button@0 {
98*4882a593Smuzhiyun			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
99*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
100*4882a593Smuzhiyun			label = "GPIO Key Power";
101*4882a593Smuzhiyun			linux,input-type = <1>;
102*4882a593Smuzhiyun			gpio-key,wakeup = <1>;
103*4882a593Smuzhiyun			debounce-interval = <100>;
104*4882a593Smuzhiyun		};
105*4882a593Smuzhiyun	};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun	rt5640-sound {
108*4882a593Smuzhiyun		compatible = "simple-audio-card";
109*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
110*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,rt5640-codec";
111*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
112*4882a593Smuzhiyun		simple-audio-card,widgets =
113*4882a593Smuzhiyun			"Microphone", "Mic Jack",
114*4882a593Smuzhiyun			"Headphone", "Headphone Jack";
115*4882a593Smuzhiyun		simple-audio-card,routing =
116*4882a593Smuzhiyun			"Mic Jack", "MICBIAS1",
117*4882a593Smuzhiyun			"IN1P", "Mic Jack",
118*4882a593Smuzhiyun			"Headphone Jack", "HPOL",
119*4882a593Smuzhiyun			"Headphone Jack", "HPOR";
120*4882a593Smuzhiyun		simple-audio-card,cpu {
121*4882a593Smuzhiyun			sound-dai = <&i2s1>;
122*4882a593Smuzhiyun		};
123*4882a593Smuzhiyun		simple-audio-card,codec {
124*4882a593Smuzhiyun			sound-dai = <&rt5640>;
125*4882a593Smuzhiyun		};
126*4882a593Smuzhiyun	};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun	hdmi_sound: hdmi-sound {
129*4882a593Smuzhiyun		status = "disabled";
130*4882a593Smuzhiyun		compatible = "simple-audio-card";
131*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
132*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
133*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,hdmi";
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun		simple-audio-card,cpu {
136*4882a593Smuzhiyun			sound-dai = <&i2s2>;
137*4882a593Smuzhiyun		};
138*4882a593Smuzhiyun		simple-audio-card,codec {
139*4882a593Smuzhiyun			sound-dai = <&dw_hdmi_audio>;
140*4882a593Smuzhiyun		};
141*4882a593Smuzhiyun	};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun	hdmi_codec: hdmi-codec {
144*4882a593Smuzhiyun		compatible = "simple-audio-card";
145*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
146*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
147*4882a593Smuzhiyun		simple-audio-card,name = "HDMI-CODEC";
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun		simple-audio-card,cpu {
150*4882a593Smuzhiyun			sound-dai = <&i2s2>;
151*4882a593Smuzhiyun		};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun		simple-audio-card,codec {
154*4882a593Smuzhiyun			sound-dai = <&hdmi>;
155*4882a593Smuzhiyun		};
156*4882a593Smuzhiyun	};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun	spdif-sound {
159*4882a593Smuzhiyun		status = "okay";
160*4882a593Smuzhiyun		compatible = "simple-audio-card";
161*4882a593Smuzhiyun		simple-audio-card,name = "ROCKCHIP,SPDIF";
162*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <128>;
163*4882a593Smuzhiyun		simple-audio-card,cpu {
164*4882a593Smuzhiyun			sound-dai = <&spdif>;
165*4882a593Smuzhiyun		};
166*4882a593Smuzhiyun		simple-audio-card,codec {
167*4882a593Smuzhiyun			sound-dai = <&spdif_out>;
168*4882a593Smuzhiyun		};
169*4882a593Smuzhiyun	};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun	spdif_out: spdif-out {
172*4882a593Smuzhiyun		status = "okay";
173*4882a593Smuzhiyun		compatible = "linux,spdif-dit";
174*4882a593Smuzhiyun		#sound-dai-cells = <0>;
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
178*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
179*4882a593Smuzhiyun		clocks = <&rk808 1>;
180*4882a593Smuzhiyun		clock-names = "ext_clock";
181*4882a593Smuzhiyun		pinctrl-names = "default";
182*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun		/*
185*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
186*4882a593Smuzhiyun		 * on the actual card populated):
187*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
188*4882a593Smuzhiyun		 * - PDN (power down when low)
189*4882a593Smuzhiyun		 */
190*4882a593Smuzhiyun		reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
191*4882a593Smuzhiyun	};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun	vcc3v3_pcie: vcc3v3-pcie-regulator {
194*4882a593Smuzhiyun		compatible = "regulator-fixed";
195*4882a593Smuzhiyun		enable-active-high;
196*4882a593Smuzhiyun		regulator-always-on;
197*4882a593Smuzhiyun		regulator-boot-on;
198*4882a593Smuzhiyun		gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
199*4882a593Smuzhiyun		pinctrl-names = "default";
200*4882a593Smuzhiyun		pinctrl-0 = <&pcie_drv>;
201*4882a593Smuzhiyun		regulator-name = "vcc3v3_pcie";
202*4882a593Smuzhiyun	};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun	vcc3v3_sys: vcc3v3-sys {
205*4882a593Smuzhiyun		compatible = "regulator-fixed";
206*4882a593Smuzhiyun		regulator-name = "vcc3v3_sys";
207*4882a593Smuzhiyun		regulator-always-on;
208*4882a593Smuzhiyun		regulator-boot-on;
209*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
210*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
211*4882a593Smuzhiyun	};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host-regulator {
214*4882a593Smuzhiyun		compatible = "regulator-fixed";
215*4882a593Smuzhiyun		enable-active-high;
216*4882a593Smuzhiyun		gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
217*4882a593Smuzhiyun		pinctrl-names = "default";
218*4882a593Smuzhiyun		pinctrl-0 = <&host_vbus_drv>;
219*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
220*4882a593Smuzhiyun		regulator-always-on;
221*4882a593Smuzhiyun	};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun	vcc5v0_sys: vcc5v0-sys {
224*4882a593Smuzhiyun		compatible = "regulator-fixed";
225*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
226*4882a593Smuzhiyun		regulator-always-on;
227*4882a593Smuzhiyun		regulator-boot-on;
228*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
229*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
230*4882a593Smuzhiyun	};
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun	vcc_phy: vcc-phy-regulator {
233*4882a593Smuzhiyun		compatible = "regulator-fixed";
234*4882a593Smuzhiyun		regulator-name = "vcc_phy";
235*4882a593Smuzhiyun		regulator-always-on;
236*4882a593Smuzhiyun		regulator-boot-on;
237*4882a593Smuzhiyun	};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun	vdd_log: vdd-log {
240*4882a593Smuzhiyun		compatible = "pwm-regulator";
241*4882a593Smuzhiyun		pwms = <&pwm2 0 25000 1>;
242*4882a593Smuzhiyun		regulator-name = "vdd_log";
243*4882a593Smuzhiyun		regulator-min-microvolt = <800000>;
244*4882a593Smuzhiyun		/*
245*4882a593Smuzhiyun		 * the firefly hardware using 3.0 v as APIO2_VDD
246*4882a593Smuzhiyun		 * voltage, but the pwm divider resistance is designed
247*4882a593Smuzhiyun		 * based on hardware which the APIO2_VDD is 1.8v, so we
248*4882a593Smuzhiyun		 * need to change the regulator-max-microvolt from 1.4v
249*4882a593Smuzhiyun		 * to 1.0v, so the pwm can output 0.9v voltage.
250*4882a593Smuzhiyun		 */
251*4882a593Smuzhiyun		regulator-max-microvolt = <1000000>;
252*4882a593Smuzhiyun		regulator-always-on;
253*4882a593Smuzhiyun		regulator-boot-on;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun		/* for rockchip boot on */
256*4882a593Smuzhiyun		rockchip,pwm_id= <2>;
257*4882a593Smuzhiyun		rockchip,pwm_voltage = <900000>;
258*4882a593Smuzhiyun	};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun	vccadc_ref: vccadc-ref {
261*4882a593Smuzhiyun		compatible = "regulator-fixed";
262*4882a593Smuzhiyun		regulator-name = "vcc1v8_sys";
263*4882a593Smuzhiyun		regulator-always-on;
264*4882a593Smuzhiyun		regulator-boot-on;
265*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
266*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
267*4882a593Smuzhiyun	};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun	vcc_lcd: vcc-lcd-regulator {
270*4882a593Smuzhiyun		compatible = "regulator-fixed";
271*4882a593Smuzhiyun		regulator-always-on;
272*4882a593Smuzhiyun		regulator-boot-on;
273*4882a593Smuzhiyun		enable-active-high;
274*4882a593Smuzhiyun		gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
275*4882a593Smuzhiyun		pinctrl-names = "default";
276*4882a593Smuzhiyun		pinctrl-0 = <&lcd_en>;
277*4882a593Smuzhiyun		regulator-name = "vcc_lcd";
278*4882a593Smuzhiyun	};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun	xin32k: xin32k {
281*4882a593Smuzhiyun		compatible = "fixed-clock";
282*4882a593Smuzhiyun		clock-frequency = <32768>;
283*4882a593Smuzhiyun		clock-output-names = "xin32k";
284*4882a593Smuzhiyun		#clock-cells = <0>;
285*4882a593Smuzhiyun	};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun	wireless-wlan {
288*4882a593Smuzhiyun		compatible = "wlan-platdata";
289*4882a593Smuzhiyun		rockchip,grf = <&grf>;
290*4882a593Smuzhiyun		wifi_chip_type = "ap6354";
291*4882a593Smuzhiyun		sdio_vref = <1800>;
292*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
293*4882a593Smuzhiyun		status = "okay";
294*4882a593Smuzhiyun	};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun	wireless-bluetooth {
297*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
298*4882a593Smuzhiyun		//wifi-bt-power-toggle;
299*4882a593Smuzhiyun		uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */
300*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
301*4882a593Smuzhiyun		pinctrl-0 = <&uart0_rts>;
302*4882a593Smuzhiyun		pinctrl-1 = <&uart0_gpios>;
303*4882a593Smuzhiyun		//BT,power_gpio  = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */
304*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */
305*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */
306*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */
307*4882a593Smuzhiyun		status = "okay";
308*4882a593Smuzhiyun	};
309*4882a593Smuzhiyun};
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun&cpu_l0 {
312*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
313*4882a593Smuzhiyun};
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun&cpu_l1 {
316*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
317*4882a593Smuzhiyun};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun&cpu_l2 {
320*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
321*4882a593Smuzhiyun};
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun&cpu_l3 {
324*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
325*4882a593Smuzhiyun};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun&cpu_b0 {
328*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_b>;
329*4882a593Smuzhiyun};
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun&cpu_b1 {
332*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_b>;
333*4882a593Smuzhiyun};
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun&display_subsystem {
336*4882a593Smuzhiyun	status = "okay";
337*4882a593Smuzhiyun};
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun&edp {
340*4882a593Smuzhiyun	status = "disabled";
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun	ports {
343*4882a593Smuzhiyun		edp_out: port@1 {
344*4882a593Smuzhiyun			reg = <1>;
345*4882a593Smuzhiyun			#address-cells = <1>;
346*4882a593Smuzhiyun			#size-cells = <0>;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun			edp_out_panel: endpoint@0 {
349*4882a593Smuzhiyun				reg = <0>;
350*4882a593Smuzhiyun				remote-endpoint = <&panel_in_edp>;
351*4882a593Smuzhiyun			};
352*4882a593Smuzhiyun		};
353*4882a593Smuzhiyun	};
354*4882a593Smuzhiyun};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun&emmc_phy {
357*4882a593Smuzhiyun	status = "okay";
358*4882a593Smuzhiyun};
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun&gmac {
361*4882a593Smuzhiyun	phy-supply = <&vcc_phy>;
362*4882a593Smuzhiyun	phy-mode = "rgmii";
363*4882a593Smuzhiyun	clock_in_out = "input";
364*4882a593Smuzhiyun	snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
365*4882a593Smuzhiyun	snps,reset-active-low;
366*4882a593Smuzhiyun	snps,reset-delays-us = <0 10000 50000>;
367*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_RMII_SRC>;
368*4882a593Smuzhiyun	assigned-clock-parents = <&clkin_gmac>;
369*4882a593Smuzhiyun	pinctrl-names = "default";
370*4882a593Smuzhiyun	pinctrl-0 = <&rgmii_pins>;
371*4882a593Smuzhiyun	tx_delay = <0x28>;
372*4882a593Smuzhiyun	rx_delay = <0x11>;
373*4882a593Smuzhiyun	status = "okay";
374*4882a593Smuzhiyun};
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun&gpu {
377*4882a593Smuzhiyun	status = "okay";
378*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
379*4882a593Smuzhiyun};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun&hdmi {
382*4882a593Smuzhiyun	#address-cells = <1>;
383*4882a593Smuzhiyun	#size-cells = <0>;
384*4882a593Smuzhiyun	#sound-dai-cells = <0>;
385*4882a593Smuzhiyun	status = "okay";
386*4882a593Smuzhiyun};
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun&i2c0 {
389*4882a593Smuzhiyun	status = "okay";
390*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <168>;
391*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <4>;
392*4882a593Smuzhiyun	clock-frequency = <400000>;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun	vdd_cpu_b: syr827@40 {
395*4882a593Smuzhiyun		compatible = "silergy,syr827";
396*4882a593Smuzhiyun		reg = <0x40>;
397*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
398*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
399*4882a593Smuzhiyun		regulator-name = "vdd_cpu_b";
400*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
401*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
402*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
403*4882a593Smuzhiyun		vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
404*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
405*4882a593Smuzhiyun		regulator-always-on;
406*4882a593Smuzhiyun		regulator-boot-on;
407*4882a593Smuzhiyun		regulator-initial-state = <3>;
408*4882a593Smuzhiyun			regulator-state-mem {
409*4882a593Smuzhiyun			regulator-off-in-suspend;
410*4882a593Smuzhiyun		};
411*4882a593Smuzhiyun	};
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun	vdd_gpu: syr828@41 {
414*4882a593Smuzhiyun		compatible = "silergy,syr828";
415*4882a593Smuzhiyun		reg = <0x41>;
416*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
417*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
418*4882a593Smuzhiyun		regulator-name = "vdd_gpu";
419*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
420*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
421*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
422*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
423*4882a593Smuzhiyun		regulator-always-on;
424*4882a593Smuzhiyun		regulator-boot-on;
425*4882a593Smuzhiyun		regulator-initial-state = <3>;
426*4882a593Smuzhiyun			regulator-state-mem {
427*4882a593Smuzhiyun			regulator-off-in-suspend;
428*4882a593Smuzhiyun		};
429*4882a593Smuzhiyun	};
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun	rk808: pmic@1b {
432*4882a593Smuzhiyun		compatible = "rockchip,rk808";
433*4882a593Smuzhiyun		reg = <0x1b>;
434*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
435*4882a593Smuzhiyun		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
436*4882a593Smuzhiyun		pinctrl-names = "default";
437*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
438*4882a593Smuzhiyun		rockchip,system-power-controller;
439*4882a593Smuzhiyun		wakeup-source;
440*4882a593Smuzhiyun		#clock-cells = <1>;
441*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun		vcc1-supply = <&vcc3v3_sys>;
444*4882a593Smuzhiyun		vcc2-supply = <&vcc3v3_sys>;
445*4882a593Smuzhiyun		vcc3-supply = <&vcc3v3_sys>;
446*4882a593Smuzhiyun		vcc4-supply = <&vcc3v3_sys>;
447*4882a593Smuzhiyun		vcc6-supply = <&vcc3v3_sys>;
448*4882a593Smuzhiyun		vcc7-supply = <&vcc3v3_sys>;
449*4882a593Smuzhiyun		vcc8-supply = <&vcc3v3_sys>;
450*4882a593Smuzhiyun		vcc9-supply = <&vcc3v3_sys>;
451*4882a593Smuzhiyun		vcc10-supply = <&vcc3v3_sys>;
452*4882a593Smuzhiyun		vcc11-supply = <&vcc3v3_sys>;
453*4882a593Smuzhiyun		vcc12-supply = <&vcc3v3_sys>;
454*4882a593Smuzhiyun		vddio-supply = <&vcc1v8_pmu>;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun		regulators {
457*4882a593Smuzhiyun			vdd_center: DCDC_REG1 {
458*4882a593Smuzhiyun				regulator-always-on;
459*4882a593Smuzhiyun				regulator-boot-on;
460*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
461*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
462*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
463*4882a593Smuzhiyun				regulator-name = "vdd_center";
464*4882a593Smuzhiyun				regulator-state-mem {
465*4882a593Smuzhiyun					regulator-off-in-suspend;
466*4882a593Smuzhiyun				};
467*4882a593Smuzhiyun			};
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun			vdd_cpu_l: DCDC_REG2 {
470*4882a593Smuzhiyun				regulator-always-on;
471*4882a593Smuzhiyun				regulator-boot-on;
472*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
473*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
474*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
475*4882a593Smuzhiyun				regulator-name = "vdd_cpu_l";
476*4882a593Smuzhiyun				regulator-state-mem {
477*4882a593Smuzhiyun					regulator-off-in-suspend;
478*4882a593Smuzhiyun				};
479*4882a593Smuzhiyun			};
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
482*4882a593Smuzhiyun				regulator-always-on;
483*4882a593Smuzhiyun				regulator-boot-on;
484*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
485*4882a593Smuzhiyun				regulator-state-mem {
486*4882a593Smuzhiyun					regulator-on-in-suspend;
487*4882a593Smuzhiyun				};
488*4882a593Smuzhiyun			};
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun			vcc_1v8: DCDC_REG4 {
491*4882a593Smuzhiyun				regulator-always-on;
492*4882a593Smuzhiyun				regulator-boot-on;
493*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
494*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
495*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
496*4882a593Smuzhiyun				regulator-state-mem {
497*4882a593Smuzhiyun					regulator-on-in-suspend;
498*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
499*4882a593Smuzhiyun				};
500*4882a593Smuzhiyun			};
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun			vcc1v8_dvp: LDO_REG1 {
503*4882a593Smuzhiyun				regulator-always-on;
504*4882a593Smuzhiyun				regulator-boot-on;
505*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
506*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
507*4882a593Smuzhiyun				regulator-name = "vcc1v8_dvp";
508*4882a593Smuzhiyun				regulator-state-mem {
509*4882a593Smuzhiyun					regulator-off-in-suspend;
510*4882a593Smuzhiyun				};
511*4882a593Smuzhiyun			};
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun			vcc3v0_tp: LDO_REG2 {
514*4882a593Smuzhiyun				regulator-always-on;
515*4882a593Smuzhiyun				regulator-boot-on;
516*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
517*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
518*4882a593Smuzhiyun				regulator-name = "vcc3v0_tp";
519*4882a593Smuzhiyun				regulator-state-mem {
520*4882a593Smuzhiyun					regulator-off-in-suspend;
521*4882a593Smuzhiyun				};
522*4882a593Smuzhiyun			};
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun			vcc1v8_pmu: LDO_REG3 {
525*4882a593Smuzhiyun				regulator-always-on;
526*4882a593Smuzhiyun				regulator-boot-on;
527*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
528*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
529*4882a593Smuzhiyun				regulator-name = "vcc1v8_pmu";
530*4882a593Smuzhiyun				regulator-state-mem {
531*4882a593Smuzhiyun					regulator-on-in-suspend;
532*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
533*4882a593Smuzhiyun				};
534*4882a593Smuzhiyun			};
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun			vcc_sd: LDO_REG4 {
537*4882a593Smuzhiyun				regulator-always-on;
538*4882a593Smuzhiyun				regulator-boot-on;
539*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
540*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
541*4882a593Smuzhiyun				regulator-name = "vcc_sd";
542*4882a593Smuzhiyun				regulator-state-mem {
543*4882a593Smuzhiyun					regulator-on-in-suspend;
544*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
545*4882a593Smuzhiyun				};
546*4882a593Smuzhiyun			};
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun			vcca3v0_codec: LDO_REG5 {
549*4882a593Smuzhiyun				regulator-always-on;
550*4882a593Smuzhiyun				regulator-boot-on;
551*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
552*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
553*4882a593Smuzhiyun				regulator-name = "vcca3v0_codec";
554*4882a593Smuzhiyun				regulator-state-mem {
555*4882a593Smuzhiyun					regulator-off-in-suspend;
556*4882a593Smuzhiyun				};
557*4882a593Smuzhiyun			};
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun			vcc_1v5: LDO_REG6 {
560*4882a593Smuzhiyun				regulator-always-on;
561*4882a593Smuzhiyun				regulator-boot-on;
562*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
563*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
564*4882a593Smuzhiyun				regulator-name = "vcc_1v5";
565*4882a593Smuzhiyun				regulator-state-mem {
566*4882a593Smuzhiyun					regulator-on-in-suspend;
567*4882a593Smuzhiyun					regulator-suspend-microvolt = <1500000>;
568*4882a593Smuzhiyun				};
569*4882a593Smuzhiyun			};
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun			vcca1v8_codec: LDO_REG7 {
572*4882a593Smuzhiyun				regulator-always-on;
573*4882a593Smuzhiyun				regulator-boot-on;
574*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
575*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
576*4882a593Smuzhiyun				regulator-name = "vcca1v8_codec";
577*4882a593Smuzhiyun				regulator-state-mem {
578*4882a593Smuzhiyun					regulator-off-in-suspend;
579*4882a593Smuzhiyun				};
580*4882a593Smuzhiyun			};
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun			vcc_3v0: LDO_REG8 {
583*4882a593Smuzhiyun				regulator-always-on;
584*4882a593Smuzhiyun				regulator-boot-on;
585*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
586*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
587*4882a593Smuzhiyun				regulator-name = "vcc_3v0";
588*4882a593Smuzhiyun				regulator-state-mem {
589*4882a593Smuzhiyun					regulator-on-in-suspend;
590*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
591*4882a593Smuzhiyun				};
592*4882a593Smuzhiyun			};
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun			vcc3v3_s3: SWITCH_REG1 {
595*4882a593Smuzhiyun				regulator-always-on;
596*4882a593Smuzhiyun				regulator-boot-on;
597*4882a593Smuzhiyun				regulator-name = "vcc3v3_s3";
598*4882a593Smuzhiyun				regulator-state-mem {
599*4882a593Smuzhiyun					regulator-off-in-suspend;
600*4882a593Smuzhiyun				};
601*4882a593Smuzhiyun			};
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun			vcc3v3_s0: SWITCH_REG2 {
604*4882a593Smuzhiyun				regulator-always-on;
605*4882a593Smuzhiyun				regulator-boot-on;
606*4882a593Smuzhiyun				regulator-name = "vcc3v3_s0";
607*4882a593Smuzhiyun				regulator-state-mem {
608*4882a593Smuzhiyun					regulator-off-in-suspend;
609*4882a593Smuzhiyun				};
610*4882a593Smuzhiyun			};
611*4882a593Smuzhiyun		};
612*4882a593Smuzhiyun	};
613*4882a593Smuzhiyun};
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun&i2c1 {
616*4882a593Smuzhiyun	status = "okay";
617*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <300>;
618*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <15>;
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun	rt5640: rt5640@1c {
621*4882a593Smuzhiyun		#sound-dai-cells = <0>;
622*4882a593Smuzhiyun		compatible = "realtek,rt5640";
623*4882a593Smuzhiyun		reg = <0x1c>;
624*4882a593Smuzhiyun		clocks = <&cru SCLK_I2S_8CH_OUT>;
625*4882a593Smuzhiyun		clock-names = "mclk";
626*4882a593Smuzhiyun		realtek,in1-differential;
627*4882a593Smuzhiyun		pinctrl-names = "default";
628*4882a593Smuzhiyun		pinctrl-0 = <&rt5640_hpcon &i2s_8ch_mclk>;
629*4882a593Smuzhiyun		hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
630*4882a593Smuzhiyun		//hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
631*4882a593Smuzhiyun		io-channels = <&saradc 4>;
632*4882a593Smuzhiyun		hp-det-adc-value = <500>;
633*4882a593Smuzhiyun	};
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun	camera0: ov13850@10 {
636*4882a593Smuzhiyun		status = "okay";
637*4882a593Smuzhiyun		compatible = "omnivision,ov13850-v4l2-i2c-subdev";
638*4882a593Smuzhiyun		reg = < 0x10 >;
639*4882a593Smuzhiyun		device_type = "v4l2-i2c-subdev";
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun		clocks = <&cru SCLK_CIF_OUT>;
642*4882a593Smuzhiyun		clock-names = "clk_cif_out";
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun		pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep";
645*4882a593Smuzhiyun		pinctrl-0 = <&cam0_default_pins>;
646*4882a593Smuzhiyun		pinctrl-1 = <&cam0_sleep_pins>;
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun		rockchip,pd-gpio = <&gpio2 12 GPIO_ACTIVE_LOW>;
649*4882a593Smuzhiyun		rockchip,pwr-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
650*4882a593Smuzhiyun		rockchip,pwr-2nd-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
651*4882a593Smuzhiyun		rockchip,rst-gpio = <&gpio0 8 GPIO_ACTIVE_LOW>;
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun		rockchip,camera-module-mclk-name = "clk_cif_out";
654*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
655*4882a593Smuzhiyun		rockchip,camera-module-name = "cmk-cb0695-fv1";
656*4882a593Smuzhiyun		rockchip,camera-module-len-name = "lg9569a2";
657*4882a593Smuzhiyun		rockchip,camera-module-fov-h = "66.0";
658*4882a593Smuzhiyun		rockchip,camera-module-fov-v = "50.1";
659*4882a593Smuzhiyun		rockchip,camera-module-orientation = <0>;
660*4882a593Smuzhiyun		rockchip,camera-module-iq-flip = <0>;
661*4882a593Smuzhiyun		rockchip,camera-module-iq-mirror = <0>;
662*4882a593Smuzhiyun		rockchip,camera-module-flip = <1>;
663*4882a593Smuzhiyun		rockchip,camera-module-mirror = <0>;
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun		rockchip,camera-module-defrect0 = <2112 1568 0 0 2112 1568>;
666*4882a593Smuzhiyun		rockchip,camera-module-defrect1 = <4224 3136 0 0 4224 3136>;
667*4882a593Smuzhiyun		rockchip,camera-module-defrect3 = <3264 2448 0 0 3264 2448>;
668*4882a593Smuzhiyun		rockchip,camera-module-flash-support = <0>;
669*4882a593Smuzhiyun		rockchip,camera-module-mipi-dphy-index = <0>;
670*4882a593Smuzhiyun	};
671*4882a593Smuzhiyun};
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun&i2c3 {
674*4882a593Smuzhiyun	status = "okay";
675*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <450>;
676*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <15>;
677*4882a593Smuzhiyun};
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun&i2c4 {
680*4882a593Smuzhiyun	status = "okay";
681*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <600>;
682*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <20>;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun	fusb0: fusb30x@22 {
685*4882a593Smuzhiyun		compatible = "fairchild,fusb302";
686*4882a593Smuzhiyun		reg = <0x22>;
687*4882a593Smuzhiyun		pinctrl-names = "default";
688*4882a593Smuzhiyun		pinctrl-0 = <&fusb0_int>;
689*4882a593Smuzhiyun		int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
690*4882a593Smuzhiyun		vbus-5v-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
691*4882a593Smuzhiyun		status = "okay";
692*4882a593Smuzhiyun	};
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun	gsl3680: gsl3680@41 {
695*4882a593Smuzhiyun		status = "disabled";
696*4882a593Smuzhiyun		compatible = "gslX680-pad";
697*4882a593Smuzhiyun		reg = <0x41>;
698*4882a593Smuzhiyun		screen_max_x = <1536>;
699*4882a593Smuzhiyun		screen_max_y = <2048>;
700*4882a593Smuzhiyun		touch-gpio = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
701*4882a593Smuzhiyun		reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
702*4882a593Smuzhiyun	};
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun	mpu6050: mpu@68 {
705*4882a593Smuzhiyun		status = "disabled";
706*4882a593Smuzhiyun		compatible = "invensense,mpu6050";
707*4882a593Smuzhiyun		reg = <0x68>;
708*4882a593Smuzhiyun		mpu-int_config = <0x10>;
709*4882a593Smuzhiyun		mpu-level_shifter = <0>;
710*4882a593Smuzhiyun		mpu-orientation = <0 1 0 1 0 0 0 0 1>;
711*4882a593Smuzhiyun		orientation-x= <1>;
712*4882a593Smuzhiyun		orientation-y= <1>;
713*4882a593Smuzhiyun		orientation-z= <1>;
714*4882a593Smuzhiyun		irq-gpio = <&gpio1 4 IRQ_TYPE_LEVEL_LOW>;
715*4882a593Smuzhiyun		mpu-debug = <1>;
716*4882a593Smuzhiyun	};
717*4882a593Smuzhiyun};
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun&i2s0 {
720*4882a593Smuzhiyun	status = "okay";
721*4882a593Smuzhiyun	rockchip,i2s-broken-burst-len;
722*4882a593Smuzhiyun	rockchip,playback-channels = <8>;
723*4882a593Smuzhiyun	rockchip,capture-channels = <8>;
724*4882a593Smuzhiyun	#sound-dai-cells = <0>;
725*4882a593Smuzhiyun};
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun&i2s1 {
728*4882a593Smuzhiyun	status = "okay";
729*4882a593Smuzhiyun	rockchip,i2s-broken-burst-len;
730*4882a593Smuzhiyun	rockchip,playback-channels = <2>;
731*4882a593Smuzhiyun	rockchip,capture-channels = <2>;
732*4882a593Smuzhiyun	#sound-dai-cells = <0>;
733*4882a593Smuzhiyun};
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun&i2s2 {
736*4882a593Smuzhiyun	#sound-dai-cells = <0>;
737*4882a593Smuzhiyun	status = "okay";
738*4882a593Smuzhiyun};
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun&io_domains {
741*4882a593Smuzhiyun	status = "okay";
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun	bt656-supply = <&vcc1v8_dvp>;		/* bt656_gpio2ab_ms */
744*4882a593Smuzhiyun	audio-supply = <&vcca1v8_codec>;	/* audio_gpio3d4a_ms */
745*4882a593Smuzhiyun	sdmmc-supply = <&vcc_sd>;		/* sdmmc_gpio4b_ms */
746*4882a593Smuzhiyun	gpio1830-supply = <&vcc_3v0>;		/* gpio1833_gpio4cd_ms */
747*4882a593Smuzhiyun};
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun&pcie_phy {
750*4882a593Smuzhiyun	status = "okay";
751*4882a593Smuzhiyun};
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun&pcie0 {
754*4882a593Smuzhiyun	ep-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
755*4882a593Smuzhiyun	num-lanes = <4>;
756*4882a593Smuzhiyun	pinctrl-names = "default";
757*4882a593Smuzhiyun	pinctrl-0 = <&pcie_clkreqn_cpm>;
758*4882a593Smuzhiyun	status = "okay";
759*4882a593Smuzhiyun};
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun&pmu_io_domains {
762*4882a593Smuzhiyun	status = "okay";
763*4882a593Smuzhiyun	pmu1830-supply = <&vcc_3v0>;
764*4882a593Smuzhiyun};
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun&pinctrl {
767*4882a593Smuzhiyun	buttons {
768*4882a593Smuzhiyun		pwrbtn: pwrbtn {
769*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
770*4882a593Smuzhiyun		};
771*4882a593Smuzhiyun	};
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun	lcd-panel {
774*4882a593Smuzhiyun		lcd_panel_reset: lcd-panel-reset {
775*4882a593Smuzhiyun			rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
776*4882a593Smuzhiyun		};
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun		lcd_en: lcd-en {
779*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
780*4882a593Smuzhiyun		};
781*4882a593Smuzhiyun	};
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun	pcie {
784*4882a593Smuzhiyun		pcie_drv: pcie-drv {
785*4882a593Smuzhiyun			rockchip,pins =
786*4882a593Smuzhiyun				<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
787*4882a593Smuzhiyun			};
788*4882a593Smuzhiyun			pcie_3g_drv: pcie-3g-drv {
789*4882a593Smuzhiyun			rockchip,pins =
790*4882a593Smuzhiyun				<0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
791*4882a593Smuzhiyun		};
792*4882a593Smuzhiyun	};
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun	pmic {
795*4882a593Smuzhiyun		vsel1_gpio: vsel1-gpio {
796*4882a593Smuzhiyun			rockchip,pins =
797*4882a593Smuzhiyun				<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
798*4882a593Smuzhiyun		};
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun		vsel2_gpio: vsel2-gpio {
801*4882a593Smuzhiyun			rockchip,pins =
802*4882a593Smuzhiyun			<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
803*4882a593Smuzhiyun		};
804*4882a593Smuzhiyun	};
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun	sdio-pwrseq {
807*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
808*4882a593Smuzhiyun			rockchip,pins =
809*4882a593Smuzhiyun				<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
810*4882a593Smuzhiyun		};
811*4882a593Smuzhiyun	};
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun	wireless-bluetooth {
814*4882a593Smuzhiyun		uart0_gpios: uart0-gpios {
815*4882a593Smuzhiyun			rockchip,pins =
816*4882a593Smuzhiyun				<2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
817*4882a593Smuzhiyun		};
818*4882a593Smuzhiyun	};
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun	rt5640 {
821*4882a593Smuzhiyun		rt5640_hpcon: rt5640-hpcon {
822*4882a593Smuzhiyun			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
823*4882a593Smuzhiyun		};
824*4882a593Smuzhiyun	};
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun	pmic {
827*4882a593Smuzhiyun		pmic_int_l: pmic-int-l {
828*4882a593Smuzhiyun			rockchip,pins =
829*4882a593Smuzhiyun				<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
830*4882a593Smuzhiyun		};
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun		pmic_dvs2: pmic-dvs2 {
833*4882a593Smuzhiyun			rockchip,pins =
834*4882a593Smuzhiyun				<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
835*4882a593Smuzhiyun		};
836*4882a593Smuzhiyun	};
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun	usb2 {
839*4882a593Smuzhiyun		host_vbus_drv: host-vbus-drv {
840*4882a593Smuzhiyun			rockchip,pins =
841*4882a593Smuzhiyun				<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
842*4882a593Smuzhiyun		};
843*4882a593Smuzhiyun	};
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun	fusb30x {
846*4882a593Smuzhiyun		fusb0_int: fusb0-int {
847*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
848*4882a593Smuzhiyun		};
849*4882a593Smuzhiyun	};
850*4882a593Smuzhiyun};
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun&pwm0 {
853*4882a593Smuzhiyun	status = "okay";
854*4882a593Smuzhiyun};
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun&pwm2 {
857*4882a593Smuzhiyun	status = "okay";
858*4882a593Smuzhiyun	pinctrl-names = "active";
859*4882a593Smuzhiyun	pinctrl-0 = <&pwm2_pin_pull_down>;
860*4882a593Smuzhiyun};
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun&rockchip_suspend {
863*4882a593Smuzhiyun	rockchip,power-ctrl =
864*4882a593Smuzhiyun		<&gpio1 18 GPIO_ACTIVE_LOW>,
865*4882a593Smuzhiyun		<&gpio1 14 GPIO_ACTIVE_HIGH>;
866*4882a593Smuzhiyun};
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun&route_edp {
869*4882a593Smuzhiyun	status = "disabled";
870*4882a593Smuzhiyun};
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun&saradc {
873*4882a593Smuzhiyun	status = "okay";
874*4882a593Smuzhiyun	vref-supply = <&vccadc_ref>;
875*4882a593Smuzhiyun};
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun&sdhci {
878*4882a593Smuzhiyun	bus-width = <8>;
879*4882a593Smuzhiyun	keep-power-in-suspend;
880*4882a593Smuzhiyun	mmc-hs400-1_8v;
881*4882a593Smuzhiyun	mmc-hs400-enhanced-strobe;
882*4882a593Smuzhiyun	non-removable;
883*4882a593Smuzhiyun	status = "okay";
884*4882a593Smuzhiyun	no-sdio;
885*4882a593Smuzhiyun	no-sd;
886*4882a593Smuzhiyun};
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun&sdmmc {
889*4882a593Smuzhiyun	max-frequency = <150000000>;
890*4882a593Smuzhiyun	no-sdio;
891*4882a593Smuzhiyun	no-mmc;
892*4882a593Smuzhiyun	bus-width = <4>;
893*4882a593Smuzhiyun	cap-mmc-highspeed;
894*4882a593Smuzhiyun	cap-sd-highspeed;
895*4882a593Smuzhiyun	disable-wp;
896*4882a593Smuzhiyun	num-slots = <1>;
897*4882a593Smuzhiyun	vqmmc-supply = <&vcc_sd>;
898*4882a593Smuzhiyun	pinctrl-names = "default";
899*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
900*4882a593Smuzhiyun	status = "okay";
901*4882a593Smuzhiyun};
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun&sdio0 {
904*4882a593Smuzhiyun	max-frequency = <50000000>;
905*4882a593Smuzhiyun	no-sd;
906*4882a593Smuzhiyun	no-mmc;
907*4882a593Smuzhiyun	bus-width = <4>;
908*4882a593Smuzhiyun	disable-wp;
909*4882a593Smuzhiyun	cap-sd-highspeed;
910*4882a593Smuzhiyun	keep-power-in-suspend;
911*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
912*4882a593Smuzhiyun	non-removable;
913*4882a593Smuzhiyun	num-slots = <1>;
914*4882a593Smuzhiyun	pinctrl-names = "default";
915*4882a593Smuzhiyun	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
916*4882a593Smuzhiyun	sd-uhs-sdr104;
917*4882a593Smuzhiyun	status = "okay";
918*4882a593Smuzhiyun};
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun&spdif {
921*4882a593Smuzhiyun	status = "okay";
922*4882a593Smuzhiyun	pinctrl-0 = <&spdif_bus_1>;
923*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <450>;
924*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <15>;
925*4882a593Smuzhiyun	#sound-dai-cells = <0>;
926*4882a593Smuzhiyun};
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun&tcphy0 {
929*4882a593Smuzhiyun	extcon = <&fusb0>;
930*4882a593Smuzhiyun	status = "okay";
931*4882a593Smuzhiyun};
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun&tcphy1 {
934*4882a593Smuzhiyun	status = "okay";
935*4882a593Smuzhiyun};
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun&tsadc {
938*4882a593Smuzhiyun	/* tshut mode 0:CRU 1:GPIO */
939*4882a593Smuzhiyun	rockchip,hw-tshut-mode = <1>;
940*4882a593Smuzhiyun	/* tshut polarity 0:LOW 1:HIGH */
941*4882a593Smuzhiyun	rockchip,hw-tshut-polarity = <1>;
942*4882a593Smuzhiyun	status = "okay";
943*4882a593Smuzhiyun};
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun&u2phy0 {
946*4882a593Smuzhiyun	status = "okay";
947*4882a593Smuzhiyun	extcon = <&fusb0>;
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun	u2phy0_otg: otg-port {
950*4882a593Smuzhiyun		status = "okay";
951*4882a593Smuzhiyun	};
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun	u2phy0_host: host-port {
954*4882a593Smuzhiyun		phy-supply = <&vcc5v0_host>;
955*4882a593Smuzhiyun		status = "okay";
956*4882a593Smuzhiyun	};
957*4882a593Smuzhiyun};
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun&u2phy1 {
960*4882a593Smuzhiyun	status = "okay";
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun	u2phy1_otg: otg-port {
963*4882a593Smuzhiyun		status = "okay";
964*4882a593Smuzhiyun	};
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun	u2phy1_host: host-port {
967*4882a593Smuzhiyun		phy-supply = <&vcc5v0_host>;
968*4882a593Smuzhiyun		status = "okay";
969*4882a593Smuzhiyun	};
970*4882a593Smuzhiyun};
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun&uart0 {
973*4882a593Smuzhiyun	pinctrl-names = "default";
974*4882a593Smuzhiyun	pinctrl-0 = <&uart0_xfer &uart0_cts>;
975*4882a593Smuzhiyun	status = "okay";
976*4882a593Smuzhiyun};
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun&uart2 {
979*4882a593Smuzhiyun	status = "okay";
980*4882a593Smuzhiyun};
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun&usbdrd3_0 {
983*4882a593Smuzhiyun	status = "okay";
984*4882a593Smuzhiyun};
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun&usbdrd3_1 {
987*4882a593Smuzhiyun	status = "okay";
988*4882a593Smuzhiyun};
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun&usbdrd_dwc3_0 {
991*4882a593Smuzhiyun	status = "okay";
992*4882a593Smuzhiyun	extcon = <&fusb0>;
993*4882a593Smuzhiyun};
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun&usbdrd_dwc3_1 {
996*4882a593Smuzhiyun	status = "okay";
997*4882a593Smuzhiyun	dr_mode = "host";
998*4882a593Smuzhiyun};
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun&usb_host0_ehci {
1001*4882a593Smuzhiyun	status = "okay";
1002*4882a593Smuzhiyun};
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun&usb_host0_ohci {
1005*4882a593Smuzhiyun	status = "okay";
1006*4882a593Smuzhiyun};
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun&usb_host1_ehci {
1009*4882a593Smuzhiyun	status = "okay";
1010*4882a593Smuzhiyun};
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun&usb_host1_ohci {
1013*4882a593Smuzhiyun	status = "okay";
1014*4882a593Smuzhiyun};
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun&cif_isp0 {
1017*4882a593Smuzhiyun	rockchip,camera-modules-attached = <&camera0>;
1018*4882a593Smuzhiyun	status = "okay";
1019*4882a593Smuzhiyun};
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun&isp0_mmu {
1022*4882a593Smuzhiyun	status = "okay";
1023*4882a593Smuzhiyun};
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun&vopb {
1026*4882a593Smuzhiyun	status = "okay";
1027*4882a593Smuzhiyun};
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun&vopb_mmu {
1030*4882a593Smuzhiyun	status = "okay";
1031*4882a593Smuzhiyun};
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun&vopl {
1034*4882a593Smuzhiyun	status = "okay";
1035*4882a593Smuzhiyun};
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun&vopl_mmu {
1038*4882a593Smuzhiyun	status = "okay";
1039*4882a593Smuzhiyun};
1040