1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "rk3399-evb-rev3.dtsi" 10*4882a593Smuzhiyun#include "rk3399-android.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip RK3399 Evaluation Board v3 (Android) LPDDR4"; 14*4882a593Smuzhiyun compatible = "rockchip,android", "rockchip,rk3399-evb-rev3-android-lp4", "rockchip,rk3399"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* first 64k(0xff8c0000~0xff8d0000) for ddr and suspend */ 17*4882a593Smuzhiyun iram: sram@ff8d0000 { 18*4882a593Smuzhiyun compatible = "mmio-sram"; 19*4882a593Smuzhiyun reg = <0x0 0xff8d0000 0x0 0x20000>; /* 128k */ 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun}; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun&dmac_bus { 24*4882a593Smuzhiyun iram = <&iram>; 25*4882a593Smuzhiyun rockchip,force-iram; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun&dsi { 29*4882a593Smuzhiyun status = "okay"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun panel@0 { 32*4882a593Smuzhiyun compatible ="simple-panel-dsi"; 33*4882a593Smuzhiyun reg = <0>; 34*4882a593Smuzhiyun backlight = <&backlight>; 35*4882a593Smuzhiyun enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>; 38*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 39*4882a593Smuzhiyun dsi,lanes = <4>; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun display-timings { 42*4882a593Smuzhiyun native-mode = <&timing0>; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun timing0: timing0 { 45*4882a593Smuzhiyun clock-frequency = <160000000>; 46*4882a593Smuzhiyun hactive = <1200>; 47*4882a593Smuzhiyun vactive = <1920>; 48*4882a593Smuzhiyun hback-porch = <21>; 49*4882a593Smuzhiyun hfront-porch = <120>; 50*4882a593Smuzhiyun vback-porch = <18>; 51*4882a593Smuzhiyun vfront-porch = <21>; 52*4882a593Smuzhiyun hsync-len = <20>; 53*4882a593Smuzhiyun vsync-len = <3>; 54*4882a593Smuzhiyun hsync-active = <0>; 55*4882a593Smuzhiyun vsync-active = <0>; 56*4882a593Smuzhiyun de-active = <0>; 57*4882a593Smuzhiyun pixelclk-active = <0>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun dsp_lut: dsp-lut { 62*4882a593Smuzhiyun gamma-lut = < 63*4882a593Smuzhiyun 0x00000000 0x00010101 0x00020202 0x00030303 0x00040404 0x00050505 0x00060606 0x00070707 64*4882a593Smuzhiyun 0x00080808 0x00090909 0x000a0a0a 0x000b0b0b 0x000c0c0c 0x000d0d0d 0x000e0e0e 0x000f0f0f 65*4882a593Smuzhiyun 0x00101010 0x00111111 0x00121212 0x00131313 0x00141414 0x00151515 0x00161616 0x00171717 66*4882a593Smuzhiyun 0x00181818 0x00191919 0x001a1a1a 0x001b1b1b 0x001c1c1c 0x001d1d1d 0x001e1e1e 0x001f1f1f 67*4882a593Smuzhiyun 0x00202020 0x00212121 0x00222222 0x00232323 0x00242424 0x00252525 0x00262626 0x00272727 68*4882a593Smuzhiyun 0x00282828 0x00292929 0x002a2a2a 0x002b2b2b 0x002c2c2c 0x002d2d2d 0x002e2e2e 0x002f2f2f 69*4882a593Smuzhiyun 0x00303030 0x00313131 0x00323232 0x00333333 0x00343434 0x00353535 0x00363636 0x00373737 70*4882a593Smuzhiyun 0x00383838 0x00393939 0x003a3a3a 0x003b3b3b 0x003c3c3c 0x003d3d3d 0x003e3e3e 0x003f3f3f 71*4882a593Smuzhiyun 0x00404040 0x00414141 0x00424242 0x00434343 0x00444444 0x00454545 0x00464646 0x00474747 72*4882a593Smuzhiyun 0x00484848 0x00494949 0x004a4a4a 0x004b4b4b 0x004c4c4c 0x004d4d4d 0x004e4e4e 0x004f4f4f 73*4882a593Smuzhiyun 0x00505050 0x00515151 0x00525252 0x00535353 0x00545454 0x00555555 0x00565656 0x00575757 74*4882a593Smuzhiyun 0x00585858 0x00595959 0x005a5a5a 0x005b5b5b 0x005c5c5c 0x005d5d5d 0x005e5e5e 0x005f5f5f 75*4882a593Smuzhiyun 0x00606060 0x00616161 0x00626262 0x00636363 0x00646464 0x00656565 0x00666666 0x00676767 76*4882a593Smuzhiyun 0x00686868 0x00696969 0x006a6a6a 0x006b6b6b 0x006c6c6c 0x006d6d6d 0x006e6e6e 0x006f6f6f 77*4882a593Smuzhiyun 0x00707070 0x00717171 0x00727272 0x00737373 0x00747474 0x00757575 0x00767676 0x00777777 78*4882a593Smuzhiyun 0x00787878 0x00797979 0x007a7a7a 0x007b7b7b 0x007c7c7c 0x007d7d7d 0x007e7e7e 0x007f7f7f 79*4882a593Smuzhiyun 0x00808080 0x00818181 0x00828282 0x00838383 0x00848484 0x00858585 0x00868686 0x00878787 80*4882a593Smuzhiyun 0x00888888 0x00898989 0x008a8a8a 0x008b8b8b 0x008c8c8c 0x008d8d8d 0x008e8e8e 0x008f8f8f 81*4882a593Smuzhiyun 0x00909090 0x00919191 0x00929292 0x00939393 0x00949494 0x00959595 0x00969696 0x00979797 82*4882a593Smuzhiyun 0x00989898 0x00999999 0x009a9a9a 0x009b9b9b 0x009c9c9c 0x009d9d9d 0x009e9e9e 0x009f9f9f 83*4882a593Smuzhiyun 0x00a0a0a0 0x00a1a1a1 0x00a2a2a2 0x00a3a3a3 0x00a4a4a4 0x00a5a5a5 0x00a6a6a6 0x00a7a7a7 84*4882a593Smuzhiyun 0x00a8a8a8 0x00a9a9a9 0x00aaaaaa 0x00ababab 0x00acacac 0x00adadad 0x00aeaeae 0x00afafaf 85*4882a593Smuzhiyun 0x00b0b0b0 0x00b1b1b1 0x00b2b2b2 0x00b3b3b3 0x00b4b4b4 0x00b5b5b5 0x00b6b6b6 0x00b7b7b7 86*4882a593Smuzhiyun 0x00b8b8b8 0x00b9b9b9 0x00bababa 0x00bbbbbb 0x00bcbcbc 0x00bdbdbd 0x00bebebe 0x00bfbfbf 87*4882a593Smuzhiyun 0x00c0c0c0 0x00c1c1c1 0x00c2c2c2 0x00c3c3c3 0x00c4c4c4 0x00c5c5c5 0x00c6c6c6 0x00c7c7c7 88*4882a593Smuzhiyun 0x00c8c8c8 0x00c9c9c9 0x00cacaca 0x00cbcbcb 0x00cccccc 0x00cdcdcd 0x00cecece 0x00cfcfcf 89*4882a593Smuzhiyun 0x00d0d0d0 0x00d1d1d1 0x00d2d2d2 0x00d3d3d3 0x00d4d4d4 0x00d5d5d5 0x00d6d6d6 0x00d7d7d7 90*4882a593Smuzhiyun 0x00d8d8d8 0x00d9d9d9 0x00dadada 0x00dbdbdb 0x00dcdcdc 0x00dddddd 0x00dedede 0x00dfdfdf 91*4882a593Smuzhiyun 0x00e0e0e0 0x00e1e1e1 0x00e2e2e2 0x00e3e3e3 0x00e4e4e4 0x00e5e5e5 0x00e6e6e6 0x00e7e7e7 92*4882a593Smuzhiyun 0x00e8e8e8 0x00e9e9e9 0x00eaeaea 0x00ebebeb 0x00ececec 0x00ededed 0x00eeeeee 0x00efefef 93*4882a593Smuzhiyun 0x00f0f0f0 0x00f1f1f1 0x00f2f2f2 0x00f3f3f3 0x00f4f4f4 0x00f5f5f5 0x00f6f6f6 0x00f7f7f7 94*4882a593Smuzhiyun 0x00f8f8f8 0x00f9f9f9 0x00fafafa 0x00fbfbfb 0x00fcfcfc 0x00fdfdfd 0x00fefefe 0x00ffffff>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun ports { 98*4882a593Smuzhiyun #address-cells = <1>; 99*4882a593Smuzhiyun #size-cells = <0>; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun port@0 { 102*4882a593Smuzhiyun reg = <0>; 103*4882a593Smuzhiyun panel_in_dsi: endpoint { 104*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun ports { 111*4882a593Smuzhiyun #address-cells = <1>; 112*4882a593Smuzhiyun #size-cells = <0>; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun port@1 { 115*4882a593Smuzhiyun reg = <1>; 116*4882a593Smuzhiyun dsi_out_panel: endpoint { 117*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun}; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun&cdn_dp { 124*4882a593Smuzhiyun extcon = <&fusb0>, <&fusb1>; 125*4882a593Smuzhiyun status = "okay"; 126*4882a593Smuzhiyun}; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun&route_dsi { 129*4882a593Smuzhiyun status = "okay"; 130*4882a593Smuzhiyun}; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun&dfi { 133*4882a593Smuzhiyun status = "okay"; 134*4882a593Smuzhiyun}; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun&dmc { 137*4882a593Smuzhiyun status = "okay"; 138*4882a593Smuzhiyun center-supply = <&vdd_center>; 139*4882a593Smuzhiyun system-status-freq = < 140*4882a593Smuzhiyun /*system status freq(KHz)*/ 141*4882a593Smuzhiyun SYS_STATUS_NORMAL 856000 142*4882a593Smuzhiyun SYS_STATUS_REBOOT 416000 143*4882a593Smuzhiyun SYS_STATUS_SUSPEND 416000 144*4882a593Smuzhiyun SYS_STATUS_VIDEO_1080P 416000 145*4882a593Smuzhiyun SYS_STATUS_VIDEO_4K 856000 146*4882a593Smuzhiyun SYS_STATUS_VIDEO_4K_10B 856000 147*4882a593Smuzhiyun SYS_STATUS_PERFORMANCE 856000 148*4882a593Smuzhiyun SYS_STATUS_BOOST 856000 149*4882a593Smuzhiyun SYS_STATUS_DUALVIEW 856000 150*4882a593Smuzhiyun SYS_STATUS_ISP 856000 151*4882a593Smuzhiyun >; 152*4882a593Smuzhiyun vop-bw-dmc-freq = < 153*4882a593Smuzhiyun /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ 154*4882a593Smuzhiyun 0 577 416000 155*4882a593Smuzhiyun 578 99999 856000 156*4882a593Smuzhiyun >; 157*4882a593Smuzhiyun auto-min-freq = <416000>; 158*4882a593Smuzhiyun auto-freq-en = <1>; 159*4882a593Smuzhiyun}; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun&dmc_opp_table { 162*4882a593Smuzhiyun compatible = "operating-points-v2"; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun opp-200000000 { 165*4882a593Smuzhiyun opp-hz = /bits/ 64 <200000000>; 166*4882a593Smuzhiyun opp-microvolt = <900000>; 167*4882a593Smuzhiyun status = "disabled"; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun opp-300000000 { 170*4882a593Smuzhiyun opp-hz = /bits/ 64 <300000000>; 171*4882a593Smuzhiyun opp-microvolt = <900000>; 172*4882a593Smuzhiyun status = "disabled"; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun opp-400000000 { 175*4882a593Smuzhiyun opp-hz = /bits/ 64 <400000000>; 176*4882a593Smuzhiyun opp-microvolt = <900000>; 177*4882a593Smuzhiyun status = "disabled"; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun opp-416000000 { 180*4882a593Smuzhiyun opp-hz = /bits/ 64 <416000000>; 181*4882a593Smuzhiyun opp-microvolt = <900000>; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun opp-528000000 { 184*4882a593Smuzhiyun opp-hz = /bits/ 64 <528000000>; 185*4882a593Smuzhiyun opp-microvolt = <900000>; 186*4882a593Smuzhiyun status = "disabled"; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun opp-600000000 { 189*4882a593Smuzhiyun opp-hz = /bits/ 64 <600000000>; 190*4882a593Smuzhiyun opp-microvolt = <900000>; 191*4882a593Smuzhiyun status = "disabled"; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun opp-800000000 { 194*4882a593Smuzhiyun opp-hz = /bits/ 64 <800000000>; 195*4882a593Smuzhiyun opp-microvolt = <900000>; 196*4882a593Smuzhiyun status = "disabled"; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun opp-856000000 { 199*4882a593Smuzhiyun opp-hz = /bits/ 64 <856000000>; 200*4882a593Smuzhiyun opp-microvolt = <900000>; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun opp-928000000 { 203*4882a593Smuzhiyun opp-hz = /bits/ 64 <928000000>; 204*4882a593Smuzhiyun opp-microvolt = <900000>; 205*4882a593Smuzhiyun status = "disabled"; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun opp-1056000000 { 208*4882a593Smuzhiyun opp-hz = /bits/ 64 <1056000000>; 209*4882a593Smuzhiyun opp-microvolt = <900000>; 210*4882a593Smuzhiyun status = "disabled"; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun}; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun&firmware_android { 215*4882a593Smuzhiyun compatible = "android,firmware"; 216*4882a593Smuzhiyun fstab { 217*4882a593Smuzhiyun compatible = "android,fstab"; 218*4882a593Smuzhiyun system { 219*4882a593Smuzhiyun compatible = "android,system"; 220*4882a593Smuzhiyun dev = "/dev/block/by-name/system"; 221*4882a593Smuzhiyun type = "ext4"; 222*4882a593Smuzhiyun mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; 223*4882a593Smuzhiyun fsmgr_flags = "wait,verify"; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun vendor { 226*4882a593Smuzhiyun compatible = "android,vendor"; 227*4882a593Smuzhiyun dev = "/dev/block/by-name/vendor"; 228*4882a593Smuzhiyun type = "ext4"; 229*4882a593Smuzhiyun mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; 230*4882a593Smuzhiyun fsmgr_flags = "wait,verify"; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun}; 234