1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "rk3399-evb-ind.dtsi" 9*4882a593Smuzhiyun#include "rk3399-android.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Rockchip RK3399 EVB IND LPDDR4 Board edp (Android)"; 13*4882a593Smuzhiyun compatible = "rockchip,android", "rockchip,rk3399-evb-ind-v13-lpddr4-android", "rockchip,rk3399"; 14*4882a593Smuzhiyun chosen: chosen { 15*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 init=/init initrd=0x62000001,0x00800000 coherent_pool=1m"; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun iram: sram@ff8d0000 { 19*4882a593Smuzhiyun compatible = "mmio-sram"; 20*4882a593Smuzhiyun reg = <0x0 0xff8d0000 0x0 0x20000>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun hub_reset: hub_reset { 24*4882a593Smuzhiyun compatible = "regulator-fixed"; 25*4882a593Smuzhiyun enable-active-high; 26*4882a593Smuzhiyun gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; 27*4882a593Smuzhiyun regulator-name = "hub_reset"; 28*4882a593Smuzhiyun regulator-always-on; 29*4882a593Smuzhiyun regulator-boot-on; 30*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 31*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun vcc_lcd: vcc-lcd { 35*4882a593Smuzhiyun compatible = "regulator-fixed"; 36*4882a593Smuzhiyun regulator-name = "vcc_lcd"; 37*4882a593Smuzhiyun startup-delay-us = <20000>; 38*4882a593Smuzhiyun enable-active-high; 39*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 40*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 41*4882a593Smuzhiyun regulator-boot-on; 42*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun panel: panel { 46*4882a593Smuzhiyun compatible = "simple-panel"; 47*4882a593Smuzhiyun backlight = <&backlight>; 48*4882a593Smuzhiyun power-supply = <&vcc_lcd>; 49*4882a593Smuzhiyun reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; 50*4882a593Smuzhiyun prepare-delay-ms = <20>; 51*4882a593Smuzhiyun reset-delay-ms = <20>; 52*4882a593Smuzhiyun enable-delay-ms = <20>; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun display-timings { 55*4882a593Smuzhiyun native-mode = <&timing0>; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun timing0: timing0 { 58*4882a593Smuzhiyun clock-frequency = <200000000>; 59*4882a593Smuzhiyun hactive = <1536>; 60*4882a593Smuzhiyun vactive = <2048>; 61*4882a593Smuzhiyun hfront-porch = <12>; 62*4882a593Smuzhiyun hsync-len = <16>; 63*4882a593Smuzhiyun hback-porch = <48>; 64*4882a593Smuzhiyun vfront-porch = <8>; 65*4882a593Smuzhiyun vsync-len = <4>; 66*4882a593Smuzhiyun vback-porch = <8>; 67*4882a593Smuzhiyun hsync-active = <0>; 68*4882a593Smuzhiyun vsync-active = <0>; 69*4882a593Smuzhiyun de-active = <0>; 70*4882a593Smuzhiyun pixelclk-active = <0>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun ports { 75*4882a593Smuzhiyun panel_in: endpoint { 76*4882a593Smuzhiyun remote-endpoint = <&edp_out>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun test-power { 82*4882a593Smuzhiyun status = "okay"; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun}; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun&backlight { 87*4882a593Smuzhiyun enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun&dmac_bus { 91*4882a593Smuzhiyun iram = <&iram>; 92*4882a593Smuzhiyun rockchip,force-iram; 93*4882a593Smuzhiyun}; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun&dp_sound { 96*4882a593Smuzhiyun status = "disabled"; 97*4882a593Smuzhiyun}; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun&edp { 100*4882a593Smuzhiyun status = "okay"; 101*4882a593Smuzhiyun force-hpd; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun ports { 104*4882a593Smuzhiyun port@1 { 105*4882a593Smuzhiyun reg = <1>; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun edp_out: endpoint { 108*4882a593Smuzhiyun remote-endpoint = <&panel_in>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun}; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun&edp_in_vopl { 115*4882a593Smuzhiyun status = "disabled"; 116*4882a593Smuzhiyun}; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun&i2c1 { 119*4882a593Smuzhiyun status = "okay"; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun sgm3784: sgm3784@30 { 122*4882a593Smuzhiyun #address-cells = <1>; 123*4882a593Smuzhiyun #size-cells = <0>; 124*4882a593Smuzhiyun compatible = "sgmicro,gsm3784"; 125*4882a593Smuzhiyun reg = <0x30>; 126*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 127*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 128*4882a593Smuzhiyun //enable-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; 129*4882a593Smuzhiyun //strobe-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; 130*4882a593Smuzhiyun status = "okay"; 131*4882a593Smuzhiyun sgm3784_led0: led@0 { 132*4882a593Smuzhiyun reg = <0x0>; 133*4882a593Smuzhiyun led-max-microamp = <299200>; 134*4882a593Smuzhiyun flash-max-microamp = <1122000>; 135*4882a593Smuzhiyun flash-max-timeout-us = <1600000>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun sgm3784_led1: led@1 { 139*4882a593Smuzhiyun reg = <0x1>; 140*4882a593Smuzhiyun led-max-microamp = <299200>; 141*4882a593Smuzhiyun flash-max-microamp = <1122000>; 142*4882a593Smuzhiyun flash-max-timeout-us = <1600000>; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun vm149c: vm149c@0c { 147*4882a593Smuzhiyun compatible = "silicon touch,vm149c"; 148*4882a593Smuzhiyun status = "okay"; 149*4882a593Smuzhiyun reg = <0x0c>; 150*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 151*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun gc2145: gc2145@3c{ 155*4882a593Smuzhiyun status = "okay"; 156*4882a593Smuzhiyun compatible = "galaxycore,gc2145"; 157*4882a593Smuzhiyun reg = <0x3c>; 158*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 159*4882a593Smuzhiyun pinctrl-0 = <&cif_clkout>; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 162*4882a593Smuzhiyun clock-names = "xvclk"; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* avdd-supply = <>; */ 165*4882a593Smuzhiyun /* dvdd-supply = <>; */ 166*4882a593Smuzhiyun /* dovdd-supply = <>; */ 167*4882a593Smuzhiyun power-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; 168*4882a593Smuzhiyun pwdn-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 169*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 170*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 171*4882a593Smuzhiyun rockchip,camera-module-name = "CameraKing"; 172*4882a593Smuzhiyun rockchip,camera-module-lens-name = "Largan"; 173*4882a593Smuzhiyun port { 174*4882a593Smuzhiyun gc2145_out: endpoint { 175*4882a593Smuzhiyun remote-endpoint = <&dvp_in_fcam>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun ov13850: ov13850@10 { 181*4882a593Smuzhiyun compatible = "ovti,ov13850"; 182*4882a593Smuzhiyun status = "okay"; 183*4882a593Smuzhiyun reg = <0x10>; 184*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 185*4882a593Smuzhiyun clock-names = "xvclk"; 186*4882a593Smuzhiyun /* avdd-supply = <>; */ 187*4882a593Smuzhiyun /* dvdd-supply = <>; */ 188*4882a593Smuzhiyun /* dovdd-supply = <>; */ 189*4882a593Smuzhiyun /* reset-gpios = <>; */ 190*4882a593Smuzhiyun reset-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 191*4882a593Smuzhiyun pwdn-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 192*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 193*4882a593Smuzhiyun pinctrl-0 = <&cif_clkout>; 194*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 195*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 196*4882a593Smuzhiyun rockchip,camera-module-name = "CMK-CT0116"; 197*4882a593Smuzhiyun rockchip,camera-module-lens-name = "Largan-50013A1"; 198*4882a593Smuzhiyun lens-focus = <&vm149c>; 199*4882a593Smuzhiyun flash-leds = <&sgm3784_led0 &sgm3784_led1>; 200*4882a593Smuzhiyun port { 201*4882a593Smuzhiyun ucam_out0: endpoint { 202*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam0>; 203*4882a593Smuzhiyun //remote-endpoint = <&mipi_in_ucam1>; 204*4882a593Smuzhiyun data-lanes = <1 2>; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun ov4689: ov4689@36 { 210*4882a593Smuzhiyun compatible = "ovti,ov4689"; 211*4882a593Smuzhiyun status = "disabled"; 212*4882a593Smuzhiyun reg = <0x36>; 213*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 214*4882a593Smuzhiyun clock-names = "xvclk"; 215*4882a593Smuzhiyun /* avdd-supply = <>; */ 216*4882a593Smuzhiyun /* dvdd-supply = <>; */ 217*4882a593Smuzhiyun /* dovdd-supply = <>; */ 218*4882a593Smuzhiyun /* reset-gpios = <>; */ 219*4882a593Smuzhiyun reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 220*4882a593Smuzhiyun pwdn-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 221*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 222*4882a593Smuzhiyun pinctrl-0 = <&cif_clkout>; 223*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 224*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 225*4882a593Smuzhiyun rockchip,camera-module-name = "JSD3425-C1"; 226*4882a593Smuzhiyun rockchip,camera-module-lens-name = "JSD3425-C1"; 227*4882a593Smuzhiyun port { 228*4882a593Smuzhiyun ucam_out1: endpoint { 229*4882a593Smuzhiyun //remote-endpoint = <&mipi_in_ucam0>; 230*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam1>; 231*4882a593Smuzhiyun data-lanes = <1 2>; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun}; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun&i2s2 { 238*4882a593Smuzhiyun #sound-dai-cells = <0>; 239*4882a593Smuzhiyun status = "okay"; 240*4882a593Smuzhiyun}; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun&isp0_mmu { 243*4882a593Smuzhiyun status = "okay"; 244*4882a593Smuzhiyun}; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun&isp1_mmu { 247*4882a593Smuzhiyun status = "okay"; 248*4882a593Smuzhiyun}; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun&mipi_dphy_rx0 { 251*4882a593Smuzhiyun status = "okay"; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun ports { 254*4882a593Smuzhiyun #address-cells = <1>; 255*4882a593Smuzhiyun #size-cells = <0>; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun port@0 { 258*4882a593Smuzhiyun reg = <0>; 259*4882a593Smuzhiyun #address-cells = <1>; 260*4882a593Smuzhiyun #size-cells = <0>; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun mipi_in_ucam0: endpoint@1 { 263*4882a593Smuzhiyun reg = <1>; 264*4882a593Smuzhiyun remote-endpoint = <&ucam_out0>; 265*4882a593Smuzhiyun data-lanes = <1 2>; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun port@1 { 270*4882a593Smuzhiyun reg = <1>; 271*4882a593Smuzhiyun #address-cells = <1>; 272*4882a593Smuzhiyun #size-cells = <0>; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun dphy_rx0_out: endpoint@0 { 275*4882a593Smuzhiyun reg = <0>; 276*4882a593Smuzhiyun remote-endpoint = <&isp0_mipi_in>; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun}; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun&mipi_dphy_tx1rx1 { 283*4882a593Smuzhiyun status = "okay"; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun ports { 286*4882a593Smuzhiyun #address-cells = <1>; 287*4882a593Smuzhiyun #size-cells = <0>; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun port@0 { 290*4882a593Smuzhiyun reg = <0>; 291*4882a593Smuzhiyun #address-cells = <1>; 292*4882a593Smuzhiyun #size-cells = <0>; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun mipi_in_ucam1: endpoint@1 { 295*4882a593Smuzhiyun reg = <1>; 296*4882a593Smuzhiyun remote-endpoint = <&ucam_out1>; 297*4882a593Smuzhiyun data-lanes = <1 2>; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun port@1 { 302*4882a593Smuzhiyun reg = <1>; 303*4882a593Smuzhiyun #address-cells = <1>; 304*4882a593Smuzhiyun #size-cells = <0>; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun dphy_tx1rx1_out: endpoint@0 { 307*4882a593Smuzhiyun reg = <0>; 308*4882a593Smuzhiyun remote-endpoint = <&isp1_mipi_in>; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun}; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun&hdmi_sound { 315*4882a593Smuzhiyun status = "okay"; 316*4882a593Smuzhiyun}; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun&route_edp { 319*4882a593Smuzhiyun status = "okay"; 320*4882a593Smuzhiyun}; 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun&route_hdmi { 323*4882a593Smuzhiyun status = "okay"; 324*4882a593Smuzhiyun connect = <&vopl_out_hdmi>; 325*4882a593Smuzhiyun}; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun&i2s1 { 328*4882a593Smuzhiyun #sound-dai-cells = <0>; 329*4882a593Smuzhiyun status = "okay"; 330*4882a593Smuzhiyun}; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun&rk809_sound { 333*4882a593Smuzhiyun status = "okay"; 334*4882a593Smuzhiyun}; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun&hdmi_in_vopb { 337*4882a593Smuzhiyun status = "disabled"; 338*4882a593Smuzhiyun}; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun&rkisp1_0 { 341*4882a593Smuzhiyun status = "okay"; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun port { 344*4882a593Smuzhiyun #address-cells = <1>; 345*4882a593Smuzhiyun #size-cells = <0>; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun isp0_mipi_in: endpoint@0 { 348*4882a593Smuzhiyun reg = <0>; 349*4882a593Smuzhiyun remote-endpoint = <&dphy_rx0_out>; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun}; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun&rkisp1_1 { 355*4882a593Smuzhiyun status = "okay"; 356*4882a593Smuzhiyun pinctrl-names = "default"; 357*4882a593Smuzhiyun pinctrl-0 = <&cif_clkout &isp_dvp_d0d7>; 358*4882a593Smuzhiyun port { 359*4882a593Smuzhiyun #address-cells = <1>; 360*4882a593Smuzhiyun #size-cells = <0>; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun isp1_mipi_in: endpoint@0 { 363*4882a593Smuzhiyun reg = <0>; 364*4882a593Smuzhiyun remote-endpoint = <&dphy_tx1rx1_out>; 365*4882a593Smuzhiyun }; 366*4882a593Smuzhiyun dvp_in_fcam: endpoint@1 { 367*4882a593Smuzhiyun reg = <1>; 368*4882a593Smuzhiyun remote-endpoint = <&gc2145_out>; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun }; 371*4882a593Smuzhiyun}; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun&vcca_0v9 { 375*4882a593Smuzhiyun regulator-always-on; 376*4882a593Smuzhiyun regulator-boot-on; 377*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 378*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 379*4882a593Smuzhiyun regulator-name = "vcca_0v9"; 380*4882a593Smuzhiyun regulator-state-mem { 381*4882a593Smuzhiyun regulator-on-in-suspend; 382*4882a593Smuzhiyun regulator-suspend-microvolt = <900000>; 383*4882a593Smuzhiyun }; 384*4882a593Smuzhiyun}; 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun&vcc0v9_soc { 387*4882a593Smuzhiyun regulator-always-on; 388*4882a593Smuzhiyun regulator-boot-on; 389*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 390*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun regulator-name = "vcc0v9_soc"; 393*4882a593Smuzhiyun regulator-state-mem { 394*4882a593Smuzhiyun regulator-off-in-suspend; 395*4882a593Smuzhiyun }; 396*4882a593Smuzhiyun}; 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun/* 399*4882a593Smuzhiyun * if enable dp_sound, should disable spdif_sound and spdif_out 400*4882a593Smuzhiyun */ 401*4882a593Smuzhiyun&spdif_out { 402*4882a593Smuzhiyun status = "disabled"; 403*4882a593Smuzhiyun}; 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun&spdif_sound { 406*4882a593Smuzhiyun status = "disabled"; 407*4882a593Smuzhiyun}; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun&i2s0 { 410*4882a593Smuzhiyun #sound-dai-cells = <0>; 411*4882a593Smuzhiyun status = "disabled"; 412*4882a593Smuzhiyun}; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun&tc358749x_sound { 415*4882a593Smuzhiyun status = "disabled"; 416*4882a593Smuzhiyun}; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun&pinctrl { 419*4882a593Smuzhiyun lcd-panel { 420*4882a593Smuzhiyun lcd_panel_reset: lcd-panel-reset { 421*4882a593Smuzhiyun rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 422*4882a593Smuzhiyun }; 423*4882a593Smuzhiyun }; 424*4882a593Smuzhiyun}; 425*4882a593Smuzhiyun 426