1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6/dts-v1/; 7 8#include "rk3399-evb-ind.dtsi" 9#include "rk3399-android.dtsi" 10 11/ { 12 model = "Rockchip RK3399 EVB IND LPDDR4 Board edp (Android)"; 13 compatible = "rockchip,android", "rockchip,rk3399-evb-ind-lpddr4-android", "rockchip,rk3399"; 14 chosen: chosen { 15 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 init=/init initrd=0x62000001,0x00800000 coherent_pool=1m"; 16 }; 17 18 iram: sram@ff8d0000 { 19 compatible = "mmio-sram"; 20 reg = <0x0 0xff8d0000 0x0 0x20000>; 21 }; 22 23 vcc_lcd: vcc-lcd { 24 compatible = "regulator-fixed"; 25 regulator-name = "vcc_lcd"; 26 startup-delay-us = <20000>; 27 enable-active-high; 28 regulator-min-microvolt = <3300000>; 29 regulator-max-microvolt = <3300000>; 30 regulator-boot-on; 31 vin-supply = <&vcc5v0_sys>; 32 }; 33 34 panel: panel { 35 compatible = "simple-panel"; 36 backlight = <&backlight>; 37 power-supply = <&vcc_lcd>; 38 reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; 39 prepare-delay-ms = <20>; 40 reset-delay-ms = <20>; 41 enable-delay-ms = <20>; 42 43 display-timings { 44 native-mode = <&timing0>; 45 46 timing0: timing0 { 47 clock-frequency = <200000000>; 48 hactive = <1536>; 49 vactive = <2048>; 50 hfront-porch = <12>; 51 hsync-len = <16>; 52 hback-porch = <48>; 53 vfront-porch = <8>; 54 vsync-len = <4>; 55 vback-porch = <8>; 56 hsync-active = <0>; 57 vsync-active = <0>; 58 de-active = <0>; 59 pixelclk-active = <0>; 60 }; 61 }; 62 63 ports { 64 panel_in: endpoint { 65 remote-endpoint = <&edp_out>; 66 }; 67 }; 68 }; 69 70 test-power { 71 status = "okay"; 72 }; 73}; 74 75&backlight { 76 enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 77}; 78 79&dmac_bus { 80 iram = <&iram>; 81 rockchip,force-iram; 82}; 83 84&dp_sound { 85 status = "disabled"; 86}; 87 88&edp { 89 status = "okay"; 90 force-hpd; 91 92 ports { 93 port@1 { 94 reg = <1>; 95 96 edp_out: endpoint { 97 remote-endpoint = <&panel_in>; 98 }; 99 }; 100 }; 101}; 102 103&edp_in_vopl { 104 status = "disabled"; 105}; 106 107&i2c1 { 108 status = "okay"; 109 110 sgm3784: sgm3784@30 { 111 #address-cells = <1>; 112 #size-cells = <0>; 113 compatible = "sgmicro,gsm3784"; 114 reg = <0x30>; 115 rockchip,camera-module-index = <0>; 116 rockchip,camera-module-facing = "back"; 117 //enable-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; 118 //strobe-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; 119 status = "okay"; 120 sgm3784_led0: led@0 { 121 reg = <0x0>; 122 led-max-microamp = <299200>; 123 flash-max-microamp = <1122000>; 124 flash-max-timeout-us = <1600000>; 125 }; 126 127 sgm3784_led1: led@1 { 128 reg = <0x1>; 129 led-max-microamp = <299200>; 130 flash-max-microamp = <1122000>; 131 flash-max-timeout-us = <1600000>; 132 }; 133 }; 134 135 vm149c: vm149c@0c { 136 compatible = "silicon touch,vm149c"; 137 status = "okay"; 138 reg = <0x0c>; 139 rockchip,camera-module-index = <0>; 140 rockchip,camera-module-facing = "back"; 141 }; 142 143 gc2145: gc2145@3c{ 144 status = "okay"; 145 compatible = "galaxycore,gc2145"; 146 reg = <0x3c>; 147 pinctrl-names = "rockchip,camera_default"; 148 pinctrl-0 = <&cif_clkout>; 149 150 clocks = <&cru SCLK_CIF_OUT>; 151 clock-names = "xvclk"; 152 153 /* avdd-supply = <>; */ 154 /* dvdd-supply = <>; */ 155 /* dovdd-supply = <>; */ 156 power-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; 157 pwdn-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 158 rockchip,camera-module-index = <1>; 159 rockchip,camera-module-facing = "front"; 160 rockchip,camera-module-name = "CameraKing"; 161 rockchip,camera-module-lens-name = "Largan"; 162 port { 163 gc2145_out: endpoint { 164 remote-endpoint = <&dvp_in_fcam>; 165 }; 166 }; 167 }; 168 169 ov13850: ov13850@10 { 170 compatible = "ovti,ov13850"; 171 status = "okay"; 172 reg = <0x10>; 173 clocks = <&cru SCLK_CIF_OUT>; 174 clock-names = "xvclk"; 175 /* avdd-supply = <>; */ 176 /* dvdd-supply = <>; */ 177 /* dovdd-supply = <>; */ 178 /* reset-gpios = <>; */ 179 reset-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 180 pwdn-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 181 pinctrl-names = "rockchip,camera_default"; 182 pinctrl-0 = <&cif_clkout>; 183 rockchip,camera-module-index = <0>; 184 rockchip,camera-module-facing = "back"; 185 rockchip,camera-module-name = "CMK-CT0116"; 186 rockchip,camera-module-lens-name = "Largan-50013A1"; 187 lens-focus = <&vm149c>; 188 flash-leds = <&sgm3784_led0 &sgm3784_led1>; 189 port { 190 ucam_out0: endpoint { 191 remote-endpoint = <&mipi_in_ucam0>; 192 //remote-endpoint = <&mipi_in_ucam1>; 193 data-lanes = <1 2>; 194 }; 195 }; 196 }; 197 198 ov4689: ov4689@36 { 199 compatible = "ovti,ov4689"; 200 status = "disabled"; 201 reg = <0x36>; 202 clocks = <&cru SCLK_CIF_OUT>; 203 clock-names = "xvclk"; 204 /* avdd-supply = <>; */ 205 /* dvdd-supply = <>; */ 206 /* dovdd-supply = <>; */ 207 /* reset-gpios = <>; */ 208 reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 209 pwdn-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 210 pinctrl-names = "rockchip,camera_default"; 211 pinctrl-0 = <&cif_clkout>; 212 rockchip,camera-module-index = <1>; 213 rockchip,camera-module-facing = "front"; 214 rockchip,camera-module-name = "JSD3425-C1"; 215 rockchip,camera-module-lens-name = "JSD3425-C1"; 216 port { 217 ucam_out1: endpoint { 218 //remote-endpoint = <&mipi_in_ucam0>; 219 remote-endpoint = <&mipi_in_ucam1>; 220 data-lanes = <1 2>; 221 }; 222 }; 223 }; 224}; 225 226&i2s2 { 227 #sound-dai-cells = <0>; 228 status = "okay"; 229}; 230 231&isp0_mmu { 232 status = "okay"; 233}; 234 235&isp1_mmu { 236 status = "okay"; 237}; 238 239&mipi_dphy_rx0 { 240 status = "okay"; 241 242 ports { 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 port@0 { 247 reg = <0>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 251 mipi_in_ucam0: endpoint@1 { 252 reg = <1>; 253 remote-endpoint = <&ucam_out0>; 254 data-lanes = <1 2>; 255 }; 256 }; 257 258 port@1 { 259 reg = <1>; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 263 dphy_rx0_out: endpoint@0 { 264 reg = <0>; 265 remote-endpoint = <&isp0_mipi_in>; 266 }; 267 }; 268 }; 269}; 270 271&mipi_dphy_tx1rx1 { 272 status = "okay"; 273 274 ports { 275 #address-cells = <1>; 276 #size-cells = <0>; 277 278 port@0 { 279 reg = <0>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 283 mipi_in_ucam1: endpoint@1 { 284 reg = <1>; 285 remote-endpoint = <&ucam_out1>; 286 data-lanes = <1 2>; 287 }; 288 }; 289 290 port@1 { 291 reg = <1>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 295 dphy_tx1rx1_out: endpoint@0 { 296 reg = <0>; 297 remote-endpoint = <&isp1_mipi_in>; 298 }; 299 }; 300 }; 301}; 302 303&hdmi_sound { 304 status = "okay"; 305}; 306 307&route_edp { 308 status = "okay"; 309}; 310 311&route_hdmi { 312 status = "okay"; 313 connect = <&vopl_out_hdmi>; 314}; 315 316&i2s1 { 317 #sound-dai-cells = <0>; 318 status = "okay"; 319}; 320 321&rk809_sound { 322 status = "okay"; 323}; 324 325&hdmi_in_vopb { 326 status = "disabled"; 327}; 328 329&rkisp1_0 { 330 status = "okay"; 331 332 port { 333 #address-cells = <1>; 334 #size-cells = <0>; 335 336 isp0_mipi_in: endpoint@0 { 337 reg = <0>; 338 remote-endpoint = <&dphy_rx0_out>; 339 }; 340 }; 341}; 342 343&rkisp1_1 { 344 status = "okay"; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&cif_clkout &isp_dvp_d0d7>; 347 port { 348 #address-cells = <1>; 349 #size-cells = <0>; 350 351 isp1_mipi_in: endpoint@0 { 352 reg = <0>; 353 remote-endpoint = <&dphy_tx1rx1_out>; 354 }; 355 dvp_in_fcam: endpoint@1 { 356 reg = <1>; 357 remote-endpoint = <&gc2145_out>; 358 }; 359 }; 360}; 361 362/* 363 * if enable dp_sound, should disable spdif_sound and spdif_out 364 */ 365&spdif_out { 366 status = "disabled"; 367}; 368 369&spdif_sound { 370 status = "disabled"; 371}; 372 373&i2s0 { 374 #sound-dai-cells = <0>; 375 status = "disabled"; 376}; 377 378&tc358749x_sound { 379 status = "disabled"; 380}; 381 382&pinctrl { 383 lcd-panel { 384 lcd_panel_reset: lcd-panel-reset { 385 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 386 }; 387 }; 388}; 389 390