1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/dts-v1/; 8#include "rk3399-box.dtsi" 9 10/ { 11 model = "Rockchip RK3399 Board rev1 (BOX)"; 12 compatible = "rockchip-box-rev1","rockchip,rk3399-box"; 13}; 14 15&pinctrl { 16 sdio0 { 17 sdio0_bus1: sdio0-bus1 { 18 rockchip,pins = 19 <2 RK_PC4 1 &pcfg_pull_up_20ma>; 20 }; 21 22 sdio0_bus4: sdio0-bus4 { 23 rockchip,pins = 24 <2 RK_PC4 1 &pcfg_pull_up_20ma>, 25 <2 RK_PC5 1 &pcfg_pull_up_20ma>, 26 <2 RK_PC6 1 &pcfg_pull_up_20ma>, 27 <2 RK_PC7 1 &pcfg_pull_up_20ma>; 28 }; 29 30 sdio0_cmd: sdio0-cmd { 31 rockchip,pins = 32 <2 RK_PD0 1 &pcfg_pull_up_20ma>; 33 }; 34 35 sdio0_clk: sdio0-clk { 36 rockchip,pins = 37 <2 RK_PD1 1 &pcfg_pull_none_20ma>; 38 }; 39 }; 40 41 sdmmc { 42 sdmmc_bus1: sdmmc-bus1 { 43 rockchip,pins = 44 <4 RK_PB0 1 &pcfg_pull_up_8ma>; 45 }; 46 47 sdmmc_bus4: sdmmc-bus4 { 48 rockchip,pins = 49 <4 RK_PB0 1 &pcfg_pull_up_8ma>, 50 <4 RK_PB1 1 &pcfg_pull_up_8ma>, 51 <4 RK_PB2 1 &pcfg_pull_up_8ma>, 52 <4 RK_PB3 1 &pcfg_pull_up_8ma>; 53 }; 54 55 sdmmc_clk: sdmmc-clk { 56 rockchip,pins = 57 <4 RK_PB4 1 &pcfg_pull_none_18ma>; 58 }; 59 60 sdmmc_cmd: sdmmc-cmd { 61 rockchip,pins = 62 <4 RK_PB5 1 &pcfg_pull_up_8ma>; 63 }; 64 }; 65 66 fusb30x { 67 fusb0_int: fusb0-int { 68 rockchip,pins = 69 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 70 }; 71 }; 72}; 73 74&i2c4 { 75 status = "okay"; 76 fusb0: fusb30x@22 { 77 compatible = "fairchild,fusb302"; 78 reg = <0x22>; 79 pinctrl-names = "default"; 80 pinctrl-0 = <&fusb0_int>; 81 vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 82 int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 83 status = "okay"; 84 }; 85}; 86 87&cdn_dp { 88 status = "okay"; 89 extcon = <&fusb0>; 90}; 91 92&hdmi_in_vopl { 93 status = "disabled"; 94}; 95 96&dp_in_vopb { 97 status = "disabled"; 98}; 99