xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3358m-vehicle-ddr3.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
9*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
10*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
11*4882a593Smuzhiyun#include "rk3358.dtsi"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	adc-keys {
15*4882a593Smuzhiyun		compatible = "adc-keys";
16*4882a593Smuzhiyun		io-channels = <&saradc 2>;
17*4882a593Smuzhiyun		io-channel-names = "buttons";
18*4882a593Smuzhiyun		poll-interval = <100>;
19*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun		vol-down-key {
22*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
23*4882a593Smuzhiyun			label = "volume down";
24*4882a593Smuzhiyun			press-threshold-microvolt = <300000>;
25*4882a593Smuzhiyun		};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		vol-up-key {
28*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
29*4882a593Smuzhiyun			label = "volume up";
30*4882a593Smuzhiyun			press-threshold-microvolt = <17000>;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	backlight: backlight {
35*4882a593Smuzhiyun		compatible = "pwm-backlight";
36*4882a593Smuzhiyun		pwms = <&pwm1 0 25000 0>;
37*4882a593Smuzhiyun		brightness-levels = <
38*4882a593Smuzhiyun			  0   1   2   3   4   5   6   7
39*4882a593Smuzhiyun			  8   9  10  11  12  13  14  15
40*4882a593Smuzhiyun			 16  17  18  19  20  21  22  23
41*4882a593Smuzhiyun			 24  25  26  27  28  29  30  31
42*4882a593Smuzhiyun			 32  33  34  35  36  37  38  39
43*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
44*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
45*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
46*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
47*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
48*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
49*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
50*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
51*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
52*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
53*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
54*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
55*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
56*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
57*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
58*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
59*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
60*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
61*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
62*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
63*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
64*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
65*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
66*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
67*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
68*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
69*4882a593Smuzhiyun			248 249 250 251 252 253 254 255>;
70*4882a593Smuzhiyun		default-brightness-level = <200>;
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	backlight_2: backlight-2 {
74*4882a593Smuzhiyun		compatible = "pwm-backlight";
75*4882a593Smuzhiyun		pwms = <&pwm3 0 10000000 0>;
76*4882a593Smuzhiyun		pinctrl-names = "default";
77*4882a593Smuzhiyun		pinctrl-0 = <&lcd0_pwren &lcd0_rst>;
78*4882a593Smuzhiyun		enable-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_HIGH>;
79*4882a593Smuzhiyun		brightness-levels = <
80*4882a593Smuzhiyun			  0   1   2   3   4   5   6   7
81*4882a593Smuzhiyun			  8   9  10  11  12  13  14  15
82*4882a593Smuzhiyun			 16  17  18  19  20  21  22  23
83*4882a593Smuzhiyun			 24  25  26  27  28  29  30  31
84*4882a593Smuzhiyun			 32  33  34  35  36  37  38  39
85*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
86*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
87*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
88*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
89*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
90*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
91*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
92*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
93*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
94*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
95*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
96*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
97*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
98*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
99*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
100*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
101*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
102*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
103*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
104*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
105*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
106*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
107*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
108*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
109*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
110*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
111*4882a593Smuzhiyun			248 249 250 251 252 253 254 255>;
112*4882a593Smuzhiyun		default-brightness-level = <60>;
113*4882a593Smuzhiyun	};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun	/* The THine 827-Q (rgb to dual lvds) don't need driver */
116*4882a593Smuzhiyun	panel-rgb {
117*4882a593Smuzhiyun		compatible = "simple-panel";
118*4882a593Smuzhiyun		#address-cells = <1>;
119*4882a593Smuzhiyun		#size-cells = <0>;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		pinctrl-names = "default";
122*4882a593Smuzhiyun		pinctrl-0 = <&pwdn_rgb>; /* This the pwdn of THine-827-Q */
123*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd>;
124*4882a593Smuzhiyun		backlight = <&backlight_2>;
125*4882a593Smuzhiyun		enable-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
126*4882a593Smuzhiyun		reset-gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>;
127*4882a593Smuzhiyun		prepare-delay-ms = <0>;
128*4882a593Smuzhiyun		reset-delay-ms = <0>;
129*4882a593Smuzhiyun		init-delay-ms = <0>;
130*4882a593Smuzhiyun		enable-delay-ms = <5>;
131*4882a593Smuzhiyun		disable-delay-ms = <10>;
132*4882a593Smuzhiyun		unprepare-delay-ms = <0>;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun		width-mm = <292>;
135*4882a593Smuzhiyun		height-mm = <109>;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun		bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun		display-timings {
140*4882a593Smuzhiyun			native-mode = <&timing1>;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun			timing1: timing1 {
143*4882a593Smuzhiyun				clock-frequency = <88200000>;
144*4882a593Smuzhiyun				hactive = <1920>;
145*4882a593Smuzhiyun				vactive = <720>;
146*4882a593Smuzhiyun				hfront-porch = <40>;
147*4882a593Smuzhiyun				hsync-len = <20>;
148*4882a593Smuzhiyun				hback-porch = <24>;
149*4882a593Smuzhiyun				vfront-porch = <5>;
150*4882a593Smuzhiyun				vsync-len = <4>;
151*4882a593Smuzhiyun				vback-porch = <4>;
152*4882a593Smuzhiyun				hsync-active = <0>;
153*4882a593Smuzhiyun				vsync-active = <0>;
154*4882a593Smuzhiyun				de-active = <0>;
155*4882a593Smuzhiyun				pixelclk-active = <0>;
156*4882a593Smuzhiyun			};
157*4882a593Smuzhiyun		};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun		ports {
160*4882a593Smuzhiyun			#address-cells = <1>;
161*4882a593Smuzhiyun			#size-cells = <0>;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun			port@0 {
164*4882a593Smuzhiyun				reg = <0>;
165*4882a593Smuzhiyun				panel_in_rgb: endpoint {
166*4882a593Smuzhiyun					remote-endpoint = <&rgb_out_panel>;
167*4882a593Smuzhiyun				};
168*4882a593Smuzhiyun			};
169*4882a593Smuzhiyun		};
170*4882a593Smuzhiyun	};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun	rk809-sound {
174*4882a593Smuzhiyun		compatible = "simple-audio-card";
175*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
176*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,rk809-codec";
177*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
178*4882a593Smuzhiyun		simple-audio-card,widgets =
179*4882a593Smuzhiyun			"Microphone", "Mic Jack",
180*4882a593Smuzhiyun			"Headphone", "Headphone Jack";
181*4882a593Smuzhiyun		simple-audio-card,routing =
182*4882a593Smuzhiyun			"Mic Jack", "MICBIAS1",
183*4882a593Smuzhiyun			"IN1P", "Mic Jack",
184*4882a593Smuzhiyun			"Headphone Jack", "HPOL",
185*4882a593Smuzhiyun			"Headphone Jack", "HPOR";
186*4882a593Smuzhiyun		simple-audio-card,cpu {
187*4882a593Smuzhiyun			sound-dai = <&i2s1_2ch>;
188*4882a593Smuzhiyun		};
189*4882a593Smuzhiyun		simple-audio-card,codec {
190*4882a593Smuzhiyun			sound-dai = <&rk809_codec>;
191*4882a593Smuzhiyun		};
192*4882a593Smuzhiyun	};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
195*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
196*4882a593Smuzhiyun		pinctrl-names = "default";
197*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun		/*
200*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
201*4882a593Smuzhiyun		 * on the actual card populated):
202*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
203*4882a593Smuzhiyun		 * - PDN (power down when low)
204*4882a593Smuzhiyun		 */
205*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>;
206*4882a593Smuzhiyun	};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun	vcc5v0_sys: vccsys {
209*4882a593Smuzhiyun		compatible = "regulator-fixed";
210*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
211*4882a593Smuzhiyun		regulator-always-on;
212*4882a593Smuzhiyun		regulator-boot-on;
213*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
214*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
215*4882a593Smuzhiyun	};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun	wireless-wlan {
218*4882a593Smuzhiyun		compatible = "wlan-platdata";
219*4882a593Smuzhiyun		wifi_chip_type = "AP6212";
220*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
221*4882a593Smuzhiyun		status = "okay";
222*4882a593Smuzhiyun	};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun	wireless-bluetooth {
225*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
226*4882a593Smuzhiyun		clocks = <&rk809 1>;
227*4882a593Smuzhiyun		clock-names = "ext_clock";
228*4882a593Smuzhiyun		uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
229*4882a593Smuzhiyun		pinctrl-names = "default","rts_gpio";
230*4882a593Smuzhiyun		pinctrl-0 = <&uart1_rts>;
231*4882a593Smuzhiyun		pinctrl-1 = <&uart1_rts_gpio>;
232*4882a593Smuzhiyun		BT,reset_gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
233*4882a593Smuzhiyun		BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
234*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
235*4882a593Smuzhiyun		status = "okay";
236*4882a593Smuzhiyun	};
237*4882a593Smuzhiyun};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun&display_subsystem {
240*4882a593Smuzhiyun	status = "okay";
241*4882a593Smuzhiyun};
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun&dsi {
244*4882a593Smuzhiyun	status = "disabled";
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun	panel@0 {
247*4882a593Smuzhiyun		compatible = "sitronix,st7703", "simple-panel-dsi";
248*4882a593Smuzhiyun		reg = <0>;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun		pinctrl-names = "default";
251*4882a593Smuzhiyun		pinctrl-0 = <&mipi_en>;
252*4882a593Smuzhiyun		enable-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun		backlight = <&backlight>;
255*4882a593Smuzhiyun		prepare-delay-ms = <0>;
256*4882a593Smuzhiyun		reset-delay-ms = <0>;
257*4882a593Smuzhiyun		init-delay-ms = <80>;
258*4882a593Smuzhiyun		enable-delay-ms = <0>;
259*4882a593Smuzhiyun		disable-delay-ms = <10>;
260*4882a593Smuzhiyun		unprepare-delay-ms = <60>;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun		width-mm = <68>;
263*4882a593Smuzhiyun		height-mm = <121>;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
266*4882a593Smuzhiyun			      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
267*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
268*4882a593Smuzhiyun		dsi,lanes = <4>;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun		panel-init-sequence = [
271*4882a593Smuzhiyun			39 00 04 ff 98 81 03
272*4882a593Smuzhiyun			15 00 02 01 00
273*4882a593Smuzhiyun			15 00 02 02 00
274*4882a593Smuzhiyun			15 00 02 03 53
275*4882a593Smuzhiyun			15 00 02 04 53
276*4882a593Smuzhiyun			15 00 02 05 13
277*4882a593Smuzhiyun			15 00 02 06 04
278*4882a593Smuzhiyun			15 00 02 07 02
279*4882a593Smuzhiyun			15 00 02 08 02
280*4882a593Smuzhiyun			15 00 02 09 00
281*4882a593Smuzhiyun			15 00 02 0a 00
282*4882a593Smuzhiyun			15 00 02 0b 00
283*4882a593Smuzhiyun			15 00 02 0c 00
284*4882a593Smuzhiyun			15 00 02 0d 00
285*4882a593Smuzhiyun			15 00 02 0e 00
286*4882a593Smuzhiyun			15 00 02 0f 00
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun			15 00 02 10 00
289*4882a593Smuzhiyun			15 00 02 11 00
290*4882a593Smuzhiyun			15 00 02 12 00
291*4882a593Smuzhiyun			15 00 02 13 00
292*4882a593Smuzhiyun			15 00 02 14 00
293*4882a593Smuzhiyun			15 00 02 15 08
294*4882a593Smuzhiyun			15 00 02 16 10
295*4882a593Smuzhiyun			15 00 02 17 00
296*4882a593Smuzhiyun			15 00 02 18 08
297*4882a593Smuzhiyun			15 00 02 19 00
298*4882a593Smuzhiyun			15 00 02 1a 00
299*4882a593Smuzhiyun			15 00 02 1b 00
300*4882a593Smuzhiyun			15 00 02 1c 00
301*4882a593Smuzhiyun			15 00 02 1d 00
302*4882a593Smuzhiyun			15 00 02 1e c0
303*4882a593Smuzhiyun			15 00 02 1f 80
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun			15 00 02 20 02
306*4882a593Smuzhiyun			15 00 02 21 09
307*4882a593Smuzhiyun			15 00 02 22 00
308*4882a593Smuzhiyun			15 00 02 23 00
309*4882a593Smuzhiyun			15 00 02 24 00
310*4882a593Smuzhiyun			15 00 02 25 00
311*4882a593Smuzhiyun			15 00 02 26 00
312*4882a593Smuzhiyun			15 00 02 27 00
313*4882a593Smuzhiyun			15 00 02 28 55
314*4882a593Smuzhiyun			15 00 02 29 03
315*4882a593Smuzhiyun			15 00 02 2a 00
316*4882a593Smuzhiyun			15 00 02 2b 00
317*4882a593Smuzhiyun			15 00 02 2c 00
318*4882a593Smuzhiyun			15 00 02 2d 00
319*4882a593Smuzhiyun			15 00 02 2e 00
320*4882a593Smuzhiyun			15 00 02 2f 00
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun			15 00 02 30 00
323*4882a593Smuzhiyun			15 00 02 31 00
324*4882a593Smuzhiyun			15 00 02 32 00
325*4882a593Smuzhiyun			15 00 02 33 00
326*4882a593Smuzhiyun			15 00 02 34 04
327*4882a593Smuzhiyun			15 00 02 35 05
328*4882a593Smuzhiyun			15 00 02 36 05
329*4882a593Smuzhiyun			15 00 02 37 00
330*4882a593Smuzhiyun			15 00 02 38 3c
331*4882a593Smuzhiyun			15 00 02 39 35
332*4882a593Smuzhiyun			15 00 02 3a 00
333*4882a593Smuzhiyun			15 00 02 3b 40
334*4882a593Smuzhiyun			15 00 02 3c 00
335*4882a593Smuzhiyun			15 00 02 3d 00
336*4882a593Smuzhiyun			15 00 02 3e 00
337*4882a593Smuzhiyun			15 00 02 3f 00
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun			15 00 02 40 00
340*4882a593Smuzhiyun			15 00 02 41 88
341*4882a593Smuzhiyun			15 00 02 42 00
342*4882a593Smuzhiyun			15 00 02 43 00
343*4882a593Smuzhiyun			15 00 02 44 1f
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun			15 00 02 50 01
346*4882a593Smuzhiyun			15 00 02 51 23
347*4882a593Smuzhiyun			15 00 02 52 45
348*4882a593Smuzhiyun			15 00 02 53 67
349*4882a593Smuzhiyun			15 00 02 54 89
350*4882a593Smuzhiyun			15 00 02 55 ab
351*4882a593Smuzhiyun			15 00 02 56 01
352*4882a593Smuzhiyun			15 00 02 57 23
353*4882a593Smuzhiyun			15 00 02 58 45
354*4882a593Smuzhiyun			15 00 02 59 67
355*4882a593Smuzhiyun			15 00 02 5a 89
356*4882a593Smuzhiyun			15 00 02 5b ab
357*4882a593Smuzhiyun			15 00 02 5c cd
358*4882a593Smuzhiyun			15 00 02 5d ef
359*4882a593Smuzhiyun			15 00 02 5e 03
360*4882a593Smuzhiyun			15 00 02 5f 14
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun			15 00 02 60 15
363*4882a593Smuzhiyun			15 00 02 61 0c
364*4882a593Smuzhiyun			15 00 02 62 0d
365*4882a593Smuzhiyun			15 00 02 63 0e
366*4882a593Smuzhiyun			15 00 02 64 0f
367*4882a593Smuzhiyun			15 00 02 65 10
368*4882a593Smuzhiyun			15 00 02 66 11
369*4882a593Smuzhiyun			15 00 02 67 08
370*4882a593Smuzhiyun			15 00 02 68 02
371*4882a593Smuzhiyun			15 00 02 69 0a
372*4882a593Smuzhiyun			15 00 02 6a 02
373*4882a593Smuzhiyun			15 00 02 6b 02
374*4882a593Smuzhiyun			15 00 02 6c 02
375*4882a593Smuzhiyun			15 00 02 6d 02
376*4882a593Smuzhiyun			15 00 02 6e 02
377*4882a593Smuzhiyun			15 00 02 6f 02
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun			15 00 02 70 02
380*4882a593Smuzhiyun			15 00 02 71 02
381*4882a593Smuzhiyun			15 00 02 72 06
382*4882a593Smuzhiyun			15 00 02 73 02
383*4882a593Smuzhiyun			15 00 02 74 02
384*4882a593Smuzhiyun			15 00 02 75 14
385*4882a593Smuzhiyun			15 00 02 76 15
386*4882a593Smuzhiyun			15 00 02 77 0f
387*4882a593Smuzhiyun			15 00 02 78 0e
388*4882a593Smuzhiyun			15 00 02 79 0d
389*4882a593Smuzhiyun			15 00 02 7a 0c
390*4882a593Smuzhiyun			15 00 02 7b 11
391*4882a593Smuzhiyun			15 00 02 7c 10
392*4882a593Smuzhiyun			15 00 02 7d 06
393*4882a593Smuzhiyun			15 00 02 7e 02
394*4882a593Smuzhiyun			15 00 02 7f 0a
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun			15 00 02 80 02
397*4882a593Smuzhiyun			15 00 02 81 02
398*4882a593Smuzhiyun			15 00 02 82 02
399*4882a593Smuzhiyun			15 00 02 83 02
400*4882a593Smuzhiyun			15 00 02 84 02
401*4882a593Smuzhiyun			15 00 02 85 02
402*4882a593Smuzhiyun			15 00 02 86 02
403*4882a593Smuzhiyun			15 00 02 87 02
404*4882a593Smuzhiyun			15 00 02 88 08
405*4882a593Smuzhiyun			15 00 02 89 02
406*4882a593Smuzhiyun			15 00 02 8a 02
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun			39 00 04 ff 98 81 04
409*4882a593Smuzhiyun			15 00 02 00 80
410*4882a593Smuzhiyun			15 00 02 70 00
411*4882a593Smuzhiyun			15 00 02 71 00
412*4882a593Smuzhiyun			15 00 02 66 fe
413*4882a593Smuzhiyun			15 00 02 82 15
414*4882a593Smuzhiyun			15 00 02 84 15
415*4882a593Smuzhiyun			15 00 02 85 15
416*4882a593Smuzhiyun			15 00 02 3a 24
417*4882a593Smuzhiyun			15 00 02 32 ac
418*4882a593Smuzhiyun			15 00 02 8c 80
419*4882a593Smuzhiyun			15 00 02 3c f5
420*4882a593Smuzhiyun			15 00 02 88 33
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun			39 00 04 ff 98 81 01
423*4882a593Smuzhiyun			15 00 02 22 0a
424*4882a593Smuzhiyun			15 00 02 31 00
425*4882a593Smuzhiyun			15 00 02 53 78
426*4882a593Smuzhiyun			15 00 02 50 5b
427*4882a593Smuzhiyun			15 00 02 51 5b
428*4882a593Smuzhiyun			15 00 02 60 20
429*4882a593Smuzhiyun			15 00 02 61 00
430*4882a593Smuzhiyun			15 00 02 62 0d
431*4882a593Smuzhiyun			15 00 02 63 00
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun			15 00 02 a0 00
434*4882a593Smuzhiyun			15 00 02 a1 10
435*4882a593Smuzhiyun			15 00 02 a2 1c
436*4882a593Smuzhiyun			15 00 02 a3 13
437*4882a593Smuzhiyun			15 00 02 a4 15
438*4882a593Smuzhiyun			15 00 02 a5 26
439*4882a593Smuzhiyun			15 00 02 a6 1a
440*4882a593Smuzhiyun			15 00 02 a7 1d
441*4882a593Smuzhiyun			15 00 02 a8 67
442*4882a593Smuzhiyun			15 00 02 a9 1c
443*4882a593Smuzhiyun			15 00 02 aa 29
444*4882a593Smuzhiyun			15 00 02 ab 5b
445*4882a593Smuzhiyun			15 00 02 ac 26
446*4882a593Smuzhiyun			15 00 02 ad 28
447*4882a593Smuzhiyun			15 00 02 ae 5c
448*4882a593Smuzhiyun			15 00 02 af 30
449*4882a593Smuzhiyun			15 00 02 b0 31
450*4882a593Smuzhiyun			15 00 02 b1 2e
451*4882a593Smuzhiyun			15 00 02 b2 32
452*4882a593Smuzhiyun			15 00 02 b3 00
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun			15 00 02 c0 00
455*4882a593Smuzhiyun			15 00 02 c1 10
456*4882a593Smuzhiyun			15 00 02 c2 1c
457*4882a593Smuzhiyun			15 00 02 c3 13
458*4882a593Smuzhiyun			15 00 02 c4 15
459*4882a593Smuzhiyun			15 00 02 c5 26
460*4882a593Smuzhiyun			15 00 02 c6 1a
461*4882a593Smuzhiyun			15 00 02 c7 1d
462*4882a593Smuzhiyun			15 00 02 c8 67
463*4882a593Smuzhiyun			15 00 02 c9 1c
464*4882a593Smuzhiyun			15 00 02 ca 29
465*4882a593Smuzhiyun			15 00 02 cb 5b
466*4882a593Smuzhiyun			15 00 02 cc 26
467*4882a593Smuzhiyun			15 00 02 cd 28
468*4882a593Smuzhiyun			15 00 02 ce 5c
469*4882a593Smuzhiyun			15 00 02 cf 30
470*4882a593Smuzhiyun			15 00 02 d0 31
471*4882a593Smuzhiyun			15 00 02 d1 2e
472*4882a593Smuzhiyun			15 00 02 d2 32
473*4882a593Smuzhiyun			15 00 02 d3 00
474*4882a593Smuzhiyun			39 00 04 ff 98 81 00
475*4882a593Smuzhiyun			05 00 01 11
476*4882a593Smuzhiyun			05 01 01 29
477*4882a593Smuzhiyun		];
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun		panel-exit-sequence = [
480*4882a593Smuzhiyun			05 00 01 28
481*4882a593Smuzhiyun			05 00 01 10
482*4882a593Smuzhiyun		];
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun		display-timings {
485*4882a593Smuzhiyun			native-mode = <&timing0>;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun			timing0: timing0 {
488*4882a593Smuzhiyun				clock-frequency = <64000000>;
489*4882a593Smuzhiyun				hactive = <720>;
490*4882a593Smuzhiyun				vactive = <1280>;
491*4882a593Smuzhiyun				hfront-porch = <40>;
492*4882a593Smuzhiyun				hsync-len = <10>;
493*4882a593Smuzhiyun				hback-porch = <40>;
494*4882a593Smuzhiyun				vfront-porch = <22>;
495*4882a593Smuzhiyun				vsync-len = <4>;
496*4882a593Smuzhiyun				vback-porch = <11>;
497*4882a593Smuzhiyun				hsync-active = <0>;
498*4882a593Smuzhiyun				vsync-active = <0>;
499*4882a593Smuzhiyun				de-active = <0>;
500*4882a593Smuzhiyun				pixelclk-active = <0>;
501*4882a593Smuzhiyun			};
502*4882a593Smuzhiyun		};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun		ports {
505*4882a593Smuzhiyun			#address-cells = <1>;
506*4882a593Smuzhiyun			#size-cells = <0>;
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun			port@0 {
509*4882a593Smuzhiyun				reg = <0>;
510*4882a593Smuzhiyun				panel_in_dsi: endpoint {
511*4882a593Smuzhiyun					remote-endpoint = <&dsi_out_panel>;
512*4882a593Smuzhiyun				};
513*4882a593Smuzhiyun			};
514*4882a593Smuzhiyun		};
515*4882a593Smuzhiyun	};
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun	ports {
518*4882a593Smuzhiyun		#address-cells = <1>;
519*4882a593Smuzhiyun		#size-cells = <0>;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun		port@1 {
522*4882a593Smuzhiyun			reg = <1>;
523*4882a593Smuzhiyun			dsi_out_panel: endpoint {
524*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi>;
525*4882a593Smuzhiyun			};
526*4882a593Smuzhiyun		};
527*4882a593Smuzhiyun	};
528*4882a593Smuzhiyun};
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun&dsi_in_vopb {
531*4882a593Smuzhiyun	status = "disabled";
532*4882a593Smuzhiyun};
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun&dsi_in_vopl {
535*4882a593Smuzhiyun	status = "disabled";
536*4882a593Smuzhiyun};
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun&route_dsi {
539*4882a593Smuzhiyun	connect = <&vopb_out_dsi>;
540*4882a593Smuzhiyun	status = "disabled";
541*4882a593Smuzhiyun};
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun&rgb {
544*4882a593Smuzhiyun	status = "okay";
545*4882a593Smuzhiyun	#address-cells = <1>;
546*4882a593Smuzhiyun	#size-cells = <0>;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun	/delete-property/ phys;
549*4882a593Smuzhiyun	/delete-property/ phy-names;
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun	pinctrl-0 = <&lcdc_m0_rgb_pins>;
552*4882a593Smuzhiyun	pinctrl-1 = <&lcdc_m0_sleep_pins>;
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun	ports {
555*4882a593Smuzhiyun		port@1 {
556*4882a593Smuzhiyun			reg = <1>;
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun			rgb_out_panel: endpoint {
559*4882a593Smuzhiyun				remote-endpoint = <&panel_in_rgb>;
560*4882a593Smuzhiyun			};
561*4882a593Smuzhiyun		};
562*4882a593Smuzhiyun	};
563*4882a593Smuzhiyun};
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun&rgb_in_vopb {
566*4882a593Smuzhiyun	status = "okay";
567*4882a593Smuzhiyun};
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun&rgb_in_vopl {
570*4882a593Smuzhiyun	status = "disabled";
571*4882a593Smuzhiyun};
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun&route_rgb {
574*4882a593Smuzhiyun	connect = <&vopb_out_rgb>;
575*4882a593Smuzhiyun	status = "okay";
576*4882a593Smuzhiyun};
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun&cpu0 {
579*4882a593Smuzhiyun	cpu-supply = <&vdd_arm>;
580*4882a593Smuzhiyun};
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun&dfi {
583*4882a593Smuzhiyun	status = "okay";
584*4882a593Smuzhiyun};
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun&dmc {
587*4882a593Smuzhiyun	center-supply = <&vdd_logic>;
588*4882a593Smuzhiyun	status = "okay";
589*4882a593Smuzhiyun};
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun&emmc {
592*4882a593Smuzhiyun	bus-width = <8>;
593*4882a593Smuzhiyun	cap-mmc-highspeed;
594*4882a593Smuzhiyun	mmc-hs200-1_8v;
595*4882a593Smuzhiyun	supports-emmc;
596*4882a593Smuzhiyun	disable-wp;
597*4882a593Smuzhiyun	non-removable;
598*4882a593Smuzhiyun	num-slots = <1>;
599*4882a593Smuzhiyun	status = "okay";
600*4882a593Smuzhiyun};
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun&gpu {
603*4882a593Smuzhiyun	mali-supply = <&vdd_logic>;
604*4882a593Smuzhiyun	status = "okay";
605*4882a593Smuzhiyun};
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun&i2c0 {
608*4882a593Smuzhiyun	status = "okay";
609*4882a593Smuzhiyun	clock-frequency = <400000>;
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun	rk809: pmic@20 {
612*4882a593Smuzhiyun		compatible = "rockchip,rk809";
613*4882a593Smuzhiyun		reg = <0x20>;
614*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
615*4882a593Smuzhiyun		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
616*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-sleep",
617*4882a593Smuzhiyun				"pmic-power-off", "pmic-reset";
618*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int>;
619*4882a593Smuzhiyun		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
620*4882a593Smuzhiyun		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
621*4882a593Smuzhiyun		pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
622*4882a593Smuzhiyun		rockchip,system-power-controller;
623*4882a593Smuzhiyun		wakeup-source;
624*4882a593Smuzhiyun		#clock-cells = <1>;
625*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
626*4882a593Smuzhiyun		//fb-inner-reg-idxs = <2>;
627*4882a593Smuzhiyun		/* 1: rst regs (default in codes), 0: rst the pmic */
628*4882a593Smuzhiyun		pmic-reset-func = <1>;
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun		vcc1-supply = <&vcc5v0_sys>;
631*4882a593Smuzhiyun		vcc2-supply = <&vcc5v0_sys>;
632*4882a593Smuzhiyun		vcc3-supply = <&vcc5v0_sys>;
633*4882a593Smuzhiyun		vcc4-supply = <&vcc5v0_sys>;
634*4882a593Smuzhiyun		vcc5-supply = <&vcc3v3_sys>;
635*4882a593Smuzhiyun		vcc6-supply = <&vcc3v3_sys>;
636*4882a593Smuzhiyun		vcc7-supply = <&vcc3v3_sys>;
637*4882a593Smuzhiyun		vcc8-supply = <&vcc3v3_sys>;
638*4882a593Smuzhiyun		vcc9-supply = <&vcc5v0_sys>;
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun		pwrkey {
641*4882a593Smuzhiyun			status = "okay";
642*4882a593Smuzhiyun		};
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
645*4882a593Smuzhiyun			gpio-controller;
646*4882a593Smuzhiyun			#gpio-cells = <2>;
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun			rk817_slppin_null: rk817_slppin_null {
649*4882a593Smuzhiyun				pins = "gpio_slp";
650*4882a593Smuzhiyun				function = "pin_fun0";
651*4882a593Smuzhiyun			};
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun			rk817_slppin_slp: rk817_slppin_slp {
654*4882a593Smuzhiyun				pins = "gpio_slp";
655*4882a593Smuzhiyun				function = "pin_fun1";
656*4882a593Smuzhiyun			};
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
659*4882a593Smuzhiyun				pins = "gpio_slp";
660*4882a593Smuzhiyun				function = "pin_fun2";
661*4882a593Smuzhiyun			};
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun			rk817_slppin_rst: rk817_slppin_rst {
664*4882a593Smuzhiyun				pins = "gpio_slp";
665*4882a593Smuzhiyun				function = "pin_fun3";
666*4882a593Smuzhiyun			};
667*4882a593Smuzhiyun		};
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun		regulators {
670*4882a593Smuzhiyun			vdd_logic: DCDC_REG1 {
671*4882a593Smuzhiyun				regulator-always-on;
672*4882a593Smuzhiyun				regulator-boot-on;
673*4882a593Smuzhiyun				regulator-min-microvolt = <950000>;
674*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
675*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
676*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
677*4882a593Smuzhiyun				regulator-name = "vdd_logic";
678*4882a593Smuzhiyun				regulator-state-mem {
679*4882a593Smuzhiyun					regulator-on-in-suspend;
680*4882a593Smuzhiyun					regulator-suspend-microvolt = <950000>;
681*4882a593Smuzhiyun				};
682*4882a593Smuzhiyun			};
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun			vdd_arm: DCDC_REG2 {
685*4882a593Smuzhiyun				regulator-always-on;
686*4882a593Smuzhiyun				regulator-boot-on;
687*4882a593Smuzhiyun				regulator-min-microvolt = <950000>;
688*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
689*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
690*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
691*4882a593Smuzhiyun				regulator-name = "vdd_arm";
692*4882a593Smuzhiyun				regulator-state-mem {
693*4882a593Smuzhiyun					regulator-off-in-suspend;
694*4882a593Smuzhiyun					regulator-suspend-microvolt = <950000>;
695*4882a593Smuzhiyun				};
696*4882a593Smuzhiyun			};
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
699*4882a593Smuzhiyun				regulator-always-on;
700*4882a593Smuzhiyun				regulator-boot-on;
701*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
702*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
703*4882a593Smuzhiyun				regulator-state-mem {
704*4882a593Smuzhiyun					regulator-on-in-suspend;
705*4882a593Smuzhiyun				};
706*4882a593Smuzhiyun			};
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun			vcc_3v3: DCDC_REG4 {
709*4882a593Smuzhiyun				regulator-always-on;
710*4882a593Smuzhiyun				regulator-boot-on;
711*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
712*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
713*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
714*4882a593Smuzhiyun				regulator-name = "vcc_3v3";
715*4882a593Smuzhiyun				regulator-state-mem {
716*4882a593Smuzhiyun					regulator-on-in-suspend;
717*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
718*4882a593Smuzhiyun				};
719*4882a593Smuzhiyun			};
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun			vcc_1v0: LDO_REG1 {
722*4882a593Smuzhiyun				regulator-always-on;
723*4882a593Smuzhiyun				regulator-boot-on;
724*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
725*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
726*4882a593Smuzhiyun				regulator-name = "vcc_1v0";
727*4882a593Smuzhiyun				regulator-state-mem {
728*4882a593Smuzhiyun					regulator-on-in-suspend;
729*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
730*4882a593Smuzhiyun				};
731*4882a593Smuzhiyun			};
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun			vcc_1v8: LDO_REG2 {
734*4882a593Smuzhiyun				regulator-always-on;
735*4882a593Smuzhiyun				regulator-boot-on;
736*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
737*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
740*4882a593Smuzhiyun				regulator-state-mem {
741*4882a593Smuzhiyun					regulator-on-in-suspend;
742*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
743*4882a593Smuzhiyun				};
744*4882a593Smuzhiyun			};
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun			vdd_1v0: LDO_REG3 {
747*4882a593Smuzhiyun				regulator-always-on;
748*4882a593Smuzhiyun				regulator-boot-on;
749*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
750*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun				regulator-name = "vdd_1v0";
753*4882a593Smuzhiyun				regulator-state-mem {
754*4882a593Smuzhiyun					regulator-on-in-suspend;
755*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
756*4882a593Smuzhiyun				};
757*4882a593Smuzhiyun			};
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun			vcc3v3_pmu: LDO_REG4 {
760*4882a593Smuzhiyun				regulator-always-on;
761*4882a593Smuzhiyun				regulator-boot-on;
762*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
763*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun				regulator-name = "vcc3v3_pmu";
766*4882a593Smuzhiyun				regulator-state-mem {
767*4882a593Smuzhiyun					regulator-on-in-suspend;
768*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun				};
771*4882a593Smuzhiyun			};
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun			vccio_sd: LDO_REG5 {
774*4882a593Smuzhiyun				regulator-always-on;
775*4882a593Smuzhiyun				regulator-boot-on;
776*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
777*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun				regulator-name = "vccio_sd";
780*4882a593Smuzhiyun				regulator-state-mem {
781*4882a593Smuzhiyun					regulator-on-in-suspend;
782*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
783*4882a593Smuzhiyun				};
784*4882a593Smuzhiyun			};
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun			vcc_sd: LDO_REG6 {
787*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
788*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
789*4882a593Smuzhiyun				regulator-boot-off;
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun				regulator-name = "vcc_sd";
792*4882a593Smuzhiyun				regulator-state-mem {
793*4882a593Smuzhiyun					regulator-off-in-suspend;
794*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun				};
797*4882a593Smuzhiyun			};
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun			vcc2v8_dvp: LDO_REG7 {
800*4882a593Smuzhiyun				regulator-boot-on;
801*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
802*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun				regulator-name = "vcc2v8_dvp";
805*4882a593Smuzhiyun				regulator-state-mem {
806*4882a593Smuzhiyun					regulator-off-in-suspend;
807*4882a593Smuzhiyun					regulator-suspend-microvolt = <2800000>;
808*4882a593Smuzhiyun				};
809*4882a593Smuzhiyun			};
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun			vcc1v8_dvp: LDO_REG8 {
812*4882a593Smuzhiyun				regulator-boot-on;
813*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
814*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun				regulator-name = "vcc1v8_dvp";
817*4882a593Smuzhiyun				regulator-state-mem {
818*4882a593Smuzhiyun					regulator-on-in-suspend;
819*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
820*4882a593Smuzhiyun				};
821*4882a593Smuzhiyun			};
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun			vdd1v5_dvp: LDO_REG9 {
824*4882a593Smuzhiyun				regulator-boot-on;
825*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
826*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun				regulator-name = "vdd1v5_dvp";
829*4882a593Smuzhiyun				regulator-state-mem {
830*4882a593Smuzhiyun					regulator-off-in-suspend;
831*4882a593Smuzhiyun					regulator-suspend-microvolt = <1500000>;
832*4882a593Smuzhiyun				};
833*4882a593Smuzhiyun			};
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun			vcc3v3_sys: DCDC_REG5 {
836*4882a593Smuzhiyun				regulator-always-on;
837*4882a593Smuzhiyun				regulator-boot-on;
838*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
839*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
840*4882a593Smuzhiyun				regulator-name = "vcc3v3_sys";
841*4882a593Smuzhiyun				regulator-state-mem {
842*4882a593Smuzhiyun					regulator-on-in-suspend;
843*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
844*4882a593Smuzhiyun				};
845*4882a593Smuzhiyun			};
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun			vcc5v0_host: SWITCH_REG1 {
848*4882a593Smuzhiyun				regulator-always-on;
849*4882a593Smuzhiyun				regulator-boot-on;
850*4882a593Smuzhiyun				regulator-name = "vcc5v0_host";
851*4882a593Smuzhiyun			};
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun			vcc3v3_lcd: SWITCH_REG2 {
854*4882a593Smuzhiyun				regulator-boot-on;
855*4882a593Smuzhiyun				regulator-name = "vcc3v3_lcd";
856*4882a593Smuzhiyun			};
857*4882a593Smuzhiyun		};
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun		rk809_codec: codec {
860*4882a593Smuzhiyun			#sound-dai-cells = <0>;
861*4882a593Smuzhiyun			compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
862*4882a593Smuzhiyun			clocks = <&cru SCLK_I2S1_OUT>;
863*4882a593Smuzhiyun			clock-names = "mclk";
864*4882a593Smuzhiyun			pinctrl-names = "default";
865*4882a593Smuzhiyun			pinctrl-0 = <&i2s1_2ch_mclk>;
866*4882a593Smuzhiyun			hp-volume = <20>;
867*4882a593Smuzhiyun			spk-volume = <3>;
868*4882a593Smuzhiyun			status = "okay";
869*4882a593Smuzhiyun		};
870*4882a593Smuzhiyun	};
871*4882a593Smuzhiyun};
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun&i2c1 {
874*4882a593Smuzhiyun	status = "okay";
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun	clock-frequency = <400000>;
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun	/* These are relatively safe rise/fall times; TODO: measure */
879*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <50>;
880*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <300>;
881*4882a593Smuzhiyun};
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun&i2s1_2ch {
884*4882a593Smuzhiyun	status = "okay";
885*4882a593Smuzhiyun	#sound-dai-cells = <0>;
886*4882a593Smuzhiyun};
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun&io_domains {
889*4882a593Smuzhiyun	status = "okay";
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun	vccio1-supply = <&vcc_3v3>;
892*4882a593Smuzhiyun	vccio2-supply = <&vcc_3v3>;
893*4882a593Smuzhiyun	vccio3-supply = <&vcc_3v3>;
894*4882a593Smuzhiyun	vccio4-supply = <&vcc3v3_pmu>;
895*4882a593Smuzhiyun	vccio5-supply = <&vcc_1v8>;
896*4882a593Smuzhiyun};
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun&isp_mmu {
899*4882a593Smuzhiyun	status = "okay";
900*4882a593Smuzhiyun};
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun&mipi_dphy_rx0 {
903*4882a593Smuzhiyun	status = "okay";
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun	ports {
906*4882a593Smuzhiyun		#address-cells = <1>;
907*4882a593Smuzhiyun		#size-cells = <0>;
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun		port@0 {
910*4882a593Smuzhiyun			reg = <0>;
911*4882a593Smuzhiyun			#address-cells = <1>;
912*4882a593Smuzhiyun			#size-cells = <0>;
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun			mipi_in_ucam: endpoint@1 {
915*4882a593Smuzhiyun				reg = <1>;
916*4882a593Smuzhiyun			//	remote-endpoint = <&ucam_out>;
917*4882a593Smuzhiyun				data-lanes = <1 2>;
918*4882a593Smuzhiyun			};
919*4882a593Smuzhiyun		};
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun		port@1 {
922*4882a593Smuzhiyun			reg = <1>;
923*4882a593Smuzhiyun			#address-cells = <1>;
924*4882a593Smuzhiyun			#size-cells = <0>;
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun			dphy_rx0_out: endpoint@0 {
927*4882a593Smuzhiyun				reg = <0>;
928*4882a593Smuzhiyun				remote-endpoint = <&isp0_mipi_in>;
929*4882a593Smuzhiyun			};
930*4882a593Smuzhiyun		};
931*4882a593Smuzhiyun	};
932*4882a593Smuzhiyun};
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun&pmu_io_domains {
935*4882a593Smuzhiyun	status = "okay";
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun	pmuio1-supply = <&vcc3v3_pmu>;
938*4882a593Smuzhiyun	pmuio2-supply = <&vcc3v3_pmu>;
939*4882a593Smuzhiyun};
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun&pwm1 {
942*4882a593Smuzhiyun	status = "okay";
943*4882a593Smuzhiyun};
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun&pwm3 {
946*4882a593Smuzhiyun	status = "okay";
947*4882a593Smuzhiyun};
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun&rk_rga {
950*4882a593Smuzhiyun	status = "okay";
951*4882a593Smuzhiyun};
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun&rkisp1 {
954*4882a593Smuzhiyun	status = "okay";
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun	port {
957*4882a593Smuzhiyun		#address-cells = <1>;
958*4882a593Smuzhiyun		#size-cells = <0>;
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun		isp0_mipi_in: endpoint@0 {
961*4882a593Smuzhiyun			reg = <0>;
962*4882a593Smuzhiyun			remote-endpoint = <&dphy_rx0_out>;
963*4882a593Smuzhiyun		};
964*4882a593Smuzhiyun	};
965*4882a593Smuzhiyun};
966*4882a593Smuzhiyun
967*4882a593Smuzhiyun&saradc {
968*4882a593Smuzhiyun	status = "okay";
969*4882a593Smuzhiyun	vref-supply = <&vcc_1v8>;
970*4882a593Smuzhiyun};
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun&sdio {
973*4882a593Smuzhiyun	bus-width = <4>;
974*4882a593Smuzhiyun	cap-sd-highspeed;
975*4882a593Smuzhiyun	supports-sdio;
976*4882a593Smuzhiyun	ignore-pm-notify;
977*4882a593Smuzhiyun	keep-power-in-suspend;
978*4882a593Smuzhiyun	non-removable;
979*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
980*4882a593Smuzhiyun	sd-uhs-sdr104;
981*4882a593Smuzhiyun	status = "okay";
982*4882a593Smuzhiyun};
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun&tsadc {
985*4882a593Smuzhiyun	pinctrl-names = "gpio", "otpout";
986*4882a593Smuzhiyun	pinctrl-0 = <&tsadc_otp_gpio>;
987*4882a593Smuzhiyun	pinctrl-1 = <&tsadc_otp_out>;
988*4882a593Smuzhiyun	status = "okay";
989*4882a593Smuzhiyun};
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun&uart1 {
992*4882a593Smuzhiyun	pinctrl-names = "default";
993*4882a593Smuzhiyun	pinctrl-0 = <&uart1_xfer &uart1_cts>;
994*4882a593Smuzhiyun	status = "okay";
995*4882a593Smuzhiyun};
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun&u2phy {
998*4882a593Smuzhiyun	status = "okay";
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun	u2phy_host: host-port {
1001*4882a593Smuzhiyun		status = "okay";
1002*4882a593Smuzhiyun		phy-supply = <&vcc5v0_host>;
1003*4882a593Smuzhiyun	};
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun	u2phy_otg: otg-port {
1006*4882a593Smuzhiyun		status = "okay";
1007*4882a593Smuzhiyun	};
1008*4882a593Smuzhiyun};
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun&usb20_otg {
1011*4882a593Smuzhiyun	status = "okay";
1012*4882a593Smuzhiyun};
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun&usb_host0_ehci {
1015*4882a593Smuzhiyun	status = "okay";
1016*4882a593Smuzhiyun};
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun&usb_host0_ohci {
1019*4882a593Smuzhiyun	status = "okay";
1020*4882a593Smuzhiyun};
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun&vopb {
1023*4882a593Smuzhiyun	status = "okay";
1024*4882a593Smuzhiyun};
1025*4882a593Smuzhiyun
1026*4882a593Smuzhiyun&vopb_mmu {
1027*4882a593Smuzhiyun	status = "okay";
1028*4882a593Smuzhiyun};
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun&vopl {
1031*4882a593Smuzhiyun	status = "okay";
1032*4882a593Smuzhiyun};
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun&vopl_mmu {
1035*4882a593Smuzhiyun	status = "okay";
1036*4882a593Smuzhiyun};
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun&mpp_srv {
1039*4882a593Smuzhiyun	status = "okay";
1040*4882a593Smuzhiyun};
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun&vdpu {
1043*4882a593Smuzhiyun	status = "okay";
1044*4882a593Smuzhiyun};
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun&vepu {
1047*4882a593Smuzhiyun	status = "okay";
1048*4882a593Smuzhiyun};
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun&vpu_mmu {
1051*4882a593Smuzhiyun	status = "okay";
1052*4882a593Smuzhiyun};
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun&hevc {
1055*4882a593Smuzhiyun	status = "okay";
1056*4882a593Smuzhiyun};
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun&hevc_mmu {
1059*4882a593Smuzhiyun	status = "okay";
1060*4882a593Smuzhiyun};
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun&pinctrl {
1063*4882a593Smuzhiyun	lcd {
1064*4882a593Smuzhiyun		lcd0_pwren: lcd0-pwren {
1065*4882a593Smuzhiyun			rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_output_high>;
1066*4882a593Smuzhiyun		};
1067*4882a593Smuzhiyun		lcd0_rst: lcd0-rst {
1068*4882a593Smuzhiyun			rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_output_high>;
1069*4882a593Smuzhiyun		};
1070*4882a593Smuzhiyun		mipi_en: mipi-en {
1071*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
1072*4882a593Smuzhiyun		};
1073*4882a593Smuzhiyun		pwdn_rgb: pwdn-rgb {
1074*4882a593Smuzhiyun			rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>;
1075*4882a593Smuzhiyun		};
1076*4882a593Smuzhiyun	};
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun	pmic {
1079*4882a593Smuzhiyun		pmic_int: pmic_int {
1080*4882a593Smuzhiyun			rockchip,pins =
1081*4882a593Smuzhiyun				<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
1082*4882a593Smuzhiyun		};
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun		soc_slppin_gpio: soc_slppin_gpio {
1085*4882a593Smuzhiyun			rockchip,pins =
1086*4882a593Smuzhiyun				<0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
1087*4882a593Smuzhiyun		};
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun		soc_slppin_slp: soc_slppin_slp {
1090*4882a593Smuzhiyun			rockchip,pins =
1091*4882a593Smuzhiyun				<0 RK_PA4 1 &pcfg_pull_none>;
1092*4882a593Smuzhiyun		};
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun		soc_slppin_rst: soc_slppin_rst {
1095*4882a593Smuzhiyun			rockchip,pins =
1096*4882a593Smuzhiyun				<0 RK_PA4 2 &pcfg_pull_none>;
1097*4882a593Smuzhiyun		};
1098*4882a593Smuzhiyun	};
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun	sdio-pwrseq {
1101*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
1102*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1103*4882a593Smuzhiyun		};
1104*4882a593Smuzhiyun	};
1105*4882a593Smuzhiyun};
1106