xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3358-evb-ddr3.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
9*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
10*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
11*4882a593Smuzhiyun#include "rk3358.dtsi"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	adc-keys {
15*4882a593Smuzhiyun		compatible = "adc-keys";
16*4882a593Smuzhiyun		io-channels = <&saradc 2>;
17*4882a593Smuzhiyun		io-channel-names = "buttons";
18*4882a593Smuzhiyun		poll-interval = <100>;
19*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun		esc-key {
22*4882a593Smuzhiyun			linux,code = <KEY_ESC>;
23*4882a593Smuzhiyun			label = "esc";
24*4882a593Smuzhiyun			press-threshold-microvolt = <1310000>;
25*4882a593Smuzhiyun		};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		home-key {
28*4882a593Smuzhiyun			linux,code = <KEY_HOME>;
29*4882a593Smuzhiyun			label = "home";
30*4882a593Smuzhiyun			press-threshold-microvolt = <624000>;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun		menu-key {
34*4882a593Smuzhiyun			linux,code = <KEY_MENU>;
35*4882a593Smuzhiyun			label = "menu";
36*4882a593Smuzhiyun			press-threshold-microvolt = <987000>;
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun		vol-down-key {
40*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
41*4882a593Smuzhiyun			label = "volume down";
42*4882a593Smuzhiyun			press-threshold-microvolt = <300000>;
43*4882a593Smuzhiyun		};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		vol-up-key {
46*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
47*4882a593Smuzhiyun			label = "volume up";
48*4882a593Smuzhiyun			press-threshold-microvolt = <17000>;
49*4882a593Smuzhiyun		};
50*4882a593Smuzhiyun	};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun	backlight: backlight {
53*4882a593Smuzhiyun		compatible = "pwm-backlight";
54*4882a593Smuzhiyun		pwms = <&pwm1 0 25000 0>;
55*4882a593Smuzhiyun		brightness-levels = <
56*4882a593Smuzhiyun			  0   1   2   3   4   5   6   7
57*4882a593Smuzhiyun			  8   9  10  11  12  13  14  15
58*4882a593Smuzhiyun			 16  17  18  19  20  21  22  23
59*4882a593Smuzhiyun			 24  25  26  27  28  29  30  31
60*4882a593Smuzhiyun			 32  33  34  35  36  37  38  39
61*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
62*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
63*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
64*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
65*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
66*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
67*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
68*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
69*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
70*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
71*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
72*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
73*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
74*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
75*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
76*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
77*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
78*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
79*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
80*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
81*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
82*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
83*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
84*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
85*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
86*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
87*4882a593Smuzhiyun			248 249 250 251 252 253 254 255>;
88*4882a593Smuzhiyun		default-brightness-level = <200>;
89*4882a593Smuzhiyun	};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun	charge-animation {
92*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
93*4882a593Smuzhiyun		rockchip,uboot-charge-on = <0>;
94*4882a593Smuzhiyun		rockchip,android-charge-on = <1>;
95*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <3500>;
96*4882a593Smuzhiyun		rockchip,screen-on-voltage = <3600>;
97*4882a593Smuzhiyun		status = "okay";
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	rk809_sound: rk809-sound {
101*4882a593Smuzhiyun		status = "okay";
102*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
103*4882a593Smuzhiyun		rockchip,card-name = "rockchip-rk809";
104*4882a593Smuzhiyun		hp-det-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
105*4882a593Smuzhiyun		io-channels = <&saradc 1>;
106*4882a593Smuzhiyun		io-channel-names = "adc-detect";
107*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
108*4882a593Smuzhiyun		poll-interval = <100>;
109*4882a593Smuzhiyun		rockchip,format = "i2s";
110*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
111*4882a593Smuzhiyun		rockchip,cpu = <&i2s1_2ch>;
112*4882a593Smuzhiyun		rockchip,codec = <&rk809_codec>;
113*4882a593Smuzhiyun		pinctrl-names = "default";
114*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
115*4882a593Smuzhiyun		play-pause-key {
116*4882a593Smuzhiyun			label = "playpause";
117*4882a593Smuzhiyun			linux,code = <KEY_PLAYPAUSE>;
118*4882a593Smuzhiyun			press-threshold-microvolt = <2000>;
119*4882a593Smuzhiyun		};
120*4882a593Smuzhiyun	};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
123*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
124*4882a593Smuzhiyun		/*clocks = <&rk809 1>;*/
125*4882a593Smuzhiyun		/*clock-names = "ext_clock";*/
126*4882a593Smuzhiyun		pinctrl-names = "default";
127*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun		/*
130*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
131*4882a593Smuzhiyun		 * on the actual card populated):
132*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
133*4882a593Smuzhiyun		 * - PDN (power down when low)
134*4882a593Smuzhiyun		 */
135*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
136*4882a593Smuzhiyun	};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun	vcc_phy: vcc-phy-regulator {
139*4882a593Smuzhiyun		compatible = "regulator-fixed";
140*4882a593Smuzhiyun		regulator-name = "vcc_phy";
141*4882a593Smuzhiyun		regulator-always-on;
142*4882a593Smuzhiyun		regulator-boot-on;
143*4882a593Smuzhiyun	};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun	vcc5v0_sys: vccsys {
146*4882a593Smuzhiyun		compatible = "regulator-fixed";
147*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
148*4882a593Smuzhiyun		regulator-always-on;
149*4882a593Smuzhiyun		regulator-boot-on;
150*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
151*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
152*4882a593Smuzhiyun	};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun	vcc5v0_host_vbus: vcc5v0-host-regulator {
155*4882a593Smuzhiyun		compatible = "regulator-fixed";
156*4882a593Smuzhiyun		gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
157*4882a593Smuzhiyun		pinctrl-names = "default";
158*4882a593Smuzhiyun		pinctrl-0 = <&host_vbus_drv>;
159*4882a593Smuzhiyun		regulator-name = "vcc5v0_host_vbus";
160*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
161*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
162*4882a593Smuzhiyun		regulator-always-on;
163*4882a593Smuzhiyun		enable-active-high;
164*4882a593Smuzhiyun	};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun	wireless-wlan {
167*4882a593Smuzhiyun		compatible = "wlan-platdata";
168*4882a593Smuzhiyun		wifi_chip_type = "AP6210";
169*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
170*4882a593Smuzhiyun		status = "okay";
171*4882a593Smuzhiyun	};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun	wireless-bluetooth {
174*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
175*4882a593Smuzhiyun		clocks = <&rk809 1>;
176*4882a593Smuzhiyun		clock-names = "ext_clock";
177*4882a593Smuzhiyun		uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
178*4882a593Smuzhiyun		pinctrl-names = "default","rts_gpio";
179*4882a593Smuzhiyun		pinctrl-0 = <&uart1_rts>;
180*4882a593Smuzhiyun		pinctrl-1 = <&uart1_rts_gpio>;
181*4882a593Smuzhiyun		BT,reset_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
182*4882a593Smuzhiyun		BT,wake_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
183*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
184*4882a593Smuzhiyun		status = "okay";
185*4882a593Smuzhiyun	};
186*4882a593Smuzhiyun};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun&display_subsystem {
189*4882a593Smuzhiyun	status = "okay";
190*4882a593Smuzhiyun};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun&dsi {
193*4882a593Smuzhiyun	status = "okay";
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun	panel@0 {
196*4882a593Smuzhiyun		compatible = "sitronix,st7703", "simple-panel-dsi";
197*4882a593Smuzhiyun		reg = <0>;
198*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd>;
199*4882a593Smuzhiyun		backlight = <&backlight>;
200*4882a593Smuzhiyun		prepare-delay-ms = <0>;
201*4882a593Smuzhiyun		reset-delay-ms = <0>;
202*4882a593Smuzhiyun		init-delay-ms = <80>;
203*4882a593Smuzhiyun		enable-delay-ms = <0>;
204*4882a593Smuzhiyun		disable-delay-ms = <10>;
205*4882a593Smuzhiyun		unprepare-delay-ms = <60>;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun		width-mm = <68>;
208*4882a593Smuzhiyun		height-mm = <121>;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
211*4882a593Smuzhiyun			      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
212*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
213*4882a593Smuzhiyun		dsi,lanes = <4>;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun		panel-init-sequence = [
216*4882a593Smuzhiyun			39 00 04 ff 98 81 03
217*4882a593Smuzhiyun			15 00 02 01 00
218*4882a593Smuzhiyun			15 00 02 02 00
219*4882a593Smuzhiyun			15 00 02 03 53
220*4882a593Smuzhiyun			15 00 02 04 53
221*4882a593Smuzhiyun			15 00 02 05 13
222*4882a593Smuzhiyun			15 00 02 06 04
223*4882a593Smuzhiyun			15 00 02 07 02
224*4882a593Smuzhiyun			15 00 02 08 02
225*4882a593Smuzhiyun			15 00 02 09 00
226*4882a593Smuzhiyun			15 00 02 0a 00
227*4882a593Smuzhiyun			15 00 02 0b 00
228*4882a593Smuzhiyun			15 00 02 0c 00
229*4882a593Smuzhiyun			15 00 02 0d 00
230*4882a593Smuzhiyun			15 00 02 0e 00
231*4882a593Smuzhiyun			15 00 02 0f 00
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun			15 00 02 10 00
234*4882a593Smuzhiyun			15 00 02 11 00
235*4882a593Smuzhiyun			15 00 02 12 00
236*4882a593Smuzhiyun			15 00 02 13 00
237*4882a593Smuzhiyun			15 00 02 14 00
238*4882a593Smuzhiyun			15 00 02 15 08
239*4882a593Smuzhiyun			15 00 02 16 10
240*4882a593Smuzhiyun			15 00 02 17 00
241*4882a593Smuzhiyun			15 00 02 18 08
242*4882a593Smuzhiyun			15 00 02 19 00
243*4882a593Smuzhiyun			15 00 02 1a 00
244*4882a593Smuzhiyun			15 00 02 1b 00
245*4882a593Smuzhiyun			15 00 02 1c 00
246*4882a593Smuzhiyun			15 00 02 1d 00
247*4882a593Smuzhiyun			15 00 02 1e c0
248*4882a593Smuzhiyun			15 00 02 1f 80
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun			15 00 02 20 02
251*4882a593Smuzhiyun			15 00 02 21 09
252*4882a593Smuzhiyun			15 00 02 22 00
253*4882a593Smuzhiyun			15 00 02 23 00
254*4882a593Smuzhiyun			15 00 02 24 00
255*4882a593Smuzhiyun			15 00 02 25 00
256*4882a593Smuzhiyun			15 00 02 26 00
257*4882a593Smuzhiyun			15 00 02 27 00
258*4882a593Smuzhiyun			15 00 02 28 55
259*4882a593Smuzhiyun			15 00 02 29 03
260*4882a593Smuzhiyun			15 00 02 2a 00
261*4882a593Smuzhiyun			15 00 02 2b 00
262*4882a593Smuzhiyun			15 00 02 2c 00
263*4882a593Smuzhiyun			15 00 02 2d 00
264*4882a593Smuzhiyun			15 00 02 2e 00
265*4882a593Smuzhiyun			15 00 02 2f 00
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun			15 00 02 30 00
268*4882a593Smuzhiyun			15 00 02 31 00
269*4882a593Smuzhiyun			15 00 02 32 00
270*4882a593Smuzhiyun			15 00 02 33 00
271*4882a593Smuzhiyun			15 00 02 34 04
272*4882a593Smuzhiyun			15 00 02 35 05
273*4882a593Smuzhiyun			15 00 02 36 05
274*4882a593Smuzhiyun			15 00 02 37 00
275*4882a593Smuzhiyun			15 00 02 38 3c
276*4882a593Smuzhiyun			15 00 02 39 35
277*4882a593Smuzhiyun			15 00 02 3a 00
278*4882a593Smuzhiyun			15 00 02 3b 40
279*4882a593Smuzhiyun			15 00 02 3c 00
280*4882a593Smuzhiyun			15 00 02 3d 00
281*4882a593Smuzhiyun			15 00 02 3e 00
282*4882a593Smuzhiyun			15 00 02 3f 00
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun			15 00 02 40 00
285*4882a593Smuzhiyun			15 00 02 41 88
286*4882a593Smuzhiyun			15 00 02 42 00
287*4882a593Smuzhiyun			15 00 02 43 00
288*4882a593Smuzhiyun			15 00 02 44 1f
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun			15 00 02 50 01
291*4882a593Smuzhiyun			15 00 02 51 23
292*4882a593Smuzhiyun			15 00 02 52 45
293*4882a593Smuzhiyun			15 00 02 53 67
294*4882a593Smuzhiyun			15 00 02 54 89
295*4882a593Smuzhiyun			15 00 02 55 ab
296*4882a593Smuzhiyun			15 00 02 56 01
297*4882a593Smuzhiyun			15 00 02 57 23
298*4882a593Smuzhiyun			15 00 02 58 45
299*4882a593Smuzhiyun			15 00 02 59 67
300*4882a593Smuzhiyun			15 00 02 5a 89
301*4882a593Smuzhiyun			15 00 02 5b ab
302*4882a593Smuzhiyun			15 00 02 5c cd
303*4882a593Smuzhiyun			15 00 02 5d ef
304*4882a593Smuzhiyun			15 00 02 5e 03
305*4882a593Smuzhiyun			15 00 02 5f 14
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun			15 00 02 60 15
308*4882a593Smuzhiyun			15 00 02 61 0c
309*4882a593Smuzhiyun			15 00 02 62 0d
310*4882a593Smuzhiyun			15 00 02 63 0e
311*4882a593Smuzhiyun			15 00 02 64 0f
312*4882a593Smuzhiyun			15 00 02 65 10
313*4882a593Smuzhiyun			15 00 02 66 11
314*4882a593Smuzhiyun			15 00 02 67 08
315*4882a593Smuzhiyun			15 00 02 68 02
316*4882a593Smuzhiyun			15 00 02 69 0a
317*4882a593Smuzhiyun			15 00 02 6a 02
318*4882a593Smuzhiyun			15 00 02 6b 02
319*4882a593Smuzhiyun			15 00 02 6c 02
320*4882a593Smuzhiyun			15 00 02 6d 02
321*4882a593Smuzhiyun			15 00 02 6e 02
322*4882a593Smuzhiyun			15 00 02 6f 02
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun			15 00 02 70 02
325*4882a593Smuzhiyun			15 00 02 71 02
326*4882a593Smuzhiyun			15 00 02 72 06
327*4882a593Smuzhiyun			15 00 02 73 02
328*4882a593Smuzhiyun			15 00 02 74 02
329*4882a593Smuzhiyun			15 00 02 75 14
330*4882a593Smuzhiyun			15 00 02 76 15
331*4882a593Smuzhiyun			15 00 02 77 0f
332*4882a593Smuzhiyun			15 00 02 78 0e
333*4882a593Smuzhiyun			15 00 02 79 0d
334*4882a593Smuzhiyun			15 00 02 7a 0c
335*4882a593Smuzhiyun			15 00 02 7b 11
336*4882a593Smuzhiyun			15 00 02 7c 10
337*4882a593Smuzhiyun			15 00 02 7d 06
338*4882a593Smuzhiyun			15 00 02 7e 02
339*4882a593Smuzhiyun			15 00 02 7f 0a
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun			15 00 02 80 02
342*4882a593Smuzhiyun			15 00 02 81 02
343*4882a593Smuzhiyun			15 00 02 82 02
344*4882a593Smuzhiyun			15 00 02 83 02
345*4882a593Smuzhiyun			15 00 02 84 02
346*4882a593Smuzhiyun			15 00 02 85 02
347*4882a593Smuzhiyun			15 00 02 86 02
348*4882a593Smuzhiyun			15 00 02 87 02
349*4882a593Smuzhiyun			15 00 02 88 08
350*4882a593Smuzhiyun			15 00 02 89 02
351*4882a593Smuzhiyun			15 00 02 8a 02
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun			39 00 04 ff 98 81 04
354*4882a593Smuzhiyun			15 00 02 00 80
355*4882a593Smuzhiyun			15 00 02 70 00
356*4882a593Smuzhiyun			15 00 02 71 00
357*4882a593Smuzhiyun			15 00 02 66 fe
358*4882a593Smuzhiyun			15 00 02 82 15
359*4882a593Smuzhiyun			15 00 02 84 15
360*4882a593Smuzhiyun			15 00 02 85 15
361*4882a593Smuzhiyun			15 00 02 3a 24
362*4882a593Smuzhiyun			15 00 02 32 ac
363*4882a593Smuzhiyun			15 00 02 8c 80
364*4882a593Smuzhiyun			15 00 02 3c f5
365*4882a593Smuzhiyun			15 00 02 88 33
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun			39 00 04 ff 98 81 01
368*4882a593Smuzhiyun			15 00 02 22 0a
369*4882a593Smuzhiyun			15 00 02 31 00
370*4882a593Smuzhiyun			15 00 02 53 78
371*4882a593Smuzhiyun			15 00 02 50 5b
372*4882a593Smuzhiyun			15 00 02 51 5b
373*4882a593Smuzhiyun			15 00 02 60 20
374*4882a593Smuzhiyun			15 00 02 61 00
375*4882a593Smuzhiyun			15 00 02 62 0d
376*4882a593Smuzhiyun			15 00 02 63 00
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun			15 00 02 a0 00
379*4882a593Smuzhiyun			15 00 02 a1 10
380*4882a593Smuzhiyun			15 00 02 a2 1c
381*4882a593Smuzhiyun			15 00 02 a3 13
382*4882a593Smuzhiyun			15 00 02 a4 15
383*4882a593Smuzhiyun			15 00 02 a5 26
384*4882a593Smuzhiyun			15 00 02 a6 1a
385*4882a593Smuzhiyun			15 00 02 a7 1d
386*4882a593Smuzhiyun			15 00 02 a8 67
387*4882a593Smuzhiyun			15 00 02 a9 1c
388*4882a593Smuzhiyun			15 00 02 aa 29
389*4882a593Smuzhiyun			15 00 02 ab 5b
390*4882a593Smuzhiyun			15 00 02 ac 26
391*4882a593Smuzhiyun			15 00 02 ad 28
392*4882a593Smuzhiyun			15 00 02 ae 5c
393*4882a593Smuzhiyun			15 00 02 af 30
394*4882a593Smuzhiyun			15 00 02 b0 31
395*4882a593Smuzhiyun			15 00 02 b1 2e
396*4882a593Smuzhiyun			15 00 02 b2 32
397*4882a593Smuzhiyun			15 00 02 b3 00
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun			15 00 02 c0 00
400*4882a593Smuzhiyun			15 00 02 c1 10
401*4882a593Smuzhiyun			15 00 02 c2 1c
402*4882a593Smuzhiyun			15 00 02 c3 13
403*4882a593Smuzhiyun			15 00 02 c4 15
404*4882a593Smuzhiyun			15 00 02 c5 26
405*4882a593Smuzhiyun			15 00 02 c6 1a
406*4882a593Smuzhiyun			15 00 02 c7 1d
407*4882a593Smuzhiyun			15 00 02 c8 67
408*4882a593Smuzhiyun			15 00 02 c9 1c
409*4882a593Smuzhiyun			15 00 02 ca 29
410*4882a593Smuzhiyun			15 00 02 cb 5b
411*4882a593Smuzhiyun			15 00 02 cc 26
412*4882a593Smuzhiyun			15 00 02 cd 28
413*4882a593Smuzhiyun			15 00 02 ce 5c
414*4882a593Smuzhiyun			15 00 02 cf 30
415*4882a593Smuzhiyun			15 00 02 d0 31
416*4882a593Smuzhiyun			15 00 02 d1 2e
417*4882a593Smuzhiyun			15 00 02 d2 32
418*4882a593Smuzhiyun			15 00 02 d3 00
419*4882a593Smuzhiyun			39 00 04 ff 98 81 00
420*4882a593Smuzhiyun			05 00 01 11
421*4882a593Smuzhiyun			05 01 01 29
422*4882a593Smuzhiyun		];
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun		panel-exit-sequence = [
425*4882a593Smuzhiyun			05 00 01 28
426*4882a593Smuzhiyun			05 00 01 10
427*4882a593Smuzhiyun		];
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun		display-timings {
430*4882a593Smuzhiyun			native-mode = <&timing1>;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun			timing1: timing1 {
433*4882a593Smuzhiyun				clock-frequency = <64000000>;
434*4882a593Smuzhiyun				hactive = <720>;
435*4882a593Smuzhiyun				vactive = <1280>;
436*4882a593Smuzhiyun				hfront-porch = <40>;
437*4882a593Smuzhiyun				hsync-len = <10>;
438*4882a593Smuzhiyun				hback-porch = <40>;
439*4882a593Smuzhiyun				vfront-porch = <22>;
440*4882a593Smuzhiyun				vsync-len = <4>;
441*4882a593Smuzhiyun				vback-porch = <11>;
442*4882a593Smuzhiyun				hsync-active = <0>;
443*4882a593Smuzhiyun				vsync-active = <0>;
444*4882a593Smuzhiyun				de-active = <0>;
445*4882a593Smuzhiyun				pixelclk-active = <0>;
446*4882a593Smuzhiyun			};
447*4882a593Smuzhiyun		};
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun		ports {
450*4882a593Smuzhiyun			#address-cells = <1>;
451*4882a593Smuzhiyun			#size-cells = <0>;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun			port@0 {
454*4882a593Smuzhiyun				reg = <0>;
455*4882a593Smuzhiyun				panel_in_dsi: endpoint {
456*4882a593Smuzhiyun					remote-endpoint = <&dsi_out_panel>;
457*4882a593Smuzhiyun				};
458*4882a593Smuzhiyun			};
459*4882a593Smuzhiyun		};
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun	};
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun	ports {
464*4882a593Smuzhiyun		#address-cells = <1>;
465*4882a593Smuzhiyun		#size-cells = <0>;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun		port@1 {
468*4882a593Smuzhiyun			reg = <1>;
469*4882a593Smuzhiyun			dsi_out_panel: endpoint {
470*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi>;
471*4882a593Smuzhiyun			};
472*4882a593Smuzhiyun		};
473*4882a593Smuzhiyun	};
474*4882a593Smuzhiyun};
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun&dsi_in_vopb {
477*4882a593Smuzhiyun	status = "okay";
478*4882a593Smuzhiyun};
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun&dsi_in_vopl {
481*4882a593Smuzhiyun	status = "disabled";
482*4882a593Smuzhiyun};
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun&route_dsi {
485*4882a593Smuzhiyun	connect = <&vopb_out_dsi>;
486*4882a593Smuzhiyun	status = "okay";
487*4882a593Smuzhiyun};
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun&cpu0 {
490*4882a593Smuzhiyun	cpu-supply = <&vdd_arm>;
491*4882a593Smuzhiyun};
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun&dfi {
494*4882a593Smuzhiyun	status = "okay";
495*4882a593Smuzhiyun};
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun&dmc {
498*4882a593Smuzhiyun	center-supply = <&vdd_logic>;
499*4882a593Smuzhiyun	status = "okay";
500*4882a593Smuzhiyun};
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun&emmc {
503*4882a593Smuzhiyun	bus-width = <8>;
504*4882a593Smuzhiyun	cap-mmc-highspeed;
505*4882a593Smuzhiyun	mmc-hs200-1_8v;
506*4882a593Smuzhiyun	supports-emmc;
507*4882a593Smuzhiyun	disable-wp;
508*4882a593Smuzhiyun	non-removable;
509*4882a593Smuzhiyun	num-slots = <1>;
510*4882a593Smuzhiyun	status = "okay";
511*4882a593Smuzhiyun};
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun&gmac {
514*4882a593Smuzhiyun	phy-supply = <&vcc_phy>;
515*4882a593Smuzhiyun	clock_in_out = "output";
516*4882a593Smuzhiyun	snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
517*4882a593Smuzhiyun	snps,reset-active-low;
518*4882a593Smuzhiyun	snps,reset-delays-us = <0 50000 50000>;
519*4882a593Smuzhiyun	status = "okay";
520*4882a593Smuzhiyun};
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun&gpu {
523*4882a593Smuzhiyun	mali-supply = <&vdd_logic>;
524*4882a593Smuzhiyun	status = "okay";
525*4882a593Smuzhiyun};
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun&i2c0 {
528*4882a593Smuzhiyun	status = "okay";
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun	rk809: pmic@20 {
531*4882a593Smuzhiyun		compatible = "rockchip,rk809";
532*4882a593Smuzhiyun		reg = <0x20>;
533*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
534*4882a593Smuzhiyun		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
535*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-sleep",
536*4882a593Smuzhiyun				"pmic-power-off", "pmic-reset";
537*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int>;
538*4882a593Smuzhiyun		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
539*4882a593Smuzhiyun		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
540*4882a593Smuzhiyun		pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
541*4882a593Smuzhiyun		rockchip,system-power-controller;
542*4882a593Smuzhiyun		wakeup-source;
543*4882a593Smuzhiyun		#clock-cells = <1>;
544*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
545*4882a593Smuzhiyun		//fb-inner-reg-idxs = <2>;
546*4882a593Smuzhiyun		/* 1: rst regs (default in codes), 0: rst the pmic */
547*4882a593Smuzhiyun		pmic-reset-func = <1>;
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun		vcc1-supply = <&vcc5v0_sys>;
550*4882a593Smuzhiyun		vcc2-supply = <&vcc5v0_sys>;
551*4882a593Smuzhiyun		vcc3-supply = <&vcc5v0_sys>;
552*4882a593Smuzhiyun		vcc4-supply = <&vcc5v0_sys>;
553*4882a593Smuzhiyun		vcc5-supply = <&vcc3v3_sys>;
554*4882a593Smuzhiyun		vcc6-supply = <&vcc3v3_sys>;
555*4882a593Smuzhiyun		vcc7-supply = <&vcc3v3_sys>;
556*4882a593Smuzhiyun		vcc8-supply = <&vcc3v3_sys>;
557*4882a593Smuzhiyun		vcc9-supply = <&vcc5v0_sys>;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun		pwrkey {
560*4882a593Smuzhiyun			status = "okay";
561*4882a593Smuzhiyun		};
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
564*4882a593Smuzhiyun			gpio-controller;
565*4882a593Smuzhiyun			#gpio-cells = <2>;
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun			rk817_slppin_null: rk817_slppin_null {
568*4882a593Smuzhiyun				pins = "gpio_slp";
569*4882a593Smuzhiyun				function = "pin_fun0";
570*4882a593Smuzhiyun			};
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun			rk817_slppin_slp: rk817_slppin_slp {
573*4882a593Smuzhiyun				pins = "gpio_slp";
574*4882a593Smuzhiyun				function = "pin_fun1";
575*4882a593Smuzhiyun			};
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
578*4882a593Smuzhiyun				pins = "gpio_slp";
579*4882a593Smuzhiyun				function = "pin_fun2";
580*4882a593Smuzhiyun			};
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun			rk817_slppin_rst: rk817_slppin_rst {
583*4882a593Smuzhiyun				pins = "gpio_slp";
584*4882a593Smuzhiyun				function = "pin_fun3";
585*4882a593Smuzhiyun			};
586*4882a593Smuzhiyun		};
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun		regulators {
589*4882a593Smuzhiyun			vdd_logic: DCDC_REG1 {
590*4882a593Smuzhiyun				regulator-always-on;
591*4882a593Smuzhiyun				regulator-boot-on;
592*4882a593Smuzhiyun				regulator-min-microvolt = <950000>;
593*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
594*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
595*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
596*4882a593Smuzhiyun				regulator-name = "vdd_logic";
597*4882a593Smuzhiyun				regulator-state-mem {
598*4882a593Smuzhiyun					regulator-on-in-suspend;
599*4882a593Smuzhiyun					regulator-suspend-microvolt = <950000>;
600*4882a593Smuzhiyun				};
601*4882a593Smuzhiyun			};
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun			vdd_arm: DCDC_REG2 {
604*4882a593Smuzhiyun				regulator-always-on;
605*4882a593Smuzhiyun				regulator-boot-on;
606*4882a593Smuzhiyun				regulator-min-microvolt = <950000>;
607*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
608*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
609*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
610*4882a593Smuzhiyun				regulator-name = "vdd_arm";
611*4882a593Smuzhiyun				regulator-state-mem {
612*4882a593Smuzhiyun					regulator-off-in-suspend;
613*4882a593Smuzhiyun					regulator-suspend-microvolt = <950000>;
614*4882a593Smuzhiyun				};
615*4882a593Smuzhiyun			};
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
618*4882a593Smuzhiyun				regulator-always-on;
619*4882a593Smuzhiyun				regulator-boot-on;
620*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
621*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
622*4882a593Smuzhiyun				regulator-state-mem {
623*4882a593Smuzhiyun					regulator-on-in-suspend;
624*4882a593Smuzhiyun				};
625*4882a593Smuzhiyun			};
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun			vcc_3v0: DCDC_REG4 {
628*4882a593Smuzhiyun				regulator-always-on;
629*4882a593Smuzhiyun				regulator-boot-on;
630*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
631*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
632*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
633*4882a593Smuzhiyun				regulator-name = "vcc_3v0";
634*4882a593Smuzhiyun				regulator-state-mem {
635*4882a593Smuzhiyun					regulator-on-in-suspend;
636*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
637*4882a593Smuzhiyun				};
638*4882a593Smuzhiyun			};
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun			vcc_1v0: LDO_REG1 {
641*4882a593Smuzhiyun				regulator-always-on;
642*4882a593Smuzhiyun				regulator-boot-on;
643*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
644*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
645*4882a593Smuzhiyun				regulator-name = "vcc_1v0";
646*4882a593Smuzhiyun				regulator-state-mem {
647*4882a593Smuzhiyun					regulator-on-in-suspend;
648*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
649*4882a593Smuzhiyun				};
650*4882a593Smuzhiyun			};
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun			vcc1v8_soc: LDO_REG2 {
653*4882a593Smuzhiyun				regulator-always-on;
654*4882a593Smuzhiyun				regulator-boot-on;
655*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
656*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun				regulator-name = "vcc1v8_soc";
659*4882a593Smuzhiyun				regulator-state-mem {
660*4882a593Smuzhiyun					regulator-on-in-suspend;
661*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
662*4882a593Smuzhiyun				};
663*4882a593Smuzhiyun			};
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun			vdd1v0_soc: LDO_REG3 {
666*4882a593Smuzhiyun				regulator-always-on;
667*4882a593Smuzhiyun				regulator-boot-on;
668*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
669*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun				regulator-name = "vcc1v0_soc";
672*4882a593Smuzhiyun				regulator-state-mem {
673*4882a593Smuzhiyun					regulator-on-in-suspend;
674*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
675*4882a593Smuzhiyun				};
676*4882a593Smuzhiyun			};
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun			vcc3v0_pmu: LDO_REG4 {
679*4882a593Smuzhiyun				regulator-always-on;
680*4882a593Smuzhiyun				regulator-boot-on;
681*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
682*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun				regulator-name = "vcc3v0_pmu";
685*4882a593Smuzhiyun				regulator-state-mem {
686*4882a593Smuzhiyun					regulator-on-in-suspend;
687*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun				};
690*4882a593Smuzhiyun			};
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun			vccio_sd: LDO_REG5 {
693*4882a593Smuzhiyun				regulator-always-on;
694*4882a593Smuzhiyun				regulator-boot-on;
695*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
696*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun				regulator-name = "vccio_sd";
699*4882a593Smuzhiyun				regulator-state-mem {
700*4882a593Smuzhiyun					regulator-on-in-suspend;
701*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
702*4882a593Smuzhiyun				};
703*4882a593Smuzhiyun			};
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun			vcc_sd: LDO_REG6 {
706*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
707*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
708*4882a593Smuzhiyun				regulator-boot-on;
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun				regulator-name = "vcc_sd";
711*4882a593Smuzhiyun				regulator-state-mem {
712*4882a593Smuzhiyun					regulator-on-in-suspend;
713*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun				};
716*4882a593Smuzhiyun			};
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun			vcc2v8_dvp: LDO_REG7 {
719*4882a593Smuzhiyun				regulator-boot-on;
720*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
721*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun				regulator-name = "vcc2v8_dvp";
724*4882a593Smuzhiyun				regulator-state-mem {
725*4882a593Smuzhiyun					regulator-off-in-suspend;
726*4882a593Smuzhiyun					regulator-suspend-microvolt = <2800000>;
727*4882a593Smuzhiyun				};
728*4882a593Smuzhiyun			};
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun			vcc1v8_dvp: LDO_REG8 {
731*4882a593Smuzhiyun				regulator-boot-on;
732*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
733*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun				regulator-name = "vcc1v8_dvp";
736*4882a593Smuzhiyun				regulator-state-mem {
737*4882a593Smuzhiyun					regulator-on-in-suspend;
738*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
739*4882a593Smuzhiyun				};
740*4882a593Smuzhiyun			};
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun			vdd1v5_dvp: LDO_REG9 {
743*4882a593Smuzhiyun				regulator-boot-on;
744*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
745*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun				regulator-name = "vdd1v5_dvp";
748*4882a593Smuzhiyun				regulator-state-mem {
749*4882a593Smuzhiyun					regulator-off-in-suspend;
750*4882a593Smuzhiyun					regulator-suspend-microvolt = <1500000>;
751*4882a593Smuzhiyun				};
752*4882a593Smuzhiyun			};
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun			vcc3v3_sys: DCDC_REG5 {
755*4882a593Smuzhiyun				regulator-always-on;
756*4882a593Smuzhiyun				regulator-boot-on;
757*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
758*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
759*4882a593Smuzhiyun				regulator-name = "vcc3v3_sys";
760*4882a593Smuzhiyun				regulator-state-mem {
761*4882a593Smuzhiyun					regulator-on-in-suspend;
762*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
763*4882a593Smuzhiyun				};
764*4882a593Smuzhiyun			};
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun			vcc5v0_host: SWITCH_REG1 {
767*4882a593Smuzhiyun				regulator-always-on;
768*4882a593Smuzhiyun				regulator-boot-on;
769*4882a593Smuzhiyun				regulator-name = "vcc5v0_host";
770*4882a593Smuzhiyun			};
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun			vcc3v3_lcd: SWITCH_REG2 {
773*4882a593Smuzhiyun				regulator-boot-on;
774*4882a593Smuzhiyun				regulator-name = "vcc3v3_lcd";
775*4882a593Smuzhiyun			};
776*4882a593Smuzhiyun		};
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun		rk809_codec: codec {
779*4882a593Smuzhiyun			#sound-dai-cells = <0>;
780*4882a593Smuzhiyun			compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
781*4882a593Smuzhiyun			clocks = <&cru SCLK_I2S1_OUT>;
782*4882a593Smuzhiyun			clock-names = "mclk";
783*4882a593Smuzhiyun			pinctrl-names = "default";
784*4882a593Smuzhiyun			pinctrl-0 = <&i2s1_2ch_mclk>;
785*4882a593Smuzhiyun			hp-volume = <20>;
786*4882a593Smuzhiyun			spk-volume = <3>;
787*4882a593Smuzhiyun			status = "okay";
788*4882a593Smuzhiyun		};
789*4882a593Smuzhiyun	};
790*4882a593Smuzhiyun};
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun&i2c1 {
793*4882a593Smuzhiyun	status = "okay";
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun	gt1x: gt1x@14 {
796*4882a593Smuzhiyun		compatible = "goodix,gt1x";
797*4882a593Smuzhiyun		reg = <0x14>;
798*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd>;
799*4882a593Smuzhiyun		goodix,rst-gpio = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
800*4882a593Smuzhiyun		goodix,irq-gpio = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>;
801*4882a593Smuzhiyun	};
802*4882a593Smuzhiyun};
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun&i2c2 {
805*4882a593Smuzhiyun	status = "okay";
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun	clock-frequency = <100000>;
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun	/* These are relatively safe rise/fall times; TODO: measure */
810*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <50>;
811*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <300>;
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun	ov5695: ov5695@36 {
814*4882a593Smuzhiyun		compatible = "ovti,ov5695";
815*4882a593Smuzhiyun		reg = <0x36>;
816*4882a593Smuzhiyun		clocks = <&cru SCLK_CIF_OUT>;
817*4882a593Smuzhiyun		clock-names = "xvclk";
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun		avdd-supply = <&vcc2v8_dvp>;
820*4882a593Smuzhiyun		dovdd-supply = <&vcc1v8_dvp>;
821*4882a593Smuzhiyun		dvdd-supply = <&vdd1v5_dvp>;
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun		/*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/
824*4882a593Smuzhiyun		pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
825*4882a593Smuzhiyun		pinctrl-names = "default";
826*4882a593Smuzhiyun		pinctrl-0 = <&cif_clkout_m0>;
827*4882a593Smuzhiyun		port {
828*4882a593Smuzhiyun			ucam_out: endpoint {
829*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam>;
830*4882a593Smuzhiyun				data-lanes = <1 2>;
831*4882a593Smuzhiyun			};
832*4882a593Smuzhiyun		};
833*4882a593Smuzhiyun	};
834*4882a593Smuzhiyun};
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun&i2s1_2ch {
837*4882a593Smuzhiyun	status = "okay";
838*4882a593Smuzhiyun	#sound-dai-cells = <0>;
839*4882a593Smuzhiyun};
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun&io_domains {
842*4882a593Smuzhiyun	status = "okay";
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun	vccio1-supply = <&vcc_3v0>;
845*4882a593Smuzhiyun	vccio2-supply = <&vccio_sd>;
846*4882a593Smuzhiyun	vccio3-supply = <&vcc_3v0>;
847*4882a593Smuzhiyun	vccio4-supply = <&vcc3v0_pmu>;
848*4882a593Smuzhiyun	vccio5-supply = <&vcc_3v0>;
849*4882a593Smuzhiyun};
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun&isp_mmu {
852*4882a593Smuzhiyun	status = "okay";
853*4882a593Smuzhiyun};
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun&mipi_dphy_rx0 {
856*4882a593Smuzhiyun	status = "okay";
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun	ports {
859*4882a593Smuzhiyun		#address-cells = <1>;
860*4882a593Smuzhiyun		#size-cells = <0>;
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun		port@0 {
863*4882a593Smuzhiyun			reg = <0>;
864*4882a593Smuzhiyun			#address-cells = <1>;
865*4882a593Smuzhiyun			#size-cells = <0>;
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun			mipi_in_ucam: endpoint@1 {
868*4882a593Smuzhiyun				reg = <1>;
869*4882a593Smuzhiyun				remote-endpoint = <&ucam_out>;
870*4882a593Smuzhiyun				data-lanes = <1 2>;
871*4882a593Smuzhiyun			};
872*4882a593Smuzhiyun		};
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun		port@1 {
875*4882a593Smuzhiyun			reg = <1>;
876*4882a593Smuzhiyun			#address-cells = <1>;
877*4882a593Smuzhiyun			#size-cells = <0>;
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun			dphy_rx0_out: endpoint@0 {
880*4882a593Smuzhiyun				reg = <0>;
881*4882a593Smuzhiyun				remote-endpoint = <&isp0_mipi_in>;
882*4882a593Smuzhiyun			};
883*4882a593Smuzhiyun		};
884*4882a593Smuzhiyun	};
885*4882a593Smuzhiyun};
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun&nandc0 {
888*4882a593Smuzhiyun	status = "okay";
889*4882a593Smuzhiyun};
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun&pmu_io_domains {
892*4882a593Smuzhiyun	status = "okay";
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun	pmuio1-supply = <&vcc3v0_pmu>;
895*4882a593Smuzhiyun	pmuio2-supply = <&vcc3v0_pmu>;
896*4882a593Smuzhiyun};
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun&pwm1 {
899*4882a593Smuzhiyun	status = "okay";
900*4882a593Smuzhiyun};
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun&rk_rga {
903*4882a593Smuzhiyun	status = "okay";
904*4882a593Smuzhiyun};
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun&rkisp1 {
907*4882a593Smuzhiyun	status = "okay";
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun	port {
910*4882a593Smuzhiyun		#address-cells = <1>;
911*4882a593Smuzhiyun		#size-cells = <0>;
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun		isp0_mipi_in: endpoint@0 {
914*4882a593Smuzhiyun			reg = <0>;
915*4882a593Smuzhiyun			remote-endpoint = <&dphy_rx0_out>;
916*4882a593Smuzhiyun		};
917*4882a593Smuzhiyun	};
918*4882a593Smuzhiyun};
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun&rockchip_suspend {
921*4882a593Smuzhiyun	status = "okay";
922*4882a593Smuzhiyun	rockchip,sleep-debug-en = <1>;
923*4882a593Smuzhiyun};
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun&saradc {
926*4882a593Smuzhiyun	status = "okay";
927*4882a593Smuzhiyun	vref-supply = <&vcc1v8_soc>;
928*4882a593Smuzhiyun};
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun&sdmmc {
931*4882a593Smuzhiyun	bus-width = <4>;
932*4882a593Smuzhiyun	cap-mmc-highspeed;
933*4882a593Smuzhiyun	cap-sd-highspeed;
934*4882a593Smuzhiyun	supports-sd;
935*4882a593Smuzhiyun	card-detect-delay = <800>;
936*4882a593Smuzhiyun	ignore-pm-notify;
937*4882a593Smuzhiyun	/*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/
938*4882a593Smuzhiyun	sd-uhs-sdr12;
939*4882a593Smuzhiyun	sd-uhs-sdr25;
940*4882a593Smuzhiyun	sd-uhs-sdr50;
941*4882a593Smuzhiyun	sd-uhs-sdr104;
942*4882a593Smuzhiyun	vqmmc-supply = <&vccio_sd>;
943*4882a593Smuzhiyun	vmmc-supply = <&vcc_sd>;
944*4882a593Smuzhiyun	status = "okay";
945*4882a593Smuzhiyun};
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun&sdio {
948*4882a593Smuzhiyun	bus-width = <4>;
949*4882a593Smuzhiyun	cap-sd-highspeed;
950*4882a593Smuzhiyun	supports-sdio;
951*4882a593Smuzhiyun	ignore-pm-notify;
952*4882a593Smuzhiyun	keep-power-in-suspend;
953*4882a593Smuzhiyun	non-removable;
954*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
955*4882a593Smuzhiyun	sd-uhs-sdr104;
956*4882a593Smuzhiyun	status = "okay";
957*4882a593Smuzhiyun};
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun&tsadc {
960*4882a593Smuzhiyun	pinctrl-names = "gpio", "otpout";
961*4882a593Smuzhiyun	pinctrl-0 = <&tsadc_otp_gpio>;
962*4882a593Smuzhiyun	pinctrl-1 = <&tsadc_otp_out>;
963*4882a593Smuzhiyun	status = "okay";
964*4882a593Smuzhiyun};
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun&uart1 {
967*4882a593Smuzhiyun	pinctrl-names = "default";
968*4882a593Smuzhiyun	pinctrl-0 = <&uart1_xfer &uart1_cts>;
969*4882a593Smuzhiyun	status = "okay";
970*4882a593Smuzhiyun};
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun&u2phy {
973*4882a593Smuzhiyun	status = "okay";
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun	u2phy_host: host-port {
976*4882a593Smuzhiyun		status = "okay";
977*4882a593Smuzhiyun		phy-supply = <&vcc5v0_host_vbus>;
978*4882a593Smuzhiyun	};
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun	u2phy_otg: otg-port {
981*4882a593Smuzhiyun		status = "okay";
982*4882a593Smuzhiyun	};
983*4882a593Smuzhiyun};
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun&usb20_otg {
986*4882a593Smuzhiyun	status = "okay";
987*4882a593Smuzhiyun};
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun&usb_host0_ehci {
990*4882a593Smuzhiyun	status = "okay";
991*4882a593Smuzhiyun};
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun&usb_host0_ohci {
994*4882a593Smuzhiyun	status = "okay";
995*4882a593Smuzhiyun};
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun&vopb {
998*4882a593Smuzhiyun	status = "okay";
999*4882a593Smuzhiyun};
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun&vopb_mmu {
1002*4882a593Smuzhiyun	status = "okay";
1003*4882a593Smuzhiyun};
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun&vopl {
1006*4882a593Smuzhiyun	status = "okay";
1007*4882a593Smuzhiyun};
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun&vopl_mmu {
1010*4882a593Smuzhiyun	status = "okay";
1011*4882a593Smuzhiyun};
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun&mpp_srv {
1014*4882a593Smuzhiyun	status = "okay";
1015*4882a593Smuzhiyun};
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun&vdpu {
1018*4882a593Smuzhiyun	status = "okay";
1019*4882a593Smuzhiyun};
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun&vepu {
1022*4882a593Smuzhiyun	status = "okay";
1023*4882a593Smuzhiyun};
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun&vpu_mmu {
1026*4882a593Smuzhiyun	status = "okay";
1027*4882a593Smuzhiyun};
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun&hevc {
1030*4882a593Smuzhiyun	status = "okay";
1031*4882a593Smuzhiyun};
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun&hevc_mmu {
1034*4882a593Smuzhiyun	status = "okay";
1035*4882a593Smuzhiyun};
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun&pinctrl {
1038*4882a593Smuzhiyun	headphone {
1039*4882a593Smuzhiyun		hp_det: hp-det {
1040*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
1041*4882a593Smuzhiyun		};
1042*4882a593Smuzhiyun	};
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun	pmic {
1045*4882a593Smuzhiyun		pmic_int: pmic_int {
1046*4882a593Smuzhiyun			rockchip,pins =
1047*4882a593Smuzhiyun				<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
1048*4882a593Smuzhiyun		};
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun		soc_slppin_gpio: soc_slppin_gpio {
1051*4882a593Smuzhiyun			rockchip,pins =
1052*4882a593Smuzhiyun				<0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
1053*4882a593Smuzhiyun		};
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun		soc_slppin_slp: soc_slppin_slp {
1056*4882a593Smuzhiyun			rockchip,pins =
1057*4882a593Smuzhiyun				<0 RK_PA4 1 &pcfg_pull_none>;
1058*4882a593Smuzhiyun		};
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun		soc_slppin_rst: soc_slppin_rst {
1061*4882a593Smuzhiyun			rockchip,pins =
1062*4882a593Smuzhiyun				<0 RK_PA4 2 &pcfg_pull_none>;
1063*4882a593Smuzhiyun		};
1064*4882a593Smuzhiyun	};
1065*4882a593Smuzhiyun
1066*4882a593Smuzhiyun	sdio-pwrseq {
1067*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
1068*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
1069*4882a593Smuzhiyun		};
1070*4882a593Smuzhiyun	};
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun	usb {
1073*4882a593Smuzhiyun		host_vbus_drv: host-vbus-drv {
1074*4882a593Smuzhiyun			rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1075*4882a593Smuzhiyun		};
1076*4882a593Smuzhiyun	};
1077*4882a593Smuzhiyun};
1078