1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun chosen: chosen { 9*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff130000 kpti=0 coherent_pool=1m"; 10*4882a593Smuzhiyun }; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun fiq-debugger { 13*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 14*4882a593Smuzhiyun rockchip,serial-id = <2>; 15*4882a593Smuzhiyun rockchip,signal-irq = <159>; 16*4882a593Smuzhiyun rockchip,wake-irq = <0>; 17*4882a593Smuzhiyun /* If enable uart uses irq instead of fiq */ 18*4882a593Smuzhiyun rockchip,irq-mode-enable = <0>; 19*4882a593Smuzhiyun rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 20*4882a593Smuzhiyun interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 21*4882a593Smuzhiyun status = "okay"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun firmware { 25*4882a593Smuzhiyun firmware_android: android {}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun optee: optee { 28*4882a593Smuzhiyun compatible = "linaro,optee-tz"; 29*4882a593Smuzhiyun method = "smc"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun reserved-memory { 34*4882a593Smuzhiyun #address-cells = <2>; 35*4882a593Smuzhiyun #size-cells = <2>; 36*4882a593Smuzhiyun ranges; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun drm_logo: drm-logo@00000000 { 39*4882a593Smuzhiyun compatible = "rockchip,drm-logo"; 40*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x0>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun ramoops: ramoops@110000 { 44*4882a593Smuzhiyun compatible = "ramoops"; 45*4882a593Smuzhiyun reg = <0x0 0x110000 0x0 0xf0000>; 46*4882a593Smuzhiyun record-size = <0x20000>; 47*4882a593Smuzhiyun console-size = <0x80000>; 48*4882a593Smuzhiyun ftrace-size = <0x00000>; 49*4882a593Smuzhiyun pmsg-size = <0x50000>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun secure_memory: secure-memory@20000000 { 53*4882a593Smuzhiyun compatible = "rockchip,secure-memory"; 54*4882a593Smuzhiyun reg = <0x0 0x20000000 0x0 0x0>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* global autoconfigured region for contiguous allocations */ 58*4882a593Smuzhiyun linux,cma { 59*4882a593Smuzhiyun compatible = "shared-dma-pool"; 60*4882a593Smuzhiyun reusable; 61*4882a593Smuzhiyun size = <0x0 0x2000000>; 62*4882a593Smuzhiyun linux,cma-default; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun}; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun&display_subsystem { 68*4882a593Smuzhiyun logo-memory-region = <&drm_logo>; 69*4882a593Smuzhiyun status = "okay"; 70*4882a593Smuzhiyun secure-memory-region = <&secure_memory>; 71*4882a593Smuzhiyun route { 72*4882a593Smuzhiyun route_hdmi: route-hdmi { 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 75*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 76*4882a593Smuzhiyun logo,mode = "fullscreen"; 77*4882a593Smuzhiyun charge_logo,mode = "fullscreen"; 78*4882a593Smuzhiyun connect = <&vop_out_hdmi>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun route_tve: route-tve { 81*4882a593Smuzhiyun status = "okay"; 82*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 83*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 84*4882a593Smuzhiyun logo,mode = "fullscreen"; 85*4882a593Smuzhiyun charge_logo,mode = "fullscreen"; 86*4882a593Smuzhiyun connect = <&vop_out_tve>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun}; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun&rng { 92*4882a593Smuzhiyun status = "okay"; 93*4882a593Smuzhiyun}; 94
