1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "px30.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun&cru { 9*4882a593Smuzhiyun assigned-clocks = <&cru PLL_NPLL>; 10*4882a593Smuzhiyun assigned-clock-rates = <1040000000>; 11*4882a593Smuzhiyun}; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun&display_subsystem { 14*4882a593Smuzhiyun ports = <&vopb_out>; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun&gpu_opp_table { 18*4882a593Smuzhiyun opp-520000000 { 19*4882a593Smuzhiyun opp-hz = /bits/ 64 <520000000>; 20*4882a593Smuzhiyun opp-microvolt = <1175000>; 21*4882a593Smuzhiyun opp-microvolt-L0 = <1175000>; 22*4882a593Smuzhiyun opp-microvolt-L1 = <1150000>; 23*4882a593Smuzhiyun opp-microvolt-L2 = <1100000>; 24*4882a593Smuzhiyun opp-microvolt-L3 = <1050000>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun&rgb { 29*4882a593Smuzhiyun phys = <&video_phy>; 30*4882a593Smuzhiyun phy-names = "phy"; 31*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 32*4882a593Smuzhiyun pinctrl-0 = <&lcdc_m1_rgb_pins>; 33*4882a593Smuzhiyun pinctrl-1 = <&lcdc_m1_sleep_pins>; 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun&pinctrl { 37*4882a593Smuzhiyun lcdc { 38*4882a593Smuzhiyun lcdc_m1_rgb_pins: lcdc-m1-rgb-pins { 39*4882a593Smuzhiyun rockchip,pins = 40*4882a593Smuzhiyun <3 RK_PA0 1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ 41*4882a593Smuzhiyun <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ 42*4882a593Smuzhiyun <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ 43*4882a593Smuzhiyun <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ 44*4882a593Smuzhiyun <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ 45*4882a593Smuzhiyun <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ 46*4882a593Smuzhiyun <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ 47*4882a593Smuzhiyun <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ 48*4882a593Smuzhiyun <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ 49*4882a593Smuzhiyun <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ 50*4882a593Smuzhiyun <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ 51*4882a593Smuzhiyun <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ 52*4882a593Smuzhiyun <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ 53*4882a593Smuzhiyun <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ 54*4882a593Smuzhiyun <3 RK_PD0 1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ 55*4882a593Smuzhiyun <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ 56*4882a593Smuzhiyun <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ 57*4882a593Smuzhiyun <3 RK_PD3 1 &pcfg_pull_none_8ma>; /* LCDC_D23 */ 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun lcdc_m1_sleep_pins: lcdc-m1-sleep-pins { 61*4882a593Smuzhiyun rockchip,pins = 62*4882a593Smuzhiyun <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ 63*4882a593Smuzhiyun <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ 64*4882a593Smuzhiyun <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ 65*4882a593Smuzhiyun <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ 66*4882a593Smuzhiyun <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ 67*4882a593Smuzhiyun <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ 68*4882a593Smuzhiyun <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ 69*4882a593Smuzhiyun <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ 70*4882a593Smuzhiyun <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ 71*4882a593Smuzhiyun <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ 72*4882a593Smuzhiyun <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ 73*4882a593Smuzhiyun <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ 74*4882a593Smuzhiyun <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ 75*4882a593Smuzhiyun <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ 76*4882a593Smuzhiyun <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ 77*4882a593Smuzhiyun <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ 78*4882a593Smuzhiyun <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ 79*4882a593Smuzhiyun <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */ 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun/delete-node/ &dsi_in_vopl; 85*4882a593Smuzhiyun/delete-node/ &lvds_vopl_in; 86*4882a593Smuzhiyun/delete-node/ &rgb_in_vopl; 87*4882a593Smuzhiyun/delete-node/ &vopl; 88*4882a593Smuzhiyun/delete-node/ &vopl_mmu; 89